CN113496729A - Read circuit for magnetic random access memory - Google Patents
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- CN113496729A CN113496729A CN202010190163.6A CN202010190163A CN113496729A CN 113496729 A CN113496729 A CN 113496729A CN 202010190163 A CN202010190163 A CN 202010190163A CN 113496729 A CN113496729 A CN 113496729A
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- 230000005291 magnetic effect Effects 0.000 title claims abstract description 74
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
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- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1697—Power supply circuits
Abstract
A read circuit of Magnetic Random Access Memory (MRAM) is used for reading a preceding-stage read circuit of magnetic storage unit information of the MRAM, a read path load tube is used for providing reference current of read operation to a magnetic storage unit to be tested; the access transistor is connected in series with the read path load tube, the other end of the access transistor is electrically connected with one end of the magnetic tunnel junction, and under the given word line voltage bias, the access transistor is arranged in a saturation region to form a common grid amplifier. Therefore, the read voltage of the amplified output is formed by the connection node of the read path load tube and the access transistor, and the read voltage and the reference voltage are used as the input of the next-stage voltage sensitive amplifier of the read path together. Therefore, the number of transistors used by a front-stage reading path is reduced, and the whole area of a chip is reduced. Meanwhile, the design of the reading circuit also reduces the power supply voltage margin occupied by components on the reading channel, thereby reducing the operable voltage.
Description
Technical Field
The invention relates to the field of magnetic random access memories, in particular to a design scheme of a front stage of a reading circuit for reading information of a magnetic storage unit of a magnetic random access memory.
Background
In recent years, Magnetic Random Access Memory (MRAM) using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile Memory, which has the characteristics of high speed read and write, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures in which there is a Free magnetic Layer (FL) that can change the magnetization direction to record different data; a Tunnel Barrier Layer (TBL) in the middle; a magnetic Reference Layer (RL) is located on the other side of the tunnel barrier Layer, with its magnetization direction unchanged.
To be able to record information in such magnetoresistive components, a writing method based on Spin momentum Transfer or Spin Transfer Torque (STT) conversion technology is used, and such an MRAM is called STT-MRAM. STT-MRAM is further classified into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM), which have better performance depending on the direction of magnetic polarization. In a Magnetic Tunnel Junction (MTJ) having Perpendicular Anisotropy (PMA), as a free layer for storing information, there are two magnetization directions in the Perpendicular direction, that is: up and down, corresponding to "0" and "1" or "1" and "0" in the binary, respectively.
Magnetic Random Access Memory (MRAM) is used as a type of non-volatile memory in integrated circuits of electronic devices and provides data storage functionality, where data is stored by programming a Magnetic Tunnel Junction (MTJ) that is part of an MRAM bit cell. An advantage of a Magnetic Random Access Memory (MRAM) is that a bit cell of a Magnetic Tunnel Junction (MTJ) can normally maintain stored information even in a power-off state because data is stored as a magnetic element in the Magnetic Tunnel Junction (MTJ).
The process of reading the MRAM is to measure the resistance of the MTJ. Using the newer STT-MRAM technology, writing to MRAM is also simpler: write operations are performed through the MTJ using a stronger current than read. A bottom-up current sets the variable magnetization layer in a direction parallel to the fixed layer, and a top-down current sets it in an anti-parallel direction.
The most basic Magnetic Random Access Memory (MRAM) cell consists of a Magnetic Tunnel Junction (MTJ) and an access transistor. The Gate (Gate) of the access transistor is connected to the Word Line (WL) of the chip to switch this access transistor on or off, the Magnetic Tunnel Junction (MTJ) and the access transistor are connected in series on the Bit Line (BL) of the chip, and the read and write operations are performed on the Bit Line (BL). The Source (Source) of the access transistor is connected to the Source Line (SL) of the chip.
A Magnetic Random Access Memory (MRAM) chip is composed of one or more arrays of MRAM memory cells, each array having external circuits such as a row address decoder for changing a received address to a selection of Word Lines (WL), a column address decoder for changing a received address to a selection of Bit Lines (BL), a read/write controller for controlling read (measure) write (current-applying) operations on the Bit Lines (BL), and an input/output controller for exchanging data with the outside. Most of the read-write circuits in the prior art are independent and separated, and different circuit designs are adopted during read and write operations.
The read-out circuit of the MRAM needs to detect the resistance of the MRAM memory cell MTJ. Since the resistance of the MTJ drifts with temperature or the like, a general method is to use some memory cells on a chip that have been written in a high resistance state or a low resistance state as reference cells, and then compare the resistance of the memory cells and the reference cells using a sense amplifier (sense amplifier).
The read process of an MRAM is the detection and comparison of the resistance of the memory cell. Whether the memory cell (MTJ) is in a high resistance state or a low resistance state is generally determined by combining a plurality of reference cells into a standard resistance to compare with the memory cell (MTJ).
The reading circuit is divided into a front part and a rear part, and the front part firstly converts the difference of two resistors (the resistance of the memory cell to be tested and the reference standard resistor) into an analog voltage signal. Fig. 1 is a schematic diagram of a previous stage of a readout circuit of a typical magnetic random access memory, which is obtained from US 08693273. In the circuit design, the load tubes P1, P2 and P3 of the read path which work as current sources are the same PMOS tube to form a current mirror, and the same read current I is provided for each pathread. The clamp transistors N1, N2 and N3 are the same NMOS transistor, and the difference of the resistances is amplified and converted into a voltage difference Vsense-VrefThe input voltage is input to a Sense Amplifier (Sense Amplifier) in the subsequent stage of the Sense circuit. Wherein the clamping voltage VclampThe resistance of NMOS transistors such as N1, N2 and N3 is controlled, thereby protecting the storage reference unit MTJREF_APAnd MTJREF_PStability is not affected by the application of high voltage, and solid is generally adoptedAnd (4) fixing the voltage. The access transistors N4, N5 and N6 are NMOS transistors for turning on or off the MTJ of the designated memory cellREF_APAnd MTJREF_PTo access (c). The embodiment in FIG. 1 is a way of memory cell, comparing a way of reference cell in P state (low resistance state) with a way of reference cell in AP state (high resistance state) in MTJREF_PAnd MTJREF_AP. In actual use, multiple paths of memory cells can be used for comparing m paths of AP state and n paths of P state reference cells which are connected in parallel.
The latter stage of the reading circuit further amplifies the analog signal output by the former stage into a digital signal. In order to improve the yield of Magnetic Random Access Memories (MRAMs), a differential amplifier is generally used in a post-stage amplifier for distinguishing a slight voltage signal difference output from a pre-stage so as to correctly read a few memory cells having a relatively large deviation from a central value.
However, even if a differential amplifier is used, the manufacturing process is inevitable to cause component deviation, which causes the output signal of the read path at the front stage to deviate, and consequently causes the error of the storage state of the read unit. This variation is mainly due to variations in the fabrication process over the clamp transistors (e.g., N1, N2, and N3 in fig. 1). To reduce the variation, these MOS transistors are often made large, occupying chip area and increasing cost.
On the other hand, in the known design, clamp transistors N1, N2, and N3(NMOS) are set to operate in the saturation amplification region. Bias voltage V between source and drain of MOS transistordsAt least needs to be larger than its overdrive voltage Vd,SAT.. Therefore, certain power supply voltage margin is occupied, and the requirement of the circuit on working voltage is improved.
Disclosure of Invention
In order to solve the problems of the prior art, the present invention provides a readout circuit of a Magnetic Random Access Memory (MRAM) that amplifies and reads the state of a memory cell to be tested using the signal amplification characteristics of an access transistor of the memory cell itself. Thus, the reading operation of the memory cell is realized with smaller circuit area and lower operable voltage.
The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme. A read circuit of a magnetic random access memory, a preceding stage read circuit for reading information of a magnetic memory cell of the magnetic random access memory, the magnetic memory cell comprising a magnetic tunnel junction and an access transistor, wherein a read path load tube is used for providing a reference current of a read operation to the magnetic memory cell to be tested; the access transistor of the magnetic storage unit is connected with the read path load tube in series, the other end of the access transistor is electrically connected with one end of the magnetic tunnel junction, and under the bias of given word line voltage, the access transistor is arranged in a saturation area to form a common grid amplifier. Therefore, the read voltage of the amplified output is formed by the connection node of the read path load tube and the access transistor, and the read voltage and the reference voltage are used as the input of the next-stage voltage sensitive amplifier of the read path together.
In an embodiment of the present application, the read path load transistor is a P-channel metal oxide semiconductor field effect transistor (PMOS), the access transistor is an N-channel metal oxide semiconductor field effect transistor (MOS) transistor (NMOS), and a drain of the access transistor is coupled to a drain of the read path load transistor, a source of the access transistor is coupled to one end of the magnetic tunnel junction.
In the embodiment of the application, the reference voltage can be formed by connecting a plurality of magnetic tunnel junction reference memory cells which are preset to be a parallel-state resistor (Rp) and an anti-parallel-state resistor (Rap) in parallel to form a standard resistor under a given reading current; or the reference voltage may be generated by configuring a high precision thin film resistor at a given read current.
In the embodiment of the application, the voltage sensitive amplifier compares the input reading voltage with the reference voltage, and then a latch receives the comparison result and converts the comparison result into a digital signal, thereby completing the reading operation of the resistance state information of the selected magnetic storage unit.
The scheme of the read-out circuit of the magnetic random access memory is used for reading the preceding-stage read-out circuit of the magnetic storage unit information of the magnetic random access memory, and the read-out circuit is used as a gating switch and an amplifier to amplify and read the state of a storage unit to be detected by utilizing the signal amplification characteristic of an access transistor of the storage unit. This reduces the number of metal-oxide-semiconductor (MOS) transistors used in the previous read path. In the design of an actual memory chip, a plurality of read paths are often configured for a complete memory array, and the technology of the invention can reduce the whole area of the chip. In addition, the access NMOS transistor of the memory unit is multiplexed, so that the power supply voltage margin occupied by components on a read path is reduced, and the operable voltage is reduced.
Drawings
FIG. 1 is a diagram of the previous stages of a typical MRAM read circuit.
FIG. 2 is a diagram of a read circuit of the magnetic random access memory according to the present invention.
Fig. 3 is a schematic diagram of a readout circuit according to an embodiment of the present invention.
FIG. 4 is a graph of the sensitivity of the circuit amplifier versus the gate voltage of the access transistor (NMOS) in an embodiment of the present invention.
FIG. 5 is a timing diagram illustrating the operation of the circuit according to the present invention.
Description of the symbols
Read path load transistors P1, P2, P3, clamp transistors N1, N2, N3, access transistors N4, N5, N6, memory cell MTJ to be tested, memory reference cell MTJREF_AP、MTJREF_P。
Preceding stage sensing circuit 100, voltage sense amplifier 200, latch 300, magnetic tunnel junction MTJ, MTJREFAccess transistors N10, N20, read path load transistors P10, P20, digital Data, pass gate switches T1, T2, T3, T4.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of the present invention and the above-described drawings, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 2, a schematic diagram of a read circuit of a magnetic random access memory according to the present invention is shown, wherein a design of a read path front stage mainly includes a front stage read circuit 100 for reading information of a magnetic memory cell of a Magnetic Random Access Memory (MRAM), the magnetic memory cell includes a magnetic tunnel junction MTJ and an access transistor N10, and a read path load tube P10 is used for providing a reference current for a read operation to a magnetic memory cell to be tested; the access transistor N10 of the magnetic memory cell is serially connected to the read path load transistor P10, and the other end of the access transistor N10 is electrically connected to one end of the MTJ and is under a given word line voltage VWLUnder bias, the access transistor N10 is placed in the saturation region, taking advantage of the signal amplification characteristics of the access transistor N10, which itself acts as an access switch, as well as acting as a gating switch and amplifier. The read voltage V of the amplified output is formed by the connection node of the read path load tube P10 and the access transistor N10senseThe read voltage VsenseAnd a reference voltage VrefTogether as inputs to the next stage voltage sense amplifier 200 of the read path.
The read path load transistor P10 is a P-channel metal-oxide-semiconductor field effect transistor (PMOS), the access transistor N10 is an N-channel metal-oxide-semiconductor field effect (MOS) transistor (NMOS), and the drain of the access transistor N10 is coupled to the drain of the read path load transistor P10, the source of the access transistor N10 is coupled to one end of the magnetic tunnel junction MTJ.
Under the bias of a given voltage Vp, a read path load tube P10 of the PMOS tubeProviding a reference current I for MTJ read operationsread. At a given word line voltage VWLUnder bias, the access transistor N10 of the NMOS transistor is set in the saturation region. The front stage of the sensing circuit is configured as a classical common-gate amplifier, the output V of which issenseAnd the reference voltage Vref together as an input to the next stage voltage sense amplifier 200 of the read path.
In the embodiments of the present application, the reference voltage VrefAt a given read current IreadNext, a plurality of reference magnetic tunnel junction reference memory cells previously set as a parallel state resistance (Rp) and an antiparallel state resistance (Rap) are connected in parallel to form a standard resistance; or the reference voltage VrefAt a given read current IreadNext, it is produced by arranging a high-precision thin-film resistor. The Magnetic Tunnel Junction (MTJ) is configured in a P parallel state and an AP antiparallel state, wherein the P state is 0, the AP state is 1, the parallel state resistance is Rp, and the antiparallel state resistance is Rap.
In implementation, the voltage sense amplifier 200 will input a read voltage VsenseAnd a reference voltage VrefAfter the size comparison is completed, a latch 300 receives the comparison result and converts the comparison result into a digital signal Data, thereby completing the reading operation of the configuration (the "P" state or the "AP" state) information of the selected magnetic memory cell.
The following provides a specific embodiment of the present invention to further illustrate the circuit design principle. Referring to fig. 3, a schematic diagram of a readout circuit according to the present invention is shown, and fig. 4 is a graph of a relationship between a circuit amplification sensitivity and a gate voltage of an access transistor (NMOS).
Take the example of a Magnetic Random Access Memory (MRAM) array that selects the ith row and the jth column as the target memory cell. In one embodiment, the pre-read path comprises a current mirror, a transmission gate switch, a memory cell to be tested (including a Magnetic Tunnel Junction (MTJ) and an access transistor N10), and a transistor for generating VrefReference cell for signal (including magnetic tunnel junction MTJ)REFAnd access transistor N20). The load transistors P10 and P20 are the same PMOS transistors forming a current mirrorProviding a read current Iread. The transmission gate switches T1, T2, T3 and T4 are identical complementary Metal Oxide Semiconductor (MOS) transmission gates, which are switching tubes of a column decoder to gate the jth column in the memory array and the corresponding reference cell column. The access transistors N10 and N20 are the same NMOS transistor, multiplexed in the present invention as the switching transistor (row i in the gated array) and signal amplifier of the memory cell. MTJ (magnetic tunnel junction)REFIs a reference standard resistance, set to 6.5KOhm in the example. The voltage sensitive amplifier 200 and the phase lock device 300 are used as the back stage of the reading circuit, and the analog voltage signal V input by the front stage is usedsense-VrefAmplifying and converting the Data into a digital signal Data to finish the reading operation of the resistance state information of the Magnetic Tunnel Junction (MTJ) of the storage unit to be tested.
Word line voltage VWL[i]The choice of bias determines the operating region and amplification characteristics of the access transistors N10 and N20, i.e., the sensitivity of the sense preamplifier. By modulating the word line voltage VWL[i]So that the MOS transistors of the switching transistors N10 and N20 operate in a saturation region while satisfying VsenseWhen the resistances at the upper and lower nodes are approximately equal, the sensitivity of the preceding stage circuit approaches the maximum value. As shown in FIG. 4, in the MTJREF＝6.5K，VWL[i]At 0.9V, the NMOS transistor operates in the Saturation amplification region (Saturation region), and the circuit sensitivity is 0.15mV/Ohm, which is close to the optimum value. When V isWL[i]When 1.2V, the NMOS transistor operates in a Linear region (Linear region), and has no amplification characteristic and low circuit sensitivity. The standard voltage VBL bias may be set to the power supply voltage VDD or lower. Logic signal Bit [ j ]]The level is set to VDD or GND for turning on or off the pass-gate switches T1, T2, T3 and T4.
FIG. 5 is a timing diagram illustrating the operation of the circuit according to the present invention. When the logic signal Bit [ j ]]At high, pass gate switches T1, T2, T3 and T4 are turned on, the jth column in the memory array and the corresponding reference voltage V for generating the reference voltagerefIs selected. Then the standard voltage VBL and the word line voltage VWL[i]Are sequentially set to high level, and the ith row of memory cells is selected. On the subsequent read path, reference read current IreadAnd (4) generating.At this moment, the difference between the resistance of the cell to be tested and the reference resistance is amplified and converted into a voltage difference V by the access transistors N10 and N20out＝Vsense-Vref. When V isoutAfter the signal is stable, the enable signal D1 of the voltage sense amplifier 200 is set to high level, the voltage sense amplifier 200 further amplifies the analog output signal of the previous stage of the read path, and sends the comparison result to the latch 300. When the enable signal D2 is high, the latch 300 converts the input signal into the digital signal Data. If the magnetic tunnel junction MTJ is RpState, therefore Vsense–Vref<0, the resulting digital signal Data is at a low level (Read "0"). If the magnetic tunnel junction MTJ is RapState, therefore Vsense–Vref>0, the resultant digital signal Data is at a high level (Read "1").
Overall, compared with the design of the prior stage of the current readout circuit, the present invention has the following advantages. 1. Smaller circuit area and reduced cost. In contrast to the technology of US Patent 08693273, the present invention does not use a clamp transistor of larger size, but rather multiplexes the access transistor of the memory cell itself as both a cell gating switch and an amplifier to amplify the difference between the memory cell resistance and the reference standard resistance. This reduces the number of transistors (NMOS) used in the preceding read path. More importantly, in the design of practical Magnetic Random Access Memory (MRAM) chips, multiple read paths are often provided for a complete memory array. The implementation of the design of the invention will reduce the overall area of the chip. 2. And the lower operable voltage can reduce power consumption. As described above, compared with the prior art, the present invention reduces the power supply voltage margin occupied by the components on the read path due to the multiplexing of the access transistors of the memory cells, thereby reducing the operable voltage.
The terms "in one embodiment" and "in various embodiments" of the present application are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.
Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (6)
1. A read circuit for a magnetic random access memory, a preceding read circuit for reading information from a magnetic memory cell of the magnetic random access memory, the magnetic memory cell comprising a magnetic tunnel junction and an access transistor,
a read path loading tube for providing a reference current for a read operation to the magnetic memory cell to be tested;
the access transistor of the magnetic storage unit is connected with the read path load tube in series, the other end of the access transistor is electrically connected with one end of the magnetic tunnel junction, and under the bias of given word line voltage, the access transistor is arranged in a saturation area to form a common grid amplifier. The reading voltage of amplified output is formed by the connection node of the reading path load tube and the access transistor; the reading voltage and the reference voltage are used together as the input of a voltage sensitive amplifier at the next stage of the reading path.
2. The sensing circuit of claim 1, wherein the read path load transistor is a P-channel metal oxide semiconductor field effect transistor.
3. The sensing circuit of claim 1, wherein the access transistor is an N-channel metal oxide semiconductor field effect (MOS) transistor and a drain of the access transistor is coupled to a drain of a read path load tube, a source of the access transistor being coupled to one end of a magnetic tunnel junction.
4. The sensing circuit of claim 1, wherein the reference voltage is generated by connecting multiple magnetic tunnel junction reference memory cells pre-configured as a parallel state resistance and an anti-parallel state resistance in parallel to form a standard resistance at a given read current.
5. A sensing circuit of claim 1, wherein the reference voltage is generated by configuring a high precision thin film resistor at a given read current.
6. The sensing circuit of claim 1, wherein the voltage sensitive amplifier performs a magnitude comparison between the input read voltage and a reference voltage, and a latch receives the comparison result and converts the comparison result into a digital signal, thereby performing a read operation on the resistance state information of the selected magnetic memory cell.
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| WO2019112068A1 (en) * | 2017-12-08 | 2019-06-13 | 国立大学法人東北大学 | Storage circuit provided with variable resistance type element, and sense amplifier |
| US10545523B1 (en) * | 2018-10-25 | 2020-01-28 | Qualcomm Incorporated | Adaptive gate-biased field effect transistor for low-dropout regulator |
| CN110858496A (en) * | 2018-08-22 | 2020-03-03 | 中电海康集团有限公司 | Memory cell reading circuit |
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2020
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020172076A1 (en) * | 2001-01-03 | 2002-11-21 | Marotta Giulio G. | Sensing scheme for low-voltage flash memory |
| CN1851823A (en) * | 2005-04-22 | 2006-10-25 | 台湾积体电路制造股份有限公司 | Magnetic random access memory device |
| CN103811073A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | High-reliability read circuit of non-volatile memory |
| CN104766623A (en) * | 2015-04-20 | 2015-07-08 | 北京航空航天大学 | Circuit for enhancing STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory) reading reliability by using substrate bias voltage feedback |
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| WO2019112068A1 (en) * | 2017-12-08 | 2019-06-13 | 国立大学法人東北大学 | Storage circuit provided with variable resistance type element, and sense amplifier |
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