CN113495206A - Sequential circuit and sequential circuit control method - Google Patents
Sequential circuit and sequential circuit control method Download PDFInfo
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- CN113495206A CN113495206A CN202010260049.6A CN202010260049A CN113495206A CN 113495206 A CN113495206 A CN 113495206A CN 202010260049 A CN202010260049 A CN 202010260049A CN 113495206 A CN113495206 A CN 113495206A
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Abstract
The embodiment of the application provides a sequential circuit and a sequential circuit control method, wherein the sequential circuit comprises a sequential sub-circuit and a clock control module, and the sequential sub-circuit is provided with a functional signal input end and a test signal input end, so that the sequential circuit can receive a functional signal and a test signal, and the sequential circuit has testability. And the time sequence sub-circuit also comprises a functional clock signal input end and a test clock signal input end, so that the clock control module inputs the functional clock signal and the test clock signal through the clock signal input end and the test clock signal input end respectively. Therefore, the sequential circuit is controlled to work in a functional mode or a test mode through the functional clock signal and the test clock signal, so that the input of the functional signal and the test signal is selected, the propagation speed of the signal from the input end to the output end of the sequential circuit is improved, and the performance of the sequential circuit is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a sequential circuit and a sequential circuit control method.
Background
Integrated circuit testing is the process of testing an integrated circuit or module and determining or evaluating the function and performance of integrated circuit components by comparing the output response and expected output of the integrated circuit, and is an important means for verifying design, monitoring production, ensuring quality, analyzing failures and guiding applications. With the increase of the integration level of the integrated circuit, the circuit becomes more complex and the test difficulty increases. In order to improve the efficiency of the integrated circuit test, the testability design is adopted when the integrated circuit is designed, namely, the hardware logic for improving the testability of the integrated circuit is inserted into the design of the integrated circuit, so that the efficiency of the integrated circuit test is improved, and the test cost is saved.
Fig. 1 is a block diagram of a sequential circuit designed by a design for testability method. The sequential circuit shown in fig. 1 is designed by a scan test design method, so that the sequential circuit can be tested. The sequential circuit comprises an input module, an input signal logic selection module, a sequential storage module and an output module. The input module comprises a functional signal input end and a scanning signal input end, and the input signal logic selection module controls the functional signal to be input through the functional signal input end and controls the scanning signal to be input through the scanning signal input end, so that the time sequence circuit is tested.
However, since the input signal logic selection module is adopted in the sequential circuit, after the input signal is input through the input end, the input signal needs to pass through the input signal logic selection module and the sequential storage module and reach the output end module, so that the delay of signal propagation is increased, and the performance of the sequential circuit is affected.
Disclosure of Invention
The embodiment of the application provides a sequential circuit and a sequential circuit control method, which can reduce the propagation delay of an input signal and further improve the performance of the sequential circuit.
In a first aspect, an embodiment of the present application provides a sequential circuit, where the sequential circuit includes a sequential sub-circuit and a clock control module, and the sequential sub-circuit is connected to the clock control module;
the time sequence sub-circuit is provided with a functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and an output end; wherein;
the functional signal input end is used for inputting functional signals to the time sequence sub-circuit;
the test signal input end is used for inputting a test signal to the sequential sub-circuit;
the clock control module is used for inputting a functional clock signal to the functional clock signal input end and inputting a test clock signal to the test clock signal input end;
when the sequential circuit works in a functional mode, if the functional clock signal input end receives an effective functional clock signal and the test clock signal input end receives an ineffective test clock signal, the sequential sub-circuit controls the output end to output a functional signal;
when the sequential circuit works in a test mode, if the input end of the test clock signal receives an effective test clock signal and the input end of the functional clock signal receives an ineffective functional clock signal, the sequential sub-circuit controls the output end to output the test signal.
Optionally, the timing sub-circuit includes: the device comprises a storage module and a time sequence control module;
the time sequence control module is provided with the functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and a signal output end;
the storage module is provided with the output end, and the signal output end of the time sequence control module is connected with the storage module;
the time sequence control module is used for storing the functional signal input by the functional signal input end to the storage module through the signal output end and outputting the functional signal through the output end of the storage module when the time sequence circuit works in a functional mode; and when the sequential circuit works in a test mode, storing the test signal input through the test signal input end into the storage module through the signal output end, and outputting the test signal through the output end of the storage module.
Optionally, the timing control module includes a first timing control unit and a second timing control unit; the signal output end comprises a functional signal output end and a test signal output end;
the first time sequence control unit is provided with the functional signal input end, the functional clock signal input end and a functional signal output end, and the functional signal output end is connected with the storage module;
the second time sequence control unit is provided with the test signal input end, the test clock signal input end and a test signal output end, and the test signal output end is connected with the storage module;
the first timing control unit is configured to receive a function signal input through the function signal input terminal when the timing circuit operates in a function mode, store the function signal in the storage module through the function signal output terminal, and output the function signal through the output terminal of the storage module;
the second sequential control unit is used for receiving the test signal input by the test signal input end when the sequential circuit works in a test mode, storing the test signal to the storage module through the test signal output end, and outputting the test signal through the output end of the storage module.
Optionally, when the sequential circuit operates in the functional mode, a functional clock signal input through the functional clock signal input terminal and a test clock signal input through the test clock signal input terminal have different phases;
and when the sequential circuit works in a test mode, the phase of the functional clock signal input through the functional clock signal input end is different from that of the test clock signal input through the test clock signal input end.
Optionally, the functional clock signal and the test clock signal are the same clock signal; wherein the content of the first and second substances,
when the sequential circuit works in a functional mode, the functional clock signal input end inputs a functional clock signal to the sequential sub-circuit, and the test clock signal input end has no signal input;
when the sequential circuit works in a test mode, the test clock signal input end inputs a test clock signal to the sequential sub-circuit, and the functional clock signal input end has no signal input.
Optionally, the functional clock signal and the test clock signal are different clock signals; wherein the content of the first and second substances,
when the sequential circuit works in a functional mode, the functional clock signal input end inputs a functional clock signal to the sequential sub-circuit, and the test clock signal input through the test clock signal input end is an invalid signal;
when the sequential circuit works in a test mode, the test clock signal input end inputs a test signal to the sequential sub-circuit, and the functional clock signal input through the functional clock signal input end is an invalid signal.
Optionally, the sequential circuit further includes: the test signal generating circuit is connected with the test signal input end;
the test signal generating circuit is configured to provide the test signal to the test signal input terminal.
Optionally, the timing sub-circuit is a latch or a flip-flop.
In a second aspect, an embodiment of the present application provides a sequential circuit control method, where the sequential circuit includes a sequential sub-circuit and a clock control module, and the sequential sub-circuit is connected to the clock control module; the time sequence sub-circuit is provided with a functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and an output end; the method comprises the following steps:
when the functional clock signal input end receives an effective functional clock signal provided by the clock control module to the sequential sub-circuit and the test signal input end receives an ineffective test clock signal provided by the clock control module to the sequential sub-circuit, the sequential circuit works in a functional mode, and the sequential sub-circuit controls the output end to output a functional signal; the functional signal is input through a functional signal input end of the sequential sub-circuit;
when the test clock signal input end receives an effective test clock signal provided by the clock control module to the sequential sub-circuit and the functional signal input end receives an invalid functional clock signal provided by the clock control module to the sequential sub-circuit, the sequential circuit works in a test mode, and the sequential sub-circuit controls the output end to output a test signal; the test signal is input through a test signal input end of the sequential sub-circuit.
Optionally, the functional clock signal and the test clock signal have different phases.
Optionally, the method includes:
the functional clock signal and the test clock signal are the same clock signal;
inputting the functional clock signal to the sequential sub-circuit through the functional clock signal input end, and if no signal is input at the test clock signal input end, the sequential circuit works in a functional mode, and the sequential sub-circuit obtains the functional signal;
and inputting the test clock signal to the sequential sub-circuit through the test clock signal input end, wherein if no signal is input from the functional clock signal input end, the sequential circuit works in a test mode, and the sequential sub-circuit obtains the test signal.
Optionally, the method includes:
the functional clock signal and the test clock signal are different clock signals;
inputting the functional clock signal to the sequential sub-circuit through the functional clock signal input end, and if the test clock signal input through the test clock signal input end is an invalid signal, the sequential circuit works in a functional mode, and the sequential sub-circuit obtains the functional signal;
and inputting the test clock signal to the sequential sub-circuit through the test clock signal input end, wherein if the functional clock signal input through the functional clock signal input end is an invalid signal, the sequential circuit works in a test mode, and the sequential sub-circuit obtains the test signal.
Optionally, the integrated circuit further includes: the test signal generating circuit is connected with the test signal input end; the method further comprises the following steps:
the test signal input end obtains the test signal through a test signal generating circuit.
The embodiment of the application provides a sequential circuit and a sequential circuit control method, wherein the sequential circuit comprises a sequential sub-circuit and a clock control module, the sequential sub-circuit is provided with a functional signal input end and a test signal input end, so that the sequential circuit can receive a functional signal and a test signal, and the sequential circuit can have testability when the input end inputs the test signal. In addition, the timing sub-circuit further includes a functional clock signal input terminal and a test clock signal input terminal, so that the clock control module inputs the functional clock signal and the test clock signal through the clock signal input terminal and the test clock signal input terminal, respectively. Therefore, when the functional clock signal is an effective signal and the test signal is an ineffective signal, the time sequence circuit works in a functional mode, so that the functional signal is output through the output end of the time sequence sub-circuit; when the test clock signal is an effective signal and the functional signal is an ineffective signal, the time sequence circuit works in a test mode, so that the test signal is output through the output end of the time sequence sub-circuit; different clock signals are matched with different working modes of the sequential circuit for input, so that the input of functional signals and test signals is selected, the addition of an input signal logic selection module is avoided, the propagation delay of the input signals can be reduced, the propagation speed of the signals from the input end to the output end of the sequential circuit is improved, and the performance of the sequential circuit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a block diagram of a sequential circuit designed using a design for testability approach;
FIG. 2 is a waveform diagram corresponding to the blocks of the sequential circuit shown in FIG. 1;
FIG. 3 is a waveform diagram of a timing circuit according to an embodiment of the present application;
FIG. 4 is a block diagram of a sequential circuit according to an embodiment of the present disclosure;
FIG. 5 is a block diagram of a sequential circuit according to another embodiment of the present application;
FIG. 6 is a block diagram of a sequential circuit according to another embodiment of the present application;
FIG. 7 is a block diagram of a sequential circuit according to another embodiment of the present application;
fig. 8 is a flowchart of a sequential circuit control method according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For the sequential circuit shown in fig. 1, it has the functions of a functional signal input (Func-in) and a test signal input (Scan-in). Therefore, in order to select the input signal, the input signal logic selection module is enabled by the enable signal TE to control whether the input signal is the functional signal or the scan signal, and the input signal is output under the control of the clock signal. As shown in fig. 2, a test signal or a functional signal is output when the clock signal CLK rises, where in the first stage shown in fig. 2, TE is 1, the sequential circuit operates in the test mode, and the test signal is input; in the second stage, when TE is 0, the sequential circuit works in the functional mode, and the functional signal is input. Because the input signal logic selection module in the sequential circuit shown in fig. 1 has a certain signal propagation delay, the input signal logic selection module increases the delay of input signal propagation while controlling the type of the input signal, thereby affecting the performance of the sequential circuit.
The embodiment of the application provides a sequential circuit, which selects whether to input a test signal or a functional signal through different clock signals, that is, as shown in fig. 3, a clock signal includes a functional clock signal (Func-CLK) and a test clock signal (Scan-CLK), when the functional clock signal is an effective signal and the test clock signal is an ineffective signal, the sequential circuit works in a functional mode, so that the functional signal is output after being input to the sequential circuit under the control of the functional clock signal; when the test clock signal is an effective signal and the functional clock signal is an ineffective signal, the sequential circuit works in a test mode, so that the test signal is output after being input to the sequential circuit under the control of the test clock signal. By adopting the technical scheme, the type of the input signal of the sequential circuit is controlled by improving the clock signal, and the type of the input signal of the sequential circuit is controlled without additionally adding an input signal logic selection module, so that the propagation delay of the signal is reduced, and the performance of the sequential circuit is improved.
Fig. 4 is a structural diagram of a sequential circuit according to an embodiment of the present application. As shown in fig. 4, the timing circuit includes a timing sub-circuit 100 and a clock control module 200, wherein the timing sub-circuit 100 is connected to the clock control module 200; the timing sub-circuit 100 has a functional signal input (Func-CLK-in), a test signal input (Scan-CLK-in), a functional clock signal input (Func-in), a test clock signal input (Scan-in), and an output. The clock control module 200 is used for inputting a clock signal to the timing sub-circuit 100, wherein the clock signal comprises a functional clock signal and a test clock signal; the timing sub-circuit 100 is configured to control the output terminal to output a functional signal or a test signal according to the clock signal transmitted by the clock control module 200.
In the embodiment shown in fig. 4, the functional signal input of the sequential sub-circuit 100 is arranged to receive a functional signal and the test signal input of the sequential sub-circuit 100 is arranged to receive a test signal. Accordingly, the functional clock signal input of the timing sub-circuit 100 is configured to receive a functional clock signal, and the test clock signal input of the timing sub-circuit 100 is configured to receive a test clock signal. Optionally, the functional signal and the test signal may be in a normal input state, which ensures that the timing sub-circuit 100 can stably receive the functional signal and the test signal, and further ensures that the signal output from the output terminal is selected from the functional signal and the test signal in the following.
The clock control module 200 is connected to the functional signal input terminal and the test signal input terminal, and is configured to input the functional clock signal to the timing sub-circuit through the functional signal input terminal and input the test clock signal to the timing sub-circuit through the test signal input terminal. In the embodiment shown in fig. 4, when the timing circuit operates in the functional mode, the functional clock signal received by the functional clock signal input terminal is an active signal, and the test clock signal received by the test clock signal input terminal is an inactive signal; thus, the timing circuit allows the functional signal to be input to the timing sub-circuit and output through the output terminal under the control of the active functional clock signal. When the clock control module 200 inputs an effective test clock signal to the timing sub-circuit through the test signal input terminal and inputs an ineffective functional clock signal to the timing sub-circuit through the functional signal input terminal, the timing circuit operates in the test mode. Therefore, the sequential circuit allows the test signal to be input into the sequential sub-circuit and output through the output end under the control of the test clock signal, so that the sequential circuit has testability.
It should be noted that, in the embodiment of the present application, the clock control module 200 is not limited, and the clock control module 200 may be, for example, an oscillation circuit, a Central Processing Unit (CPU), or other electronic devices that can output a clock signal.
Further, since the timing sub-circuit shown in fig. 4 includes a functional clock signal input terminal and a test clock signal input terminal, the functional clock signal and the test clock signal are respectively input, that is, the functional clock signal and the test clock signal are input through different input terminals, so that the inputs of the two clock signals are not affected by each other, and further, the input and the output of the functional signal are not affected by the input and the output of the test signal.
The sequential circuit provided by the embodiment of the application comprises the sequential sub-circuit and the clock control module, wherein the sequential sub-circuit is provided with a functional signal input end and a test signal input end, so that the sequential circuit can receive a functional signal and a test signal, and the sequential circuit can have testability when the test signal is input at the input end. In addition, the timing sub-circuit further includes a functional clock signal input terminal and a test clock signal input terminal, so that the clock control module inputs the functional clock signal and the test clock signal through the clock signal input terminal and the test clock signal input terminal, respectively. Therefore, when the functional clock signal is an effective signal and the test signal is an ineffective signal, the time sequence circuit works in a functional mode, so that the functional signal is output through the output end of the time sequence sub-circuit; when the test clock signal is an effective signal and the functional signal is an ineffective signal, the time sequence circuit works in a test mode, so that the test signal is output through the output end of the time sequence sub-circuit; different clock signals are matched with different working modes of the sequential circuit for input, so that the input of functional signals and test signals is selected, the addition of an input signal logic selection module is avoided, the propagation delay of the input signals can be reduced, the propagation speed of the signals from the input end to the output end of the sequential circuit is improved, and the performance of the sequential circuit is improved. In addition, because an input signal logic selection module is not required to be added, the whole power consumption and the occupied logic area of the sequential circuit are reduced.
On the basis of the embodiment shown in fig. 4, as shown in fig. 5, the timing sub-circuit 100 includes: a memory module 110 and a timing control module 120. The timing control module 120 has a functional signal input terminal, a test signal input terminal, a functional clock signal input terminal, a test clock signal input terminal, and a signal output terminal; the signal output terminal of the timing control module 120 is connected to the memory module 110 to provide a signal input for the memory module 110, and the memory module 110 has an output terminal which can be used as an output terminal of the timing circuit.
Optionally, in the embodiment shown in fig. 5, when the timing circuit operates in the functional mode, the timing control module 120 stores the functional signal input through the functional signal input terminal into the storage module 110 through the signal output terminal, and outputs the functional signal through the output terminal of the storage module 110; and, when the timing circuit operates in the test mode, the timing control module 120 stores the test signal input through the test signal input terminal to the memory module 110 through the signal output terminal, and outputs the test signal through the output terminal of the memory module 110.
On the basis of fig. 5, as shown in fig. 6, the timing control module 120 includes: a first timing control unit 121 and a second timing control unit 122. The first timing control unit 121 has a functional signal input end, a functional clock signal input end, and a functional signal output end, and the functional signal output end is connected to the memory module 110; the second timing control unit 122 has a functional test input terminal, a test clock signal input terminal, and a test signal output terminal, and the test signal output terminal is connected to the memory module 110.
In the embodiment shown in fig. 6, the first timing control unit 121 corresponds to a functional mode of the timing circuit, and the second timing control unit 122 corresponds to a test mode of the timing circuit. When the timing circuit operates in the functional mode, the functional clock signal received by the functional clock signal receiving terminal is an effective signal, so that the functional signal is input to the first timing control unit 121 through the functional signal input terminal, and is output after being stored in the memory module 110 through the functional signal output terminal. When the timing circuit operates in the test mode, the test clock signal received by the test clock signal receiving terminal is an effective signal, so that the test signal is input to the second timing control unit 122 through the test signal input terminal, and is output after being stored in the memory module 110 through the test signal output terminal.
Alternatively, the timing sub-circuit may be a flip-flop or a latch, for example.
On the basis of any one of the embodiments shown in fig. 4 to 6, when the sequential circuit operates in the functional mode, the phase of the functional clock signal input through the functional clock signal input terminal is different from the phase of the test clock signal input through the test clock signal input terminal; when the sequential circuit operates in the test mode, the functional clock signal input through the functional clock signal input terminal and the test clock signal input through the test clock signal input terminal have different phases.
Optionally, the functional clock signal and the test clock signal are, for example, the same clock signal, that is, the same clock signal is input to the functional clock signal input terminal or the test clock signal input terminal at different times. The clock control module 200 outputs a clock signal, and if the clock signal is inputted as a functional clock signal through the functional clock signal input terminal, the test clock signal input terminal does not have a clock signal input, which is equivalent to the functional clock signal input terminal receiving an effective functional clock signal, and the test clock signal input terminal receiving an ineffective test clock signal, so that the sequential circuit operates in a functional mode, and when the rising edge of the clock signal arrives, the functional signal is inputted through the functional signal input terminal and then outputted through the output terminal.
Similarly, if the clock signal is input as a test clock signal through the test clock signal input terminal, and the functional clock signal input terminal does not input the clock signal, the functional clock signal input terminal receives an invalid functional clock signal, and the test clock signal input terminal receives an valid test clock signal, so that the sequential circuit works in the test mode.
Optionally, the functional clock signal and the test clock signal are different clock signals, that is, the control module 200 inputs the first clock signal (i.e., the functional clock signal) to the functional clock signal input terminal and inputs the second clock signal (i.e., the test clock signal) to the test clock signal input terminal, and at the same time, waveforms of the functional clock signal and the test clock signal are different. When the functional clock signal is an active signal and the test clock signal is an inactive signal, the timing circuit operates in a functional mode, such as the first stage of FIG. 3. In the first stage, the functional clock signal is a valid clock signal, and the test clock signal is set to 0; when the rising edge of the functional clock signal arrives, the timing sub-circuit 100 receives the functional signal through the functional signal input terminal and outputs the functional signal through the output terminal. If the functional signal changes, the output terminal of the timing sub-circuit 100 outputs the changed functional signal when the rising edge of the first functional clock signal after the change of the functional signal arrives. Therefore, the waveform of the signal output from the output terminal of the timing sub-circuit 100 corresponds to the waveform of the functional signal.
When the test clock signal is an active signal and the functional clock signal is an inactive signal, the timing circuit operates in a test mode, such as the second stage of FIG. 3. In the second phase, the test clock signal is a valid clock signal, and the functional clock signal is set to 0, thereby inputting the test signal. When the rising edge of the test clock signal arrives, the timing sub-circuit 100 receives the test signal through the test signal input terminal and outputs it through the output terminal. If the test signal changes, the output end of the timing sub-circuit 100 outputs the changed test signal when the rising edge of the first test clock signal after the change of the test signal arrives. Therefore, the waveform of the signal output from the output terminal of the timing sub-circuit 100 corresponds to the waveform of the test signal.
Therefore, the functional signal and the test signal are separately sampled by the phase difference between the functional clock signal and the test clock signal, that is, the test signal cannot be sampled when the functional signal is sampled; while the test signal is being sampled, the functional signal cannot be sampled. Therefore, an input signal logic selection module does not need to be added in the sequential circuit, so that the propagation delay of the input signal is reduced, the propagation speed of the signal from input to output is improved, and the performance of the sequential circuit is improved.
On the basis of any of the above-mentioned embodiments, the test signal is used to test the sequential circuit, wherein the sequential circuit can be tested when the production is completed, and the test is not performed after the test is passed, in which case, the test signal can be provided by an external signal generator. Optionally, the sequential circuit needs to be tested as required in the using process of the sequential circuit due to different functions and designs, in this case, because the sequential circuit is integrated in the integrated circuit, the test signal cannot be provided by the external signal generator, and therefore, as shown in fig. 7, the sequential circuit may further include: the test signal generating circuit 300, the test signal generating circuit 300 is connected with the test signal input terminal.
In the embodiment shown in fig. 7, when the sequential circuit operates in the test mode and a test signal is required, the test signal generating circuit generates a required test timing signal to supply the test signal to the test signal input terminal, so that the test signal can be supplied when the sequential circuit requires the test signal.
For the timing circuit provided in any of the above embodiments, a timing circuit control method is shown in fig. 8, and the method includes:
s101, when the functional clock signal input end receives an effective functional clock signal provided by the clock control module to the sequential sub-circuit, and the test signal input end receives an ineffective test clock signal provided by the clock control module to the sequential sub-circuit, the sequential circuit works in a functional mode.
Specifically, the operation mode of the sequential circuit may be preset, for example, after the functional mode is executed, the test mode is executed, and then the functional mode is executed, or the operation mode of the sequential circuit may be obtained by the functional clock signal and the test clock signal.
S102, when the test clock signal input end receives an effective test clock signal provided by the clock control module to the sequential sub-circuit and the functional signal input end receives an ineffective functional clock signal provided by the clock control module to the sequential sub-circuit, the sequential circuit works in a test mode.
Specifically, in combination with the sequential circuit shown in any of the above embodiments, the clock control module 200 inputs an effective functional clock signal through the functional clock signal input terminal, and when an ineffective test clock signal is input through the test clock signal input terminal, the sequential circuit is in the functional mode. At this time, the sequential sub-circuit 100 causes the functional signal to be input to the sequential sub-circuit 100 through the functional signal input terminal and output from the output terminal.
The clock control module 200 inputs an effective test clock signal through the test clock signal input terminal, and when an ineffective functional clock signal is input through the functional clock signal input terminal, the sequential circuit is in the test mode. At this time, the sequential sub-circuit 100 causes the test signal to be input to the sequential sub-circuit 100 through the test signal input terminal and output from the output terminal.
It should be noted that, the embodiment of the present application does not limit the execution sequence of S101 and S102, and determines to execute S101 or S102 according to the validity or invalidity of the functional clock signal and the test clock signal input by the clock control module 200. When S101 is executed, S102 is not executed; when S102 is executed, S101 is not executed.
In this embodiment, the sequential circuit selects the input of the functional signal and the test signal through the functional clock signal and the test clock signal input by the clock control module, so that the sequential circuit can work in the functional mode and the test mode without adding a signal logic selection module for selecting the functional signal and the test signal, thereby reducing the propagation delay of the input signal, improving the propagation speed of the signal from input to output, and further improving the performance of the sequential circuit. In addition, because the input signal logic selection module is not required to be added, the power consumption and the logic area of the input signal logic selection module are reduced, and the overall power consumption and the occupied logic area of the sequential circuit are reduced.
In the embodiment shown in fig. 8, the selection of the functional signal and the test signal is achieved by making the functional clock signal and the test clock signal clock signals different in phase.
Optionally, the functional clock signal and the test clock signal are, for example, the same clock signal, and if the clock signal output by the clock control module 200 is input as the functional clock signal through the functional clock signal input terminal and the test clock signal input terminal does not have the clock signal input, the timing circuit operates in the functional mode, and when the rising edge of the clock signal arrives, the functional signal is input through the functional signal input terminal and is then output through the output terminal.
Similarly, if the clock signal output by the clock control module 200 is input as a test clock signal through the test clock signal input terminal and no clock signal is input at the functional clock signal input terminal, the sequential circuit operates in the test mode, and when the rising edge of the clock signal arrives, the test signal is input through the test signal input terminal and is output through the output terminal.
Optionally, the functional clock signal and the test clock signal are different clock signals, and at the same time, waveforms of the functional clock signal and the test clock signal are different, as shown in fig. 3, when the functional clock signal is an effective signal and the test clock signal is an ineffective signal, the timing circuit operates in a functional mode, as shown in the first stage in fig. 3. In the first phase, the functional clock signal is a valid clock signal, and the test clock signal sets 0, thereby inputting the functional signal. When the rising edge of the functional clock signal arrives, the timing sub-circuit 100 receives the functional signal through the functional signal input terminal and outputs the functional signal through the output terminal. If the functional signal changes, the output terminal of the timing sub-circuit 100 outputs the changed functional signal when the rising edge of the first functional clock signal after the change of the functional signal arrives. Therefore, the waveform of the signal output from the output terminal of the timing sub-circuit 100 corresponds to the waveform of the functional signal.
When the test clock signal is an active signal and the functional clock signal is an inactive signal, the timing circuit operates in a test mode, such as the second stage of FIG. 3. In the second phase, the test clock signal is a valid clock signal, and the functional clock signal is set to 0, thereby inputting the test signal. When the rising edge of the test clock signal arrives, the timing sub-circuit 100 receives the functional signal through the test signal input terminal and outputs the functional signal through the output terminal. If the test signal changes, the output end of the timing sub-circuit 100 outputs the changed test signal when the rising edge of the first test clock signal after the change of the test signal arrives. Therefore, the waveform of the signal output from the output terminal of the timing sub-circuit 100 corresponds to the waveform of the test signal.
Therefore, the functional signal and the test signal are separately sampled by the phase difference between the functional clock signal and the test clock signal, that is, the test signal cannot be sampled when the functional signal is sampled; while the test signal is being sampled, the functional signal cannot be sampled. Therefore, an input signal logic selection module does not need to be added in the sequential circuit, so that the propagation delay of the input signal is reduced, the propagation speed of the signal from input to output is improved, and the performance of the sequential circuit is improved.
Optionally, for the sequential circuit shown in fig. 6, since the sequential circuit includes the test signal generating circuit 300, the sequential control method further includes: the test signal input end obtains a test signal through the test signal generating circuit.
Specifically, the test signal generation circuit may generate a test signal in real time and output the test signal to the test signal output terminal, or generate the test signal and output the test signal to the test signal output terminal when the sequential circuit operates in the test mode, for example.
Optionally, the test signal generating circuit generates the test signal when the sequential circuit operates in the test mode, where the test signal generating circuit may receive the test clock signal synchronously with the input end of the test clock signal, and when receiving an effective test clock signal, the test signal generating circuit generates the test signal, and when the received test clock signal is invalid or the test clock signal is not received, the test signal generating circuit does not generate the test signal, so that power consumption of the test signal generating circuit may be reduced, and power consumption of the sequential circuit is also reduced.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (11)
1. The sequential circuit is characterized by comprising a sequential sub-circuit and a clock control module, wherein the sequential sub-circuit is connected with the clock control module;
the time sequence sub-circuit is provided with a functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and an output end; wherein;
the functional signal input end is used for inputting functional signals to the time sequence sub-circuit;
the test signal input end is used for inputting a test signal to the sequential sub-circuit;
the clock control module is used for inputting a functional clock signal to the functional clock signal input end and inputting a test clock signal to the test clock signal input end;
when the sequential circuit works in a functional mode, if the functional clock signal input end receives an effective functional clock signal and the test clock signal input end receives an ineffective test clock signal, the sequential sub-circuit controls the output end to output a functional signal;
when the sequential circuit works in a test mode, if the test clock signal input end receives an effective test clock signal and the functional clock signal input end receives an ineffective functional clock signal, the sequential sub-circuit controls the output end to output the test signal.
2. The sequential circuit of claim 1, wherein the sequential sub-circuit comprises: the device comprises a storage module and a time sequence control module;
the time sequence control module is provided with the functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and a signal output end;
the storage module is provided with the output end, and the signal output end of the time sequence control module is connected with the storage module;
the time sequence control module is used for storing the functional signal input by the functional signal input end to the storage module through the signal output end and outputting the functional signal through the output end of the storage module when the time sequence circuit works in a functional mode; when the sequential circuit works in a test mode, the test signal input through the test signal input end is stored to the storage module through the signal output end; and output through the output end of the storage module.
3. The timing circuit of claim 2, wherein the timing control module comprises a first timing control unit and a second timing control unit; the signal output end comprises a functional signal output end and a test signal output end;
the first time sequence control unit is provided with the functional signal input end, the functional clock signal input end and a functional signal output end, and the functional signal output end is connected with the storage module;
the second time sequence control unit is provided with the test signal input end, the test clock signal input end and a test signal output end, and the test signal output end is connected with the storage module;
the first timing control unit is used for receiving a functional signal input by the functional signal input end when the timing circuit works in a functional mode, and storing the functional signal to the storage module through the functional signal output end; outputting the functional signal through an output end of the storage module;
the second sequential control unit is used for receiving a test signal input by the test signal input end when the sequential circuit works in a test mode, and storing the test signal to the storage module through the test signal output end; and outputting the test signal through an output terminal of the memory module.
4. The sequential circuit of any of claims 1-3, wherein a functional clock signal input through the functional clock signal input is out of phase with a test clock signal input through the test clock signal input when the sequential circuit is operating in a functional mode;
and when the sequential circuit works in a test mode, the phase of the functional clock signal input through the functional clock signal input end is different from that of the test clock signal input through the test clock signal input end.
5. The sequential circuit of claim 4, wherein the functional clock signal and the test clock signal are the same clock signal; wherein the content of the first and second substances,
when the sequential circuit works in a functional mode, the functional clock signal input end inputs a functional clock signal to the sequential sub-circuit, and the test clock signal input end has no signal input;
when the sequential circuit works in a test mode, the test clock signal input end inputs a test clock signal to the sequential sub-circuit, and the functional clock signal input end has no signal input.
6. The sequential circuit of claim 4, wherein the functional clock signal and the test clock signal are different clock signals; wherein the content of the first and second substances,
when the sequential circuit works in a functional mode, the functional clock signal input end inputs a functional clock signal to the sequential sub-circuit, and the test clock signal input through the test clock signal input end is an invalid signal;
when the sequential circuit works in a test mode, the test clock signal input end inputs a test signal to the sequential sub-circuit, and the functional clock signal input through the functional clock signal input end is an invalid signal.
7. The sequential circuit of claim 4, wherein the sequential circuit further comprises: the test signal generating circuit is connected with the test signal input end;
the test signal generating circuit is configured to provide the test signal to the test signal input terminal.
8. A sequential circuit control method is characterized in that a sequential circuit comprises a sequential sub-circuit and a clock control module, wherein the sequential sub-circuit is connected with the clock control module; the time sequence sub-circuit is provided with a functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and an output end; the method comprises the following steps:
when the functional clock signal input end receives an effective functional clock signal provided by the clock control module to the sequential sub-circuit and the test signal input end receives an ineffective test clock signal provided by the clock control module to the sequential sub-circuit, the sequential circuit works in a functional mode, and the sequential sub-circuit controls the output end to output a functional signal; the functional signal is input through a functional signal input end of the sequential sub-circuit;
when the test clock signal input end receives an effective test clock signal provided by the clock control module to the sequential sub-circuit and the functional signal input end receives an invalid functional clock signal provided by the clock control module to the sequential sub-circuit, the sequential circuit works in a test mode, and the sequential sub-circuit controls the output end to output a test signal; the test signal is input through a test signal input end of the sequential sub-circuit.
9. The method of claim 8, wherein the functional clock signal and the test clock signal are out of phase.
10. The method of claim 9, comprising:
the functional clock signal and the test clock signal are the same clock signal;
inputting the functional clock signal to the sequential sub-circuit through the functional clock signal input end, and if no signal is input at the test clock signal input end, the sequential circuit works in a functional mode, and the sequential sub-circuit obtains the functional signal;
and inputting the test clock signal to the sequential sub-circuit through the test clock signal input end, wherein if no signal is input from the functional clock signal input end, the sequential circuit works in a test mode, and the sequential sub-circuit obtains the test signal.
11. The method of claim 9, comprising:
the functional clock signal and the test clock signal are different clock signals;
inputting the functional clock signal to the sequential sub-circuit through the functional clock signal input end, and if the test clock signal input through the test clock signal input end is an invalid signal, the sequential circuit works in a functional mode, and the sequential sub-circuit obtains the functional signal;
and inputting the test clock signal to the sequential sub-circuit through the test clock signal input end, wherein if the functional clock signal input through the functional clock signal input end is an invalid signal, the sequential circuit works in a test mode, and the sequential sub-circuit obtains the test signal.
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