CN113488097B - Efficient reference current adjusting method, device and application for memory chip - Google Patents
Efficient reference current adjusting method, device and application for memory chip Download PDFInfo
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- 238000012360 testing method Methods 0.000 claims abstract description 110
- 230000015654 memory Effects 0.000 claims abstract description 48
- 238000012795 verification Methods 0.000 claims abstract description 40
- 230000000694 effects Effects 0.000 claims description 18
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3413—Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The invention relates to the technical field of memories and discloses a method, a device and an application for efficiently adjusting reference current of a memory chip, wherein the method comprises the steps of collecting related data in advance, configuring a plurality of erasing or programming operation parameters, presetting a target current value, a target current interval, an adjustable current range and calling triggering conditions, and alternately executing current verification operation and current adjustment operation on each reference unit until the memory chip or all the reference units exit the verification operation; the adjustment method of the invention realizes personalized adjustment of the reference current in the memory chip by dynamically adjusting the conditions of erasing and programming, can efficiently adjust the threshold voltage of the reference unit with the fastest speed and the lowest loss, has stable and reliable adjustment result, realizes complete parallelism of the multi-chip parallel test system designed on the basis, reduces waiting caused by over-erasing and over-programming, and has wide application value.
Description
Technical Field
The invention relates to the field of memory technology, in particular to a method, a device and application for efficiently adjusting reference current of a memory chip.
Background
In order to verify the correctness of the nonvolatile memory product, a series of test flows are performed before the product leaves the factory. The most typical Flash memory Flash, in practice, before performing logic function test, electrical erasure characteristic test and program code test, it is necessary to precisely adjust the reference current of the nonvolatile memory chip to be tested.
Taking SLC (Single Level Cell) Flash memory as an example, the readout principle is as follows: the same gate terminal and drain terminal voltages are applied to the memory cell and the reference cell, and the drain terminal currents are compared, and if the memory cell current is larger than the reference cell current (hereinafter referred to as reference current), it is defined as "1", otherwise, it is defined as "0". I.e., to define a memory cell storing a "1" and storing a "0", whether the memory cell current is greater or less than the reference current. Therefore, the reference current is a decision point of the stored data, which is the basis of the whole Flash memory read-out system, and needs to be adjusted relatively accurately before testing.
Reference current regulation refers to erasing (Erase) or programming (Program) a reference cell such that its reference current meets the requirements of a systematic evaluation test. If the range of the reference current is within the preset range, the threshold voltage setting of the reference current can be considered to be completed, if the range is not within the preset range, the reference current is required to be continuously adjusted, and if the range is smaller than the lowest value of the preset range, the reference unit is required to execute the erasing operation, the threshold voltage is reduced, and the reference current is improved; if the threshold voltage is greater than the maximum value of the preset range, the reference unit is required to execute the programming operation, the threshold voltage is increased, and the reference current is reduced.
In the current setting process of a certain reference unit of a memory chip, the erasing operation and the programming operation and the erasing and programming intensity which should be performed in the next step need to be repeatedly determined according to the test result. The threshold voltage setting of the reference cell is typically accomplished by first erasing below the threshold voltage and then programming weakly. For chips with large reference current difference, a long time is required to complete the threshold voltage setting, the limitation is high, and the adjustment time is wasted greatly.
In addition, when the parallel measurement number is large, the reference units of the chips are inconsistent due to inconsistent specific adjustment, and the adjustment of the reference units cannot be completed by adopting the same operation process for the chips which are simultaneously measured, so how to reduce the test time under the parallel measurement condition of a plurality of memory chips, and especially how to reduce the adjustment time of the threshold parameters of the reference units, become the problem to be solved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a high-efficiency reference current adjusting method, a device and application for a memory chip, which can adjust a reference unit to a preset threshold voltage at an optimal speed, and realize and measure the maximization of reference current adjusting efficiency.
The invention solves the technical problems by adopting the following technical scheme:
the invention provides a high-efficiency reference current adjusting method for a memory chip, which comprises the following steps:
acquiring related data of a memory chip to be detected in advance, and configuring a plurality of erasing or programming operation parameters according to the range of a reference current difference delta I before and after operation;
presetting a target current value, a target current interval and an adjustable current range, and sequentially matching and setting an erasing or programming operation parameter to call a triggering condition;
performing a current verification operation, comprising: executing power-on operation on each reference unit in the memory chip, reading test reference current of each reference unit, judging whether the test reference current is out of an adjustable current range, if yes, marking the chip as a defective state and exiting verification operation, otherwise, judging whether the reference current is in a target current interval, if yes, marking the reference unit as a finished attribute and exiting verification operation, otherwise, triggering execution of current adjustment operation, and comprising:
positioning the associated calling triggering condition according to the comparison result of the test reference current and the target current value, and calling the corresponding erasing or programming operation parameter to execute the erasing or programming operation on the memory cell;
the current verification operation and the current adjustment operation described above are alternately performed for each reference cell until the memory chip or all reference cells exit the verification operation.
Preferably, the pre-collecting the related data of the memory chip to be tested specifically includes:
memory chips of equivalent specifications are pre-calibrated, and erasing or programming effect data based on different voltages and pulse intensities are systematically collected, wherein the erasing or programming effect data comprises reference current change values:
the effect data and the corresponding voltage and pulse intensity are stored in a matching manner and form a reference database.
Preferably, the configuration of the plurality of erasing or programming operation parameters according to the range of the reference current difference Δi before and after the operation specifically includes:
configuring a first erase or program operation parameter corresponding to a ΔI of 5 μA.ltoreq.50μA;
configuring a second erase or program operation parameter corresponding to 1 μA < ΔI < 5 μA;
a third erase or program operation parameter is configured corresponding to 0.1 μA.ltoreq.ΔI < 1 μA.
Preferably, the target current interval is [ I ] Order of (A) -ΔI P ,I Order of (A) +ΔI P ]The adjustable current range is I Order of (A) ±ΔI a Wherein I Order of (A) For the target current value, ΔI P For reference current redundancy ΔI a Is the maximum adjustable current difference.
Preferably, the step of setting the trigger conditions for the matching of the erasing or programming operation parameters sequentially specifically includes:
configuring a first call trigger condition of 5 μA to +|ΔI corresponding to a first erase or program operation parameter Measuring |；
Configuring a second call trigger condition 1 μA to +|ΔI corresponding to a second erase or program operation parameter Measuring |＜5μA；
Configuring a third call trigger condition ΔI corresponding to a third erase or program operation parameter P ≤|ΔI Measuring |＜1μA；
Wherein DeltaI Measuring To test the difference between the reference current and the target current.
Preferably, the erase or program operation parameters include an erase or program operation start voltage, a start pulse intensity, a maximum number of operations, a preset boosting number, and an operation voltage increment Δv.
Preferably, the invoking the corresponding erase or program operation parameter to perform the erase or program operation on the memory cell specifically includes:
reading the number of times the erase or program operation parameter has been invoked:
if the maximum operation times are exceeded, the memory cell chip is marked as defective and the adjustment operation is exited,
otherwise, judging whether the called times reach the preset supercharging times or not:
if so, executing the current erasing or programming operation after the delta V is increased on the last erasing or programming operation voltage, otherwise, executing the current erasing or programming operation according to the last erasing or programming operation voltage;
updating the called secondary value of the erasing or programming operation parameter after the operation is finished;
wherein the value of DeltaV is dynamically adjusted according to the number of increments.
The invention also provides a high-efficiency reference current adjusting device for the memory chip, which comprises a control module, a memory module and a test adjusting module, wherein,
the control module is internally provided with a control unit matched with each reference unit in the memory chip, and the control unit is used for processing and configuring a plurality of erasing or programming operation parameters according to the pre-acquired data sent by the test adjustment module, and sequentially matching and setting triggering conditions for the erasing or programming operation parameters so as to control the test adjustment module to execute corresponding test adjustment actions on each reference unit;
the memory module is provided with a memory unit and a counting unit which are matched with each reference unit in the memory chip, the memory unit is used for storing erasing or programming operation parameters, a preset target current value, a target current interval and an adjustable current range, and the counting unit is used for recording the called times of the erasing or programming operation parameters in real time;
the test adjustment module is provided with a test adjustment unit matched with each reference unit in the memory chip, the test adjustment unit is configured to send the data related to the memory chip to be tested collected in advance into the control unit for processing, and the control unit, the storage unit and the counting unit are matched to alternately execute current verification operation and current adjustment operation on the reference units, and the test adjustment module specifically comprises the following steps:
performing a current verification operation, comprising: the test adjustment unit executes power-on operation on each reference unit in the memory chip, the control unit reads the test reference current of each reference unit and judges whether the test reference current is out of the adjustable current range, if yes, the chip is marked as a defective state and the verification operation is withdrawn, the connection between the chip and the test adjustment unit is disconnected, otherwise, whether the reference current is in a target current interval is judged, if yes, the reference unit is marked as a completion attribute and the verification operation is withdrawn, the connection between the reference unit and the test adjustment unit is disconnected, otherwise, the current adjustment operation is triggered and executed, and the method comprises the following steps:
the control unit locates the associated calling trigger condition according to the comparison result of the test reference current and the target current value, calls the corresponding erasing or programming operation parameter stored in the storage unit, and controls the test adjustment unit to execute erasing or programming operation on the storage unit;
the current verification operation and the current adjustment operation described above are alternately performed for each reference cell until the memory chip or all reference cells exit the verification operation.
Preferably, the pre-collecting the data related to the memory chip to be tested specifically includes:
the test adjustment module is used for systematically acquiring erasing or programming effect data based on different voltages and pulse intensities in batches of memory chips with equivalent specifications in advance, and comprises reference current change values:
matching and storing the effect data with the corresponding voltage and pulse intensity to form a reference database;
the erasing or programming operation parameters stored in the memory unit comprise an erasing or programming operation starting voltage, an initial pulse intensity, a maximum operation frequency, a preset boosting frequency and an operation voltage increment delta V;
the invoking the corresponding erase or program operation parameter to perform the erase or program operation on the memory cell specifically includes:
the control unit reads the called times of the erasing or programming operation parameters in the counting unit:
if the maximum operation times are exceeded, marking the memory cell chip as defective state, exiting the adjustment operation, disconnecting the connection with the test adjustment unit,
otherwise, judging whether the called times reach the preset supercharging times or not:
if so, controlling the test adjustment unit to execute the current erasing or programming operation after the delta V is increased on the last erasing or programming operation voltage, otherwise, executing the current erasing or programming operation according to the last erasing or programming operation voltage;
updating the called secondary value of the erasing or programming operation parameter in the counting unit after the operation is finished;
wherein the value of DeltaV is dynamically adjusted according to the number of increments.
The invention also provides a parallel test system of the multi-memory chip, which comprises:
the reference current high-efficiency adjusting devices are respectively matched with the memory chips;
the test adjustment module comprises a test machine table and a probe table, and each memory chip is connected with the test machine table through the probe table;
and the master control device is configured to control the control module in each reference current high-efficiency adjusting device so as to control the reference current high-efficiency adjusting device, the test machine and the probe station, and execute reference current adjusting actions on each memory chip in parallel according to the reference current high-efficiency adjusting method.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a high-efficiency reference current adjusting method, which realizes the dynamic adjustment of the erasing and programming intensity through the configuration of erasing or programming operation parameters and the setting of calling triggering conditions, and the current verification operation and the current adjusting operation which are alternately executed realize the personalized adjustment of the reference current in a memory chip, and the special dynamic supercharging operation further reduces the frequency of voltage threshold adjustment, so that the high-efficiency adjustment of the threshold voltage of a reference unit can be carried out at the fastest speed and the lowest loss, and the adjusting result is stable and reliable;
the parallel test system of the multi-memory chips designed based on the efficient reference current adjustment method realizes complete parallel of erasure and programming, and the values of erasure and programming intensity are adjusted in a targeted manner according to different reference units in each chip to realize intensity control, so that time increase caused by over erasure or over programming is avoided, too weak conditions are not selected for completely avoiding over erasure or over programming, chips with weak erasure or programming performance can be caused, and the threshold voltage setting requirement can be met only by a plurality of times of operations, thereby reaching preset threshold voltage at optimal speed, and maximizing the efficiency of parallel test.
Other prominent substantial features and significant advances of the invention relative to the prior art are described in further detail in the examples section.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a flow chart of a method for efficiently adjusting reference current in embodiment 1;
FIG. 2 is a flowchart of an erase or program operation in embodiment 1;
FIG. 3 is a schematic diagram of a high efficiency reference current regulator in accordance with embodiment 2;
fig. 4 is a schematic diagram of a parallel test system of multiple memory chips in embodiment 3.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that certain names are used throughout the specification and claims to refer to particular components. It should be appreciated that one of ordinary skill in the art may refer to the same component by different names. The description and claims do not identify differences in names as a way of distinguishing components, but rather are identified as a way of distinguishing components. As used in the specification and claims of this application, the terms "comprising" or "including" are to be construed as "including but not limited to" or "including but not limited to". The embodiments described in the detailed description are preferred embodiments of the invention and are not intended to limit the scope of the invention.
Example 1
Referring to fig. 1 and 2, the present embodiment provides a reference current efficient adjustment method for a memory chip, which includes:
the method for collecting the related data of the memory chip to be measured in advance specifically comprises the following steps: memory chips of equivalent specifications are pre-calibrated, and erasing or programming effect data based on different voltages and pulse intensities are systematically collected, wherein the erasing or programming effect data comprises reference current change values:
matching and storing the effect data with the corresponding voltage and pulse intensity to form a reference database; in this embodiment, the erasing and programming effects of the memory chip to be tested can be pre-collected on a large scale on the existing test system, and the erasing and programming intensities can be gradually increased according to a preset program, so that more background data can be acquired as much as possible; for example, the initial reference current of the whole wafer can be automatically collected, and the erasing and programming effects of different adjusting voltages and pulse widths on the threshold voltage of the chip can be collected and analyzed to obtain initial data;
configuring a plurality of erasing or programming operation parameters according to the range of the reference current difference delta I before and after operation; the method specifically comprises the following steps:
configuring a first erase or program operation parameter corresponding to a ΔI of 5 μA.ltoreq.50μA;
configuring a second erase or program operation parameter corresponding to 1 μA < ΔI < 5 μA;
configuring a third erase or program operation parameter corresponding to 0.1 μA < ΔI < 1 μA;
in this embodiment, the erasing or programming operation parameters include an erasing or programming operation start voltage, a start pulse intensity, a maximum operation frequency, a preset boosting frequency and an operation voltage increment Δv, which may be set separately according to erasing and programming, and will not be described in detail;
presetting a target current value, a target current interval and an adjustable currentThe range, and match and set up and call the triggering condition to the erasing or programming operation parameter sequentially; in the target current interval [ I ] Order of (A) -ΔI P ,I Order of (A) +ΔI P ]The adjustable current range is I Order of (A) ±ΔI a Wherein I Order of (A) For the target current value, ΔI P For reference current redundancy ΔI a For maximum adjustable current difference, it should be noted that the reference current is the current between the drain and the source, and we generally choose the target current value I Order of (A) 12 μA, reference current redundancy ΔI P 0.3 mu A, maximum adjustable current difference DeltaI a If the difference between the reference current value and the target current value is within 50 mu A, the reference current value is directly considered as a defective chip by exceeding 50 mu A, if the reference current value is within 12 mu A plus or minus 0.3 mu A, the threshold voltage setting of the reference current can be considered to be completed, if the reference current value is not within the range, if the reference current value is greater than 12.3 mu A or less than 11.7 mu A, the threshold voltage of the reference unit is required to be continuously adjusted to achieve the effect of adjusting the reference current, if the reference current value is less than 11.7 mu A, the reference unit is required to execute the erasing operation, the threshold voltage is reduced, and the reference current value is increased; if the voltage is larger than 12.3 mu A, the reference unit is required to execute programming operation, the threshold voltage is increased, and the reference current value is reduced;
the call triggering conditions in this embodiment specifically include:
configuring a first call trigger condition of 5 μA to +|ΔI corresponding to a first erase or program operation parameter Measuring |；
Configuring a second call trigger condition 1 μA to +|ΔI corresponding to a second erase or program operation parameter Measuring |＜5μA；
Configuring a third call trigger condition ΔI corresponding to a third erase or program operation parameter P ≤|ΔI Measuring |＜1μA；
Wherein DeltaI Measuring To test the difference between the reference current and the target current.
When the memory chip is actually tested and adjusted, the first erasing or programming operation parameter is triggered to be used for executing the erasing and over-programming operation under the condition that the difference value between the test reference current and the target current is overlarge, so that the reference current can be adjusted quickly, the second erasing or programming operation parameter or the third erasing or programming operation parameter is continuously triggered to be used for carrying out the fine adjustment of the threshold voltage after the difference value between the test reference current and the target current is smaller, and the fluctuation amplitude of the reference current is prevented from being overlarge due to the strong change of the threshold voltage caused by over-erasing or over-programming, so that the adjustment time is shortened, and the adjustment efficiency is improved;
performing a current verification operation, comprising: executing power-on operation on each reference unit in the memory chip, reading test reference current of each reference unit, judging whether the test reference current is out of an adjustable current range, if yes, marking the chip as a defective state and exiting verification operation, otherwise, judging whether the reference current is in a target current interval, if yes, marking the reference unit as a finished attribute and exiting verification operation, otherwise, triggering execution of current adjustment operation, and comprising:
positioning the associated calling triggering condition according to the comparison result of the test reference current and the target current value, and calling the corresponding erasing or programming operation parameters to execute the erasing or programming operation on the memory cell, wherein the method specifically comprises the following steps:
reading the number of times the erase or program operation parameter has been invoked:
if the maximum operation times are exceeded, the memory cell chip is marked as defective and the adjustment operation is exited,
otherwise, judging whether the called times reach the preset supercharging times or not:
if so, executing the current erasing or programming operation after the delta V is increased on the last erasing or programming operation voltage, otherwise, executing the current erasing or programming operation according to the last erasing or programming operation voltage;
updating the called secondary value of the erasing or programming operation parameter after the operation is finished;
for example, if the maximum number of operations in the first erase or program operation parameter is set to 3, the preset boosting number is 0, the maximum number of operations in the second erase or program operation parameter is set to 10, the preset boosting number is 5, the maximum number of operations in the second erase or program operation parameter is set to 30, the preset boosting number is 3, if the test reference isThe difference between the current and the target current satisfies 5 mu A to delta I Measuring And I, calling a first erasing or programming operation parameter to execute erasing or programming operation on the reference unit according to the initial voltage and the initial pulse intensity, and executing verification operation after the operation is finished, wherein if the difference value between the verified test reference current and the target current meets 5 mu A-delta I Measuring I, calling a first erasing or programming operation parameter to execute erasing or programming operation on the reference unit according to the initial voltage and the initial pulse intensity, if the difference between the verified test reference current and the target current meets 1 mu A to be less than or equal to I delta I Measuring Calling a second erasing or programming operation parameter to execute erasing or programming operation on the reference unit according to the initial voltage and the initial pulse intensity, executing verification operation after the operation is finished, and if the difference between the verified test reference current and the target current meets delta I P ≤|ΔI Measuring Calling a third erasing or programming operation parameter to execute erasing or programming operation on the reference unit according to the initial voltage and the initial pulse intensity, and executing verification operation after the operation is finished, wherein if the difference between the verified test reference current and the target current still meets delta I P ≤|ΔI Measuring If the initial pulse intensity is smaller than 1 mu A, the erasing or programming operation is repeatedly executed, if the initial pulse intensity is smaller than 1 mu A, the erasing or programming operation is continuously executed on the reference unit after the initial pulse intensity is increased by delta V for the third time, the initial pulse intensity can be increased proportionally, and if the initial pulse intensity is executed for the 30 th time, the difference between the verified test reference current and the target current still meets delta I P ≤|ΔI Measuring Marking the memory chip as defective and exiting the adjustment operation if the difference between the test reference current and the target current after the 5 th verification is performed satisfies |ΔI Measuring |≤ΔI P Marking the storage unit as a finished state and exiting the adjustment operation;
the value of Δv is dynamically adjusted according to the increment times, for example, Δv can be set to linearly increase according to the increment times, and the change value of Δv can be gradually reduced according to the increment times, which are not described in detail;
the voltage is generally adjusted first, and only the voltage reaches a predetermined range to adjust the pulse intensity, wherein the adjustment of the pulse intensity can be set by referring to the voltage adjustment, and the description is omitted here;
in the embodiment, the trigger condition is set in multiple steps, and the current adjustment action is performed for the differential matching of the reference units among the memory chips by adjusting the operation parameters of erasing programming so as to reduce the test adjustment time;
meanwhile, aiming at the possible defects of the memory chip, setting defect identification conditions, judging that the chip has defects when the continuous maximum operation times of the erasing or programming operation are not effective, further under the same adjustment triggering conditions, increasing the voltage delta V of the erasing or programming operation to execute the erasing or programming operation according to each increase of the preset boosting times of the operation under the same calling triggering conditions, on one hand, increasing the success rate of adjustment, saving the adjustment time, on the other hand, realizing the dynamic variability of the adjustment operation under the same calling triggering conditions, and on the other hand, realizing the accurate and rapid adjustment of the reference current when the reference current is closer to the target current interval;
the current verification operation and the current adjustment operation described above are alternately performed for each reference cell until the memory chip or all reference cells exit the verification operation.
Example 2
Referring to fig. 3, the present embodiment provides a reference current efficient adjustment device for a memory chip, including a control module, a memory module, and a test adjustment module, wherein
The control module is internally provided with a control unit matched with each reference unit in the memory chip, and the control unit is used for processing and configuring a plurality of erasing or programming operation parameters according to the pre-acquired data sent by the test adjustment module, and sequentially matching and setting triggering conditions for the erasing or programming operation parameters so as to control the test adjustment module to execute corresponding test adjustment actions on each reference unit;
the pre-collecting the related data of the memory chip to be tested in this embodiment specifically includes:
the test adjustment module is used for systematically acquiring erasing or programming effect data based on different voltages and pulse intensities in batches of memory chips with equivalent specifications in advance, and comprises reference current change values:
matching and storing the effect data with the corresponding voltage and pulse intensity to form a reference database;
in this embodiment, the several erase or program operation parameters specifically include:
configuring a first erase or program operation parameter corresponding to a ΔI of 5 μA.ltoreq.50μA;
configuring a second erase or program operation parameter corresponding to 1 μA < ΔI < 5 μA;
configuring a third erase or program operation parameter corresponding to 0.1 μA < ΔI < 1 μA;
the call triggering conditions configured in the embodiment specifically include:
configuring a first call trigger condition of 5 μA to +|ΔI corresponding to a first erase or program operation parameter Measuring |；
Configuring a second call trigger condition 1 μA to +|ΔI corresponding to a second erase or program operation parameter Measuring |＜5μA；
Configuring a third call trigger condition ΔI corresponding to a third erase or program operation parameter P ≤|ΔI Measuring |＜1μA；
Wherein DeltaI Measuring To test the difference between the reference current and the target current.
The memory module is provided with a memory unit and a counting unit which are matched with each reference unit in the memory chip, the memory unit is used for storing erasing or programming operation parameters, a preset target current value, a target current interval and an adjustable current range, and the counting unit is used for recording the called times of the erasing or programming operation parameters in real time;
in the present embodiment, the target current interval is [ I ] Order of (A) -ΔI P ,I Order of (A) +ΔI P ]The adjustable current range is I Order of (A) ±ΔI a Wherein I Order of (A) For the target current value, ΔI P For reference current redundancy ΔI a Is the maximum adjustable current difference;
the erasing or programming operation parameters stored in the memory cell in this embodiment include an erasing or programming operation start voltage, a start pulse intensity, a maximum operation number, a preset boosting number and an operation voltage increment Δv;
the test adjustment module is provided with a test adjustment unit matched with each reference unit in the memory chip, the test adjustment unit is configured to send the data related to the memory chip to be tested collected in advance into the control unit for processing, and the control unit, the storage unit and the counting unit are matched to alternately execute current verification operation and current adjustment operation on the reference units, and the test adjustment module specifically comprises the following steps:
performing a current verification operation, comprising: the test adjustment unit executes power-on operation on each reference unit in the memory chip, the control unit reads the test reference current of each reference unit and judges whether the test reference current is out of the adjustable current range, if yes, the chip is marked as a defective state and the verification operation is withdrawn, the connection between the chip and the test adjustment unit is disconnected, otherwise, whether the reference current is in a target current interval is judged, if yes, the reference unit is marked as a completion attribute and the verification operation is withdrawn, the connection between the reference unit and the test adjustment unit is disconnected, otherwise, the current adjustment operation is triggered and executed, and the method comprises the following steps:
the control unit locates the associated calling trigger condition according to the comparison result of the test reference current and the target current value, calls the corresponding erasing or programming operation parameter stored in the storage unit, and controls the test adjustment unit to execute erasing or programming operation on the storage unit;
the method for executing the erasing or programming operation on the memory cell by calling the corresponding erasing or programming operation parameters in the embodiment specifically comprises the following steps:
the control unit reads the called times of the erasing or programming operation parameters in the counting unit:
if the maximum operation times are exceeded, marking the memory cell chip as defective state, exiting the adjustment operation, disconnecting the connection with the test adjustment unit,
otherwise, judging whether the called times reach the preset supercharging times or not:
if so, controlling the test adjustment unit to execute the current erasing or programming operation after the delta V is increased on the last erasing or programming operation voltage, otherwise, executing the current erasing or programming operation according to the last erasing or programming operation voltage;
updating the called secondary value of the erasing or programming operation parameter in the counting unit after the operation is finished;
wherein the value of DeltaV is dynamically adjusted according to the number of increments.
The current verification operation and the current adjustment operation described above are alternately performed for each reference cell until the memory chip or all reference cells exit the verification operation.
Example 3
Referring to fig. 4, the present embodiment provides a parallel test system for multiple memory chips, including:
a plurality of reference current high-efficiency adjustment devices as described in embodiment 2, which are respectively provided in a matching manner with each memory chip;
the test adjustment module comprises a test machine table and a probe table, and each memory chip is connected with the test machine table through the probe table;
and the master control device is configured to control the control modules in the reference current high-efficiency adjusting devices, so as to control the reference current high-efficiency adjusting devices, the test machine and the probe station, and execute reference current adjusting actions on all memory chips in parallel according to the reference current high-efficiency adjusting method in the embodiment 1.
The system is used in the parallel test process of the whole wafer, a storage unit and a control unit are configured for each reference unit to be tested, the control unit is used for generating a specific operation instruction of the reference unit in the next step, the storage unit is used for storing various data required by operation and judgment, the complete parallel of the erasure and the programming is realized through the system, the control of the intensity can be realized by pertinently adjusting the value of the storage unit according to the difference of the required erasure and the programming intensity of the reference unit in each chip, the time increase caused by over erasure/over programming is avoided, the reference unit in the chip with weak self erasure/programming performance can not be met due to the fact that the over weak condition is selected for completely avoiding over erasure/over programming, and the threshold voltage setting requirement can be met through a plurality of operations, so that the threshold voltage can be reached at the optimal speed, and the efficiency of the test is maximized.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (8)
1. A method for efficient reference current regulation for a memory chip, the method comprising:
acquiring related data of a memory chip to be detected in advance, and configuring a plurality of erasing or programming operation parameters according to the range of a reference current difference delta I before and after operation;
presetting a target current value, a target current interval and an adjustable current range, and sequentially matching and setting an erasing or programming operation parameter to call a triggering condition;
performing a current verification operation, comprising: executing power-on operation on each reference unit in the memory chip, reading test reference current of each reference unit, judging whether the test reference current is out of an adjustable current range, marking the chip as a defective state and exiting verification operation if yes, otherwise judging whether the test reference current is in a target current interval, marking the reference unit as a finished attribute and exiting verification operation if yes, otherwise triggering execution of current adjustment operation, and comprising:
positioning the associated calling triggering condition according to the comparison result of the test reference current and the target current value, and calling the corresponding erasing or programming operation parameter to execute the erasing or programming operation on the reference unit;
alternately executing the current verification operation and the current adjustment operation on each reference unit until the memory chip or all the reference units exit the verification operation;
the configuration of a plurality of erasing or programming operation parameters according to the range of the reference current difference delta I before and after operation specifically comprises the following steps:
configuring a first erase or program operation parameter corresponding to a ΔI of 5 μA.ltoreq.50μA;
configuring a second erase or program operation parameter corresponding to 1 μA < ΔI < 5 μA;
configuring a third erase or program operation parameter corresponding to 0.1 μA < ΔI < 1 μA;
the method comprises the steps of sequentially matching and setting the erasing or programming operation parameters to call the triggering conditions, and specifically comprises the following steps:
configuring a first call trigger condition of 5 μA to +|ΔI corresponding to a first erase or program operation parameter Measuring |；
Configuring a second call trigger condition 1 μA to +|ΔI corresponding to a second erase or program operation parameter Measuring |＜5μA；
Configuring a third call trigger condition ΔI corresponding to a third erase or program operation parameter P ≤|ΔI Measuring |＜1μA；
Wherein DeltaI Measuring To test the difference between the reference current and the target current.
2. The method for efficiently adjusting reference current of a memory chip according to claim 1, wherein the pre-collecting data related to the memory chip to be measured specifically comprises:
memory chips of equal specifications are pre-acquired systematically, and erasing or programming effect data based on different voltages and pulse intensities are acquired systematically, wherein the erasing or programming effect data comprise reference current change values;
the effect data and the corresponding voltage and pulse intensity are stored in a matching manner and form a reference database.
3. The method of claim 1, wherein the target current interval is [ I ] Order of (A) -ΔI P ,I Order of (A) +ΔI P ]The adjustable current range is I Order of (A) ±ΔI a Wherein I Order of (A) For the target current value, ΔI P For reference current redundancy ΔI a Is the maximum adjustable current difference.
4. The method of claim 1, wherein the erase or program operation parameters include an erase or program operation start voltage, a start pulse intensity, a maximum number of operations, a preset boosting number, and an operation voltage increment Δv.
5. The method of claim 4, wherein said invoking the corresponding erase or program operation parameters to perform the erase or program operation on the reference cell comprises:
reading the number of times the erase or program operation parameter has been invoked:
if the maximum operation times are exceeded, the memory chip is marked as defective and the adjustment operation is exited,
otherwise, judging whether the called times reach the preset supercharging times or not:
if so, executing the current erasing or programming operation after the delta V is increased on the last erasing or programming operation voltage, otherwise, executing the current erasing or programming operation according to the last erasing or programming operation voltage;
updating the called secondary value of the erasing or programming operation parameter after the operation is finished;
wherein the value of DeltaV is dynamically adjusted according to the number of increments.
6. A high-efficiency reference current adjusting device for a memory chip is characterized by comprising a control module, a memory module and a test adjusting module, wherein
The control module is internally provided with a control unit matched with each reference unit in the memory chip, and the control unit is used for processing and configuring a plurality of erasing or programming operation parameters according to the pre-acquired data sent by the test adjustment module, and sequentially matching and setting triggering conditions for the erasing or programming operation parameters so as to control the test adjustment module to execute corresponding test adjustment actions on each reference unit;
wherein the configuration obtains a plurality of erasing or programming operation parameters, specifically including:
configuring a first erase or program operation parameter corresponding to a ΔI of 5 μA.ltoreq.50μA;
configuring a second erase or program operation parameter corresponding to 1 μA < ΔI < 5 μA;
configuring a third erase or program operation parameter corresponding to 0.1 μA < ΔI < 1 μA;
the method comprises the steps of sequentially matching and setting the erasing or programming operation parameters to call the triggering conditions, and specifically comprises the following steps:
configuring a first call trigger condition of 5 μA to +|ΔI corresponding to a first erase or program operation parameter Measuring |；
Configuring a second call trigger condition 1 μA to +|ΔI corresponding to a second erase or program operation parameter Measuring |＜5μA；
Configuring a third call trigger condition ΔI corresponding to a third erase or program operation parameter P ≤|ΔI Measuring |＜1μA；
Wherein DeltaI Measuring For testing the difference between the reference current and the target current;
the memory module is provided with a memory unit and a counting unit which are matched with each reference unit in the memory chip, the memory unit is used for storing erasing or programming operation parameters, a preset target current value, a target current interval and an adjustable current range, and the counting unit is used for recording the called times of the erasing or programming operation parameters in real time;
the test adjustment module is provided with a test adjustment unit matched with each reference unit in the memory chip, the test adjustment unit is configured to send the data related to the memory chip to be tested collected in advance into the control unit for processing, and the control unit, the storage unit and the counting unit are matched to alternately execute current verification operation and current adjustment operation on the reference units, and the test adjustment module specifically comprises the following steps:
performing a current verification operation, comprising: the test adjustment unit executes power-on operation on each reference unit in the memory chip, the control unit reads the test reference current of each reference unit and judges whether the test reference current is out of the adjustable current range, if yes, the chip is marked as a defective state and the verification operation is withdrawn, the connection between the chip and the test adjustment unit is disconnected, otherwise, whether the reference current is in a target current interval is judged, if yes, the reference unit is marked as a completion attribute and the verification operation is withdrawn, the connection between the reference unit and the test adjustment unit is disconnected, otherwise, the current adjustment operation is triggered and executed, and the method comprises the following steps:
the control unit locates the associated calling trigger condition according to the comparison result of the test reference current and the target current value, calls the corresponding erasing or programming operation parameter stored in the storage unit, and controls the test adjustment unit to execute erasing or programming operation on the reference unit;
the current verification operation and the current adjustment operation described above are alternately performed for each reference cell until the memory chip or all reference cells exit the verification operation.
7. The reference current efficient adjustment device for a memory chip according to claim 6, wherein the pre-collecting data related to the memory chip to be measured specifically comprises:
the test adjustment module is used for systematically acquiring erasing or programming effect data based on different voltages and pulse intensities in batches of memory chips with equivalent specifications in advance, and comprises reference current change values:
matching and storing the effect data with the corresponding voltage and pulse intensity to form a reference database;
the erasing or programming operation parameters stored in the memory unit comprise an erasing or programming operation starting voltage, an initial pulse intensity, a maximum operation frequency, a preset boosting frequency and an operation voltage increment delta V;
the step of calling the corresponding erasing or programming operation parameters stored in the storage unit and controlling the test adjustment unit to execute the erasing or programming operation on the reference unit specifically comprises the following steps:
the control unit reads the called times of the erasing or programming operation parameters in the counting unit:
if the maximum operation times are exceeded, marking the memory chip as defective state, exiting the adjustment operation, disconnecting the connection with the test adjustment unit,
otherwise, judging whether the called times reach the preset supercharging times or not:
if so, controlling the test adjustment unit to execute the current erasing or programming operation after the delta V is increased on the last erasing or programming operation voltage, otherwise, executing the current erasing or programming operation according to the last erasing or programming operation voltage;
updating the called secondary value of the erasing or programming operation parameter in the counting unit after the operation is finished;
wherein the value of DeltaV is dynamically adjusted according to the number of increments.
8. A parallel test system for multiple memory chips, comprising:
a plurality of reference current high-efficiency adjusting devices as defined in claim 6 or 7, which are respectively matched with the memory chips;
the test adjustment module comprises a test machine table and a probe table, and each memory chip is connected with the test machine table through the probe table;
and the master control device is configured to control the control module in each reference current high-efficiency adjusting device, so as to control the reference current high-efficiency adjusting device, the test machine and the probe station, and execute the reference current adjusting action on each memory chip in parallel according to the reference current high-efficiency adjusting method as set forth in claims 1-5.
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| CN116595933B (en) * | 2023-07-17 | 2024-07-05 | 芯天下技术股份有限公司 | Random verification method and device for voltage configuration, electronic equipment and storage medium |
| CN116959544B (en) * | 2023-09-20 | 2023-12-15 | 上海芯存天下电子科技有限公司 | Verification current setting method, operation verification method and related equipment |
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