CN113485948B

CN113485948B - NVM bad block management method and control part

Info

Publication number: CN113485948B
Application number: CN202110730397.XA
Authority: CN
Inventors: 盛亮; 代亮亮
Original assignee: Chengdu Starblaze Technology Co ltd
Current assignee: Chengdu Starblaze Technology Co ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2023-11-14
Anticipated expiration: 2041-06-29
Also published as: CN113485948A

Abstract

An NVM bad block management method and control unit are provided. The provided storage bad block management method comprises the following steps: scanning the physical blocks in each logic unit to generate a first information table; determining a first type of merging block and a second type of merging block according to a first information table, determining at least one first merging block from the first type of merging blocks and determining a second merging block corresponding to each first merging block from the second type of merging blocks, wherein the first merging blocks comprise bad physical blocks, the second merging blocks comprise good physical blocks, and the good physical blocks in the second merging blocks can replace the bad physical blocks in the first merging blocks for data storage; and determining a first physical address of a bad physical block in each first merging block and a second physical address of a good physical block in a corresponding second merging block, and recording the association relation between the first physical address and the second physical address.

Description

NVM bad block management method and control part

Technical Field

The present application relates to memory device technology, and more particularly, to a bad block management method for NVM (Non Volatile Memory ), a method for accessing NVM, and a control unit.

Background

Fig. 1 illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capability for the host. The host and the storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, high speed peripheral component interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.

NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), XPoint memory, etc. are common NVM.

The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM 110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.

The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.

An example of a media interface controller is provided in chinese patent application No. 201510253428.1, entitled "microinstruction sequence execution method and apparatus thereof," which applies storage media access commands to NVM chips by executing microinstructions. Examples of media interface controllers are provided in chinese patent application No. 2020106080147, chinese patent application No. 202010615178.2, chinese patent application No. "intelligent read-and-redo method and media interface controller thereof," chinese patent application No. 202010207004.2, chinese patent application No. 201810380329.3, chinese patent application No. "method and apparatus for out-of-order execution of NVM commands" and chinese patent application No. 201610836531.3, and chinese patent application No. "method and apparatus for generating NVM chip interface commands".

Fig. 2 shows a detailed block diagram of the control components of the memory device.

The host accesses the storage device in IO commands that follow the storage protocol. The control component generates one or more storage commands based on the IO commands from the host and provides the storage commands to the media interface controller. The media interface controller generates storage media access commands (e.g., program commands, read commands, erase commands) that follow the interface protocol of the NVM chip from the storage commands. The control unit also keeps track of all storage commands generated from one IO command being executed and indicates to the host the result of processing the IO command.

Referring to fig. 2, the control part includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface acquires an IO command provided by the host and generates a storage command to be provided to the storage command processing unit. The storage commands, for example, access the same size of storage space, e.g., 4KB. The data unit of the data accessed by the corresponding one of the storage commands recorded in the NVM chip is referred to as a data frame. The physical page records one or more frames of data. For example, a physical page is 17664 bytes in size and a data frame is 4KB in size, and one physical page can store 4 data frames.

The storage medium management unit maintains a logical address to physical address translation for each storage command. For example, the storage medium management unit includes FTL tables. For a read command, the storage medium management unit outputs a physical address corresponding to a logical address accessed by the storage command, for a write command, the storage medium management unit allocates an available physical address to the storage medium management unit, and records a mapping relationship between the logical address accessed by the storage medium management unit and the allocated physical address. The storage medium management unit also maintains functions required to manage the NVM chip, such as garbage collection, wear leveling, etc.

The storage command processing unit operates the medium interface controller to issue a storage medium access command to the NVM chip according to the physical address provided by the storage medium management unit. For the sake of clarity, the commands sent by the storage command processing unit to the media interface controller are referred to as media interface commands, while the commands sent by the media interface controller to the NVM chip are referred to as storage media access commands. The storage medium access command follows the interface protocol of the NVM chip.

The NVM chip includes one or more Logic Units (LUNs). One or more dies (Die) may be included within the NVM chip package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within an NVM chip may execute commands and report status independently of each other. In "Open NAND Flash Interface Specification (review 3.0)" available from http:// www.micron.com/-/media/Documents/Products/Other% 20Documents/ONFI3_0gold.as hx, the meaning of target, logical element, plane is provided as regards to the object, which is part of the prior art. In the present application, the use of a Target (Target) is interchangeable with the use of a Logical Unit (LUN), unless otherwise indicated.

NVM chips typically store and read data on a page basis. While data is erased in blocks. A block (also referred to as a physical block) contains a plurality of pages (also referred to as physical pages). The physical pages have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes. Each Plane (Plane) may include a plurality of physical blocks. Physical blocks from multiple logical units and having the same physical address in the NVM chip are then grouped into large blocks. The plurality of logical units that provide physical blocks for a chunk is referred to as a logical unit group, each logical unit in the logical unit group may provide a physical block for the chunk.

For example, FIG. 3A shows a block construction schematic, in FIG. 3A, a block is constructed on every 16 logical units, each block including physical blocks from 16 logical units, in FIG. 3A block 0 includes physical block 0 from each of the 16 logical units, and block 2 includes physical block 2 from each logical unit, and other ways of constructing a block are also possible, as exemplified in the China patent application No. 201710752321.0, which provides other ways of constructing a block. Also in fig. 3A, a physical block is indicated by a reference numeral shaped as Bb-a, where a indicates that the physical block is provided by a logical unit (LUNa), and b indicates that the block number of the physical block in the logical unit is b.

Fig. 3B shows a schematic diagram of a logic cell and plane (Plan). Each Logical Unit (LUN) includes a plurality of planes (Plan). Referring to FIG. 3B, a large block is constructed on the logical units of 16 logical units (LUN 0, LUN1, LUN2, …, LUN 15), physical block B0 of LUN0-LUN15 constitutes large block 0, and physical block B1 of LUN0-LUN15 constitutes large block 1. Taking LUN2 as an example, LUN2 includes 4 planes (plane 0, plane 1, plane 2, and plane 3, where plane 0 and plane 3 are shown in fig. 3B, and plane 1 and plane 2 are not shown), each plane in the LUN can perform read and write operations at the same time to improve the parallelism of NVM operations.

With the development of the age, in order to meet mass data storage, the storage capacity of NVM is also increasing. The large capacity NVM has more Logical Units (LUNs), each comprising more physical blocks. The NVM manufactured in the factory inevitably has bad blocks. The occurrence and distribution of bad blocks is typically random. The NVM has bad blocks at the factory and new bad blocks appear on the NVM over time and used. The storage medium management unit of the control unit manages the bad physical blocks and stores the bad physical block information (e.g., by FTL algorithm). To identify and manage bad blocks, the NVM is shipped with the bad block locations marked. During the manufacturing process of a memory device including an NVM, the NVM included therein is scanned to identify bad blocks therein, where the bad blocks include both existing bad blocks when the NVM is shipped and new bad blocks generated after shipment. The control section records the location of each bad block (e.g., physical address, block number, or bitmap indicating bad blocks) so that the storage medium management unit knows the existence of bad blocks and normal physical blocks replace bad blocks. In the prior art, the control unit records the bad physical block information by generating a bad physical block bit for each bad physical block and storing the bad physical block bit in a designated physical block of the NVM, and for a mass storage device, more storage resources are required to be consumed to store the bad block information.

Disclosure of Invention

NVM has a variety of specifications. For example, the same or different vendor's NVM, the number and size of its physical blocks, the number and size of its physical pages, etc. are different, which introduces an additional burden to the control unit to manage the NVM. To facilitate the use of diversified NVMs, the control unit or its storage medium management unit organizes the diversified NVMs into a standard or uniform morphology. For example, a unified morphology physical block includes 1000 physical pages, each physical page being 16KB in size. It is understood that 1000 physical pages, 16KB, are examples. Still by way of example, an NVM chip whose physical blocks actually include 512 physical pages, each physical page being 16KB in size. At this time, 2 physical blocks of the NVM chip are combined to obtain physical blocks of a unified form, each real physical block provides 500 physical pages for the physical blocks of the unified form, and the remaining physical pages are reserved or not used. It will be appreciated that physical blocks of uniform morphology are built with one or more real physical blocks, depending on the actual specifications of the NVM chip. For simplicity, the unified form of physical blocks will also be referred to hereinafter as "merge blocks". The use of a merge block also facilitates the use of less storage resources to store physical block (merge block) information.

Typically, adjacent physical blocks are combined to obtain a merged block, so that a block address (block number) of the merged block constitutes a direct mapping relationship of block addresses of physical blocks constituting the merged block. For example, 1 bit is added to the block address of the merged block to obtain the block address of each of the 2 physical blocks constituting the merged block. And removing the lowest bit of the block address or the block number according to the address or the physical block number of the physical block communicating the merging block to obtain the merging block address or the merging block number.

However, the presence of bad blocks of NVM adds complexity to building a consolidated block (unified form of physical block). On the one hand, since the probability of existence of bad blocks in two or more adjacent physical blocks is multiplied by a factor equal to the number of physical blocks constituting a merge block, once a physical block is a bad block, a merge block constructed of the same physical block as it cannot be used, which results in waste of memory resources (physical blocks) of the NVM; on the other hand, the replacement technique of the bad (physical) block of the related art cannot be applied to the merge blocks because bad physical blocks in each merge block are distributed differently, and another merge block cannot be directly replaced with the merge block. Some of the occasional bad blocks in the NVM are replaced with normal blocks having different addresses by a block replacement technique, and when the physical address of a bad block is accessed, the access is responded to by the normal block replacing the bad block. The block replacement technique thus builds a logical block space, where "logical block space" is different from the logical address space constituted by LBAs (logical block addresses), but is intended to express that the logical block space includes consecutive block numbers, each of which is normally accessible. When a merge block is used, the block number of the logical block space represents the merge block number, and when a physical block is a bad block, the merge block number in the logical block space corresponding to the bad block is served by other normal merge blocks, so that other parts of the upper system or the control unit can operate the logical block space completely composed of normal blocks without considering the influence of the bad block.

In this case, it is desirable to construct a logical block space that does not contain bad blocks for upper layer use.

According to the scheme provided by the embodiment of the application, the control part records the information of the merging blocks obtained by merging at least two physical blocks at one time in each entry of the first information table, namely the control part can record the information of a plurality of physical blocks through each entry of the first information table, so that the physical block information can be stored by using less storage resources as possible; the control part records the association relation between the first physical address of the bad physical block in the first merging block and the second physical address of the good physical block in the corresponding second merging block besides the information of the merging blocks which are merged once, merges the good physical block in the first merging block with the good physical block in the second merging block according to the association relation to obtain a good physical block which is merged twice, and constructs a logic block space which does not contain the bad physical block and has continuous addresses under the condition that the natural bad physical block exists in the NVM chip so as to be convenient for the upper layer to use and further improve the performance of the storage device.

According to a first aspect of the present application, there is provided a method for managing bad blocks of a first NVM according to the first aspect of the present application, comprising: scanning physical blocks in each Logical Unit (LUN) to generate a first information table, wherein the first information table comprises a plurality of entries, each entry comprises information of a merging block which is merged at one time, and each merging block comprises at least two physical blocks; determining a first type of merging block and a second type of merging block according to a first information table, determining at least one first merging block from the first type of merging blocks and determining a second merging block corresponding to each first merging block from the second type of merging blocks, wherein the first type of merging block and the second type of merging block are different merging blocks, the first merging block comprises a bad physical block, the second merging block comprises a good physical block, and the good physical block in the second merging block can replace the bad physical block in the first merging block for data storage; and determining a first physical address of a bad physical block in each first merging block and a second physical address of a good physical block in a corresponding second merging block, and recording the association relation between the first physical address and the second physical address.

According to a first NVM bad block management method of the first aspect of the present application, there is provided a second NVM bad block management method according to the first aspect of the present application, each consolidated block comprising: at least two physical blocks adjacent to each other in a same plane (plane); or physical blocks of the same Logical Unit (LUN) in which at least two physical addresses are the same within multiple planes.

According to a second NVM bad block management method of the first aspect of the present application, there is provided a third NVM bad block management method according to the first aspect of the present application, the information of the merging blocks once merged, comprising: the method comprises the steps of merging the types of the blocks and the information of each physical block in the merged blocks, wherein the types of the merged blocks comprise good merged blocks and bad merged blocks which are merged at one time, the bad merged blocks comprise bad merged blocks of a first type and bad merged blocks of a second type, the first type of the bad merged blocks are bad physical blocks of all physical blocks, the second type of the bad merged blocks comprise good physical blocks and bad physical blocks, and the good merged blocks which are merged at one time are good physical blocks of all physical blocks.

The method for managing the first, second or third NVM bad blocks according to the first aspect of the present application provides the method for managing the fourth NVM bad blocks according to the first aspect of the present application, further comprising: combining the good physical blocks in the first combined block and the second combined block corresponding to the first combined block to obtain a good combined block for secondary combination; the number of physical blocks of the good merging blocks of the secondary merging is the same as that of the physical blocks of the merging blocks, and all the physical blocks of the good merging blocks of the secondary merging are good physical blocks.

The method for managing the fourth NVM bad block according to the first aspect of the present application provides the method for managing the fifth NVM bad block according to the first aspect of the present application, and the second type bad merged block comprises: the high-order bits are good physical blocks and the high-order bits are bad physical blocks or the high-order bits are bad physical blocks and the high-order bits are good physical blocks, wherein the high-order bits and the high-order bits refer to the high-order bits and the high-order bits in two bits occupied by the information of each physical block in the storage block.

According to the fourth or fifth NVM bad block management method of the first aspect of the present application, a sixth NVM bad block management method according to the first aspect of the present application is provided, wherein the second type of merge block comprises at least one merged good merge block and/or a second type of bad merge block; the first type of merge blocks include at least a second type of bad merge blocks.

The method for managing the NVM bad blocks according to any one of the first to sixth aspects of the present application provides the method for managing the NVM bad blocks according to the first aspect of the present application, wherein the determining the first type of merging blocks and the second type of merging blocks according to the first information table includes: and determining the number of bad merging blocks in each big block of the storage device according to the first information table, and determining the first merging blocks and the second merging blocks according to the number.

According to a seventh NVM bad block management method of the first aspect of the present application, a method for managing an eighth NVM bad block according to the first aspect of the present application is provided, and the method for determining the first type of merging blocks and the second type of merging blocks according to the number includes: taking all the merging blocks in a specified number of first large blocks with the largest bad merging blocks or all the merging blocks comprising at least one good physical block as second-class merging blocks, and acquiring the first-class merging blocks from the merging blocks of other large blocks except the first large blocks in the storage device; or taking all the merging blocks in the second big blocks with the quantity larger than the preset threshold value or all the merging blocks comprising at least one good physical block as second-type merging blocks, and acquiring the first-type merging blocks from the merging blocks of other big blocks except the second big blocks in the storage device.

According to a method for managing an NVM bad block of any one of the first to eighth aspects of the present application, a method for managing a ninth NVM bad block of the first aspect of the present application is provided, wherein at least one first merge block is determined from the first type of merge blocks and a second merge block corresponding to each first merge block is determined from the second type of merge blocks, including: for the merging block A of the first merging block, if one or more merging blocks B of the second merging block which is not allocated and is in the same logic unit with the merging block A exist, allocating the merging block B closest to the physical address of the merging block A to the merging block A, and taking the merging block A and the allocated merging block B as corresponding first merging blocks and second merging blocks.

The method for managing the ninth NVM bad block according to the first aspect of the present application provides the method for managing the tenth NVM bad block according to the first aspect of the present application, further comprising: and for the merging block A of the first type of merging block, if no merging block B of the second type of merging block which is not allocated and is in the same logic unit as the merging block A exists, taking the merging block of the large block where the merging block A exists as the second type of merging block.

The ninth or tenth NVM bad block management method according to the first aspect of the present application proposes the eleventh NVM bad block management method according to the first aspect of the present application, further comprising: for a merging block A of a first type of merging block, if one or more merging blocks B of a second type of merging blocks which are not allocated and are in the same plane in the same logic unit as the merging block A exist, allocating the merging block B closest to the physical address of the merging block A to the merging block A, and taking the merging block A and the allocated merging block B as corresponding first merging blocks and second merging blocks.

The eleventh NVM bad block management method according to the first aspect of the present application proposes the twelfth NVM bad block management method according to the first aspect of the present application, further comprising: and for the merging block A of the first type of merging block, if no merging block B of the second type of merging block which is not allocated and is in the same plane with the merging block A in the same logic unit exists, taking the merging block of the large block where the merging block A exists as the second type of merging block.

According to a thirteenth NVM bad block management method of the first aspect of the present application, at least one first merge block is determined from the first type of merge blocks and a second merge block corresponding to each first merge block is determined from the second type of merge blocks, including: determining a plurality of third merging blocks and a first quantity thereof from first merging blocks in the same Logic Unit (LUN) and a plurality of fourth merging blocks and a second quantity thereof from second merging blocks according to a first information table respectively, wherein the third merging blocks comprise good physical blocks and bad physical blocks, and the fourth merging blocks comprise good physical blocks or good physical blocks and bad physical blocks; the first and second merge blocks are determined based on the first and second numbers.

According to a thirteenth NVM bad block management method of the first aspect of the present application, a fourteenth NVM bad block management method according to the first aspect of the present application is provided, the first merged block and the second merged block are determined according to the first number and the second number, including: if the first number is not greater than the second number, taking each third merging block as a first merging block, and taking a fourth merging block closest to each first merging block as a corresponding second merging block; or if the first number is larger than the second number, each fourth merging block is used as a second merging block, and the first merging block closest to each second merging block is used as the corresponding first merging block.

The fourteenth NVM bad block management method according to the first aspect of the present application provides the fifteenth NVM bad block management method according to the first aspect of the present application, further comprising: if the first number is larger than the second number, determining that a fifth merging block of the second merging blocks corresponding to the third merging blocks does not exist in the at least one third merging block; and taking all the merging blocks in the row corresponding to the fifth merging block as second-class merging blocks.

The method for managing NVM bad blocks according to any one of the first to fifteenth aspects of the present application proposes a method for managing NVM bad blocks according to the first aspect of the present application, further comprising: the type of the merging block corresponding to each first merging block in the first information table is adjusted from the bad merging block of primary merging to the good merging block of secondary merging, so as to obtain a second information table; or generating a second information table, wherein each entry in the second information table contains information of the merging blocks which are merged twice, and the index of each entry in the second information table is the same as the index of the first merging block in the corresponding first information table.

The method for managing NVM bad blocks according to any one of the third to sixteenth aspects of the present application proposes a seventeenth NVM bad block management method according to the first aspect of the present application, further comprising: and generating a third information table according to the second information table and the association relation, wherein each entry in the third information table contains source information of each physical block in the good merging blocks which are merged twice.

According to a seventeenth NVM bad block management method of the first aspect of the present application, a method for eighteenth NVM bad block management according to the first aspect of the present application is provided, the source information includes at least one of the following information: of the two physical blocks constituting the good merging block of the secondary merging, the high bit of the information of the respective physical blocks constituting the merging block, which provide the merging block of the first physical block, indicates the good physical block, the low bit indicates the bad physical block, the high bit of the information of the respective physical blocks constituting the merging block, which provide the merging block of the second physical block, indicates the good physical block, and the low bit indicates the bad physical block; providing low bits of information of each physical block constituting the merged block of the first physical block to indicate a good physical block, high bits to indicate a bad physical block, and providing low bits of information of each physical block constituting the merged block of the second physical block to indicate a bad physical block, high bits to indicate a good physical block; providing high bits of information of each physical block constituting the merged block of the first physical block to indicate good physical blocks, low bits to indicate good physical blocks, and low bits of information of each physical block constituting the merged block of the second physical block to indicate good physical blocks, and high bits to indicate bad physical blocks; the high bits of the information of the respective physical blocks constituting the merged block of the first physical block indicate bad physical blocks, the low bits indicate good physical blocks, and the high bits of the information of the respective physical blocks constituting the merged block of the second physical block indicate bad physical blocks.

The seventeenth or eighteenth NVM bad block management method according to the first aspect of the present application proposes a nineteenth NVM bad block management method according to the first aspect of the present application, further comprising: the second information table, the third information table, and the association relationship are stored in a specified physical block of each Logical Unit (LUN).

According to the nineteenth NVM bad block management method of the first aspect of the present application, a twenty-first NVM bad block management method according to the first aspect of the present application is provided, and the association relationship is stored in the form of an address mapping table.

According to a sixteenth to twentieth of the first aspect of the present application, there is provided a method for managing a twenty-first NVM bad block according to the first aspect of the present application, the information of the merge block corresponding to the first merge block in the second information table, including: a flag bit, a type of the first merge block, and a type of a second merge block corresponding thereto, wherein the flag bit is used to flag whether a bad block in the first merge block can be replaced by the second merge block.

According to a twenty-first NVM bad block management method of the first aspect of the present application, a twenty-second NVM bad block management method of the first aspect of the present application is provided, the information of the merge block occupies 8 bits, wherein the flag bit occupies 1 bit, the type of the second merge block and the type of the first merge block each occupy 3 bits.

According to a second aspect of the present application there is provided a control unit according to the second aspect of the present application comprising a processor and a memory, the memory storing program code which, when executed by the processor, performs the method of NVM bad block management of any of the first to twenty-second aspects.

According to a third aspect of the present application, there is provided a method of processing an IO command according to the first aspect of the present application, comprising: receiving an I/O command sent by a host, and acquiring a merging block to be accessed by the I/O command; acquiring one or more physical blocks constituting a merged block; one or more physical blocks of the merge block are accessed in response to the I/O command.

According to a first method for processing IO commands in a third aspect of the present application, a second method for processing IO commands in a third aspect of the present application is provided, wherein the merging blocks include a primary merging good merging block and a secondary merging good merging block, the primary merging good merging block is a merging block obtained by primary merging of at least two good physical blocks, and the primary merging good merging block is a good physical block; the good merging block of the secondary merging refers to a merging block obtained by merging the first merging block and the good physical block in the second merging block corresponding to the first merging block, all physical blocks of the good merging block of the secondary merging are good physical blocks, the first merging block and the second merging block are merging blocks which are merged at one time, the first merging block at least comprises a bad physical block, the second merging block at least comprises a good physical block, and the good physical block in the second merging block can replace the bad physical block in the first merging block for data storage.

According to a third aspect of the present application, there is provided a method for processing an IO command according to the third aspect of the present application, for obtaining one or more physical blocks constituting a merge block, comprising: judging whether the merging block is a good merging block of primary merging or a good merging block of secondary merging; if the merge block is a one-time-merge good merge block, one or more physical blocks in the one-time-merge good merge block are determined according to the number or index of the one-time-merge good merge block.

According to the third method for processing IO command in the third aspect of the application, a fourth method for processing IO command in the third aspect of the application is provided, and the method further comprises: if the merging block is a good merging block of the secondary merging, inquiring a third information table to obtain good physical blocks corresponding to the good merging block of the secondary merging, wherein each entry in the third information table contains source information of each physical block in the good merging block of the secondary merging.

According to a fifth method for processing IO commands according to the third aspect of the present application, a method for accessing a memory device according to the sixth aspect of the present application is provided, and if the I/O command is a read command or a write command, a physical block of the merge block is accessed in response to the I/O command.

According to a fourth or fifth method of handling IO commands according to the third aspect of the present application, a sixth method of handling IO commands according to the third aspect of the present application is presented, wherein if the I/O command is an erase command, all physical blocks of the merge block are erased in response to the I/O command.

According to the fourth or fifth method for processing IO command in the third aspect of the present application, a seventh method for processing IO command in the third aspect of the present application is provided, further comprising: receiving a write command sent by a host, selecting a merging block from unassigned merging blocks, and assigning a storage space corresponding to the merging block to the write command; and writing data into the storage space according to the write command.

According to a seventh method for processing an IO command according to the third aspect of the present application, there is provided a method for processing an IO command according to the eighth aspect of the present application, wherein the allocating a memory space corresponding to the merge block to the write command includes: identifying whether the merge block is a good merge block for secondary merge; if yes, obtaining source information of each physical block in the merging block by inquiring a third information table, and distributing storage spaces corresponding to part or all of the physical blocks in the merging block to the write command according to the source information.

According to a fourth or eighth method for processing IO commands in the third aspect of the present application, a ninth method for processing IO commands in the third aspect of the present application is provided, a read command sent by a host is received, and a physical address of a physical block corresponding to a logical block address pair carried by the read command is queried according to an FTL table; and reading data from the physical block corresponding to the physical address according to the read command, and sending the data to the host.

According to a fourth aspect of the present application, there is provided a first method of processing an IO command according to the fourth aspect of the present application, characterized by comprising: receiving a write command sent by a host; selecting a merge block from the unwritten merge blocks; allocating memory space from the selected merge block; writing the data corresponding to the write command into the allocated storage space; and recording the logical block address corresponding to the write command and the physical address of the allocated storage space.

According to the first method for processing IO command of the fourth aspect of the present application, there is provided the second method for processing IO command of the fourth aspect of the present application, further comprising: receiving a read command sent by a host; inquiring a physical address corresponding to the logical block address accessed by the read command; and reading data from the storage space corresponding to the physical address to respond to the read command.

According to a fourth aspect of the present application, there is provided a method for processing IO commands according to the third aspect of the present application, wherein the allocating memory space from the selected merge block includes, if the selected merge block is a good merge block for one merge, determining one or more physical blocks according to the selected merge block number; if the selected merging block is a good merging block of secondary merging, inquiring an information table to determine one or more physical blocks; the storage space is allocated from the one or more physical blocks.

According to a third method of processing IO commands of the fourth aspect of the present application, there is provided a method of processing IO commands of the fourth aspect of the present application, wherein it is determined whether the selected merge block is a primary merged good merge block or a secondary merged good merge block, based on a block number lookup information table of the selected merge block.

According to one of the first to fourth methods of processing an IO command according to the fourth aspect of the present application, there is provided a fifth method of processing an IO command according to the fourth aspect of the present application, wherein the merge blocks include a primary merged good merge block and a secondary merged good merge block, wherein the primary merged good merge block refers to a merge block obtained by primary merging of at least two good physical blocks, and the primary merged good merge block is a good physical block; the good merging block of the secondary merging refers to a merging block obtained by merging the first merging block and the good physical block in the second merging block corresponding to the first merging block, all physical blocks of the good merging block of the secondary merging are good physical blocks, the first merging block and the second merging block are merging blocks which are merged at one time, the first merging block at least comprises a bad physical block, the second merging block at least comprises a good physical block, and the good physical block in the second merging block can replace the bad physical block in the first merging block for data storage.

According to a fifth aspect of the present application there is provided a control unit according to the fifth aspect of the present application comprising a processor and a memory, the memory storing program code which, when executed by the processor, performs the method of accessing the storage device of any of the third and fourth aspects.

Compared with the prior art, the scheme provided by the embodiment of the application has at least the following beneficial effects:

1. in the scheme provided by the embodiment of the application, the control part records the information of the merging block which is obtained by merging at least two physical blocks at one time in each entry of the first information table, namely the control part can record the information of a plurality of physical blocks through each entry of the first information table, so that the control part can consume less memory resources as much as possible to store the physical block information.

2. The control part records the association relation between the first physical address of the bad physical block in the first merging block and the second physical address of the good physical block in the corresponding second merging block besides the information of the merging blocks which are merged once, merges the good physical block in the first merging block with the good physical block in the second merging block according to the association relation to obtain a good physical block which is merged twice, and constructs a logic block space which does not contain the bad physical block and has continuous addresses under the condition that the NVM chip can have the natural bad physical block so as to be convenient for upper layer use and further improve the performance of the storage device.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.

FIG. 1 illustrates a block diagram of a prior art memory device;

FIG. 2 illustrates a detailed block diagram of the control components of the storage device;

FIG. 3A shows a prior art block construction schematic;

FIG. 3B shows a schematic diagram of a logic cell and Plane;

FIG. 4A is a schematic diagram showing the structure of a first information table of the present application;

FIG. 4B is a flow chart illustrating the NVM bad block management method of the present application;

FIG. 4C shows a schematic diagram of a first type of merge block and a second type of merge block of the application;

FIG. 5A shows a schematic diagram of a first merge block and a second merge block within the same logical unit of the present application;

FIG. 5B illustrates a schematic diagram of a first merge block and a second merge block within a further same logical unit of the present application;

FIG. 5C illustrates a schematic diagram of a first binning block and a second binning block within the same plane of the same logic unit of the present application;

FIG. 5D illustrates a schematic diagram of a first binning block and a second binning block within the same plane of yet another same logic unit of the present application;

FIG. 5E shows a schematic diagram of a twice-consolidated good consolidated block resulting from the twice-consolidation of the present application;

FIG. 5F is a schematic diagram of a further secondary merge of the present application resulting in a secondary merged good merge block;

FIG. 5G shows a schematic diagram of a further secondary merge of the present application resulting in a secondary merged good merge block;

FIG. 6A shows a schematic diagram of a second information table of the present application;

FIG. 6B is a schematic diagram showing the structure of a second information table according to the present application;

FIG. 6C is a diagram showing information of a merging block corresponding to a first merging block in a second information table according to the present application;

FIG. 6D is a schematic diagram of a third information table according to an embodiment of the present application;

fig. 7 shows a flowchart of another NVM bad block management method according to an embodiment of the present application.

FIG. 8A illustrates a flow chart of a method of memory device access of the present application;

FIG. 8B is a schematic diagram of responding to a read command provided by an embodiment of the present application;

FIG. 8C shows a schematic diagram of responding to a write command provided by an embodiment of the present application;

FIG. 8D shows a schematic diagram of yet another response read command provided by an embodiment of the present application;

FIG. 8E shows a schematic diagram of responding to an erase command provided by an embodiment of the present application;

FIG. 9A shows a schematic diagram of responding to a write command provided by yet another embodiment of the present application;

FIG. 9B shows a schematic diagram of responding to a read command provided by another embodiment of the present application;

fig. 10 shows a schematic structural view of the control unit of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Fig. 4A is a schematic structural diagram of a first information table according to an embodiment of the present application.

For example, the index of the merging block corresponding to each entry in the first information table may be the block number of the merging block, or may be the physical address of the merging block on the NVM chip; the merge block corresponding to each entry in the first information table may be composed of two or more physical blocks. The first information table shown in fig. 4A is constructed with the block numbers of the index as the merge blocks, each merge block containing two physical blocks (a first physical block and a second physical block).

As shown in fig. 4A, the first information table includes 3 entries, namely an entry 0, an entry 1 and an entry 2, each of which includes an index of a merging block, a type of the merging block and information of each physical block in the merging block, where a block number of the merging block corresponding to the entry 0 is 0, the type of the merging block is a good merging block for once merging, physical blocks 0-0 indicated by high bits in each physical information in the merging block are good physical blocks, and physical blocks 0-1 indicated by low bits are also good physical blocks; the block number of the merging block corresponding to the item 1 is 1, the type of the merging block is a bad merging block which is merged at one time, a physical block 1-0 indicated by high bits in each physical information in the merging block is a bad physical block, and a physical block 1-1 indicated by low bits is also a bad physical block; the block number of the merging block corresponding to the item 2 is 2, the type of the merging block is a bad merging block which is merged at one time, the physical block 2-0 indicated by the high bit in each physical information in the merging block is a good physical block, and the physical block 2-1 indicated by the low bit is also a bad physical block. It should be understood that the physical block merging in the embodiment of the present application does not refer to physical merging, but an operation unit corresponding to operations such as data reading/writing/erasing. For example, in response to an erase command, all physical blocks of the merge block are erased simultaneously. There are a variety of ways to compose a merge block that is merged at a time, including but not limited to: consists of at least two adjacent physical blocks with physical addresses in the same LUN and/or plane (plane); or from physical blocks of the same physical address in multiple planes of the same Logical Unit (LUN).

According to an embodiment of the application, referring also to fig. 4A, the plurality of entries of the first information table record information of all the once-consolidated merge blocks (also referred to as once-consolidated merge block information) of the NVM.

Further, the types of physical blocks in the storage device include good physical blocks and bad physical blocks, wherein a good physical block refers to a physical block capable of performing operations such as data read/write/erase, and the bad physical block is identified by a known or future generation manner. Since there are two types of physical blocks, the type of a merging block that is once composed of at least two physical blocks may exist in various forms. For example, taking the example that each merging block of one merging contains two physical blocks, the composition of the merging block of one merging includes two bad physical blocks, two good physical blocks, or one bad physical block and one good physical block. As an example, a once-merged merge block that is entirely composed of good physical blocks is referred to as a once-merged good merge block, and a once-merged merge block that contains bad physical blocks is referred to as a bad merge block. Bad merge blocks in turn contain two cases: all physical blocks are bad physical blocks or contain good physical blocks and bad physical blocks. As an example, all physical blocks are bad physical blocks, referred to as bad merge blocks of a first type, and containing good physical blocks and bad physical blocks are referred to as bad merge blocks of a second type.

As another example, the merging block information of one merging includes: the type of the merging block which is merged at one time and the information of each physical block constituting the merging block, wherein the type of the merging block comprises a good merging block and a bad merging block which are merged at one time, and the bad merging block comprises a bad merging block of a first type and a bad merging block of a second type.

Further, in the scheme provided by the embodiment of the application, when the control unit stores the first information table, the information of each physical block forming the merging block in each entry occupies a plurality of bits, the number of bits is the same as the number of physical blocks contained in each merging block, and the information of one physical block is stored in each bit. For example, taking the example that each merging block contains two physical blocks, the information of each physical block constituting the merging block in each entry occupies 2 bits, and each bit stores the information of one physical block. Since a physical block contains two cases of good and bad, the information (2 bits) of each physical block constituting a block of a bad block composed of two physical blocks includes two forms as follows: the high bit indicates a good physical block and the low bit indicates a merging block of a bad physical block, or the high bit indicates a bad physical block and the low bit indicates a merging block of a good physical block, wherein the high bit and the high bit refer to the high bit and the high bit of two bits occupied by information of each physical block constituting the merging block.

Fig. 4B shows a flowchart of an NVM bad block management method according to an embodiment of the present application. The process illustrated in FIG. 4B is performed to build a merge block, for example, on a manufacturing line that manufactures the storage device, or when the storage device is powered up.

In step 401, the control unit scans a physical block in each Logical Unit (LUN) to generate a first information table.

For example, the control component scans the bad block table of each LUN storing bad block (physical block) information, and optionally by accessing the physical blocks to identify good and bad blocks, and generates a first information table as illustrated in FIG. 4A for each LUN. Alternatively, the first information table is recorded at the start position of the merge block No. 0 of each LUN.

In step 402, the control unit obtains the first merging block and the corresponding second merging block according to the first information table.

Specifically, since the information of all the once-merged merging blocks of the NVM recorded in the first information table includes the once-merged good merging block (each physical block constituting the merging block is a good physical block) information and the bad merging block (there is a bad physical block in the physical blocks constituting the merging block) information, that is, there may be bad merging blocks that cannot be used in the once-merged merging block, in order to make all the merging blocks usable in a large block constructed on the NVM as much as possible, or to make as many merging blocks usable as possible. By way of example, some of the primary merged blocks (at least the merged block with the good physical block and at least the merged block with the bad physical block) in the NVM may be twice merged to obtain a twice merged good merged block that can be used.

Further, in order to obtain a good merge block of the secondary merge that can be used for the secondary merge, it is necessary to select a merge block (a first merge block and a second merge block) that can be subjected to the secondary merge from all the merge blocks of the primary merge.

In the scheme provided by the embodiment of the application, the control part determines a plurality of modes of the first merging block and the second merging block corresponding to the secondary merging, and as an example, the control part determines the first merging block and the second merging block according to the first information table, determines at least one first merging block from the first merging blocks and determines the second merging block corresponding to each first merging block from the second merging blocks. The first merge block refers to a merge block containing one-time merge of bad physical blocks, for example, the first merge block is a bad physical block for part or all of the physical blocks; the second merge block refers to a merge block that contains a good physical block that can replace a bad physical block in the first merge block for data storage, e.g., the second merge block is a good physical block that is all or part of the physical blocks. The processor divides the merging blocks which are merged at one time into two types according to the types of all the merging blocks in the first information table and the physical block information of the merging blocks, wherein the merging blocks of the first type are different from the merging blocks of the second type, the merging blocks of the first type comprise the first merging blocks, and the merging blocks of the second type comprise the second merging blocks.

Further, there are various ways in which the control unit determines the first type of binning block and the second type of binning block in order to make as large a block as possible out of the chunks constructed on the NVM, all binning blocks can be used, or as many binning blocks as possible can be used, while breaking down as few chunks as possible to provide good physical blocks for other chunks. In one possible implementation manner, the control unit determines the number of bad merging blocks in each big block of the storage device according to the first information table, and determines the first type of merging block and the second type of merging block according to the number of bad merging blocks in each big block.

Optionally, the control unit takes all the merging blocks in a specified number of first large blocks with the largest bad merging blocks or all the merging blocks including at least one good physical block as second-class merging blocks, and acquires the first-class merging blocks from the merging blocks of other large blocks except the first large blocks in the storage device; or taking all the merging blocks in the second big blocks with the quantity larger than the preset threshold value or all the merging blocks comprising at least one good physical block as second-type merging blocks, and acquiring the first-type merging blocks from the merging blocks of other big blocks except the second big blocks in the storage device.

Specifically, the control unit determines the number of bad blocks in each big block, and then selects a first big block from all big blocks according to the number of bad blocks in each big block, wherein the first big block includes but is not limited to: the large blocks with the largest number of bad merging blocks in all large blocks are larger than the specified number of large blocks or are sorted from more to less according to the number of bad merging blocks, and the specified number of large blocks are selected from the sequence. The control section acquires a second type of merging block from the first large block, and acquires a first type of merging block from all the merging blocks except the first large block, for example, takes all the merging blocks except the first large block as the first type of merging block, or selects a merging block containing at least a bad physical block from all the merging blocks except the first large block as the first type of merging block.

Fig. 4C illustrates a schematic diagram of a first type of merge block and a second type of merge block in a storage device according to an embodiment of the present application.

According to an embodiment of the application, a large block includes multiple consolidated blocks from individual LUNs. By way of example, each merge block belonging to the same chunk has the same chunk address or merge block number.

As shown in fig. 4C, chunk 0 includes a merged block 0 (constituted by, for example, physical block 0 and physical block 1) from each of 16 logical units, chunk 1 is constituted by a merged block 1 (constituted by, for example, physical block 2 and physical block 3) from each of logical units, chunk 2 is constituted by a merged block 2 (constituted by, for example, physical block 4 and physical block 3) from each of logical units, and chunk N includes a merged block N (constituted by, for example, physical block 2N and physical block 2n+1) from each of logical units. If the big block N is the big block with the largest bad merging block number in all the big blocks, the second merging block is obtained from the big block N, and the first merging block is obtained from the big blocks 0-N-1.

Further, in the solution provided in the embodiment of the present application, the control unit determines at least one first merging block from the first merging blocks and determines a second merging block corresponding to each first merging block from the second merging blocks, which includes but is not limited to:

in one possible implementation, for a merging block a of a first type of merging block, if there are one or more merging blocks B of a second type of merging block that are not allocated and are within the same logical unit as the merging block a, the control unit allocates a merging block B closest to the physical address of the merging block a to the merging block a, and takes the merging block a and the allocated merging block B as corresponding first merging block and second merging block.

Fig. 5A shows a schematic diagram of a first merge block and a second merge block in the same logic unit according to an embodiment of the present application.

As shown in fig. 5A, in the logical unit LUN0, there are a merge block a of the first type of merge block and merge blocks B1 and B2 of the second type of merge block, wherein the merge block a contains bad physical blocks, the merge block B1 and the merge block B2 each contain good physical blocks, and neither the merge block B1 nor the merge block B2 is allocated with the first merge block corresponding thereto. If the distance between the block B1 and the block a is smaller than the distance between the block B2 and the block a in the LUN0, the block a is taken as a first block, and the block B1 is taken as a second block corresponding to the first block. Where "distance" refers to the distance between the NVM chip at the actual physical location or physical address of merge block a and merge block B1.

In yet another possible implementation manner, for the merging block a of the first type of merging block, if there is no merging block B of the second type of merging block that is not allocated and is in the same logical unit as the merging block a, the control unit takes the merging block of the large block where the merging block a is located as the merging block of the second type.

FIG. 5B is a schematic diagram of a first merge block and a second merge block within a same logical unit according to an embodiment of the present application.

As shown in fig. 5B, in the logical unit LUN0, there are the merged blocks A1, A2 and A3 of the first type merged block and the merged blocks B1 and B2 of the second type merged block, where the merged blocks A1, A2 and A3 contain bad physical blocks, the merged block B1 and the merged block B2 each contain good physical blocks, and the merged block B1 is allocated to the first merged block A1 corresponding thereto, the merged block B2 is allocated to the first merged block A2 corresponding thereto, that is, all the second type merged blocks in the LUN0 are allocated, there are no unallocated second type merged blocks, and for the merged block A3 there are no matched second type merged blocks, the merged block (containing the good physical block) of the large block where the merged block A3 is located is taken as the second type merged block, for providing the good physical block for other first type merged blocks.

In yet another possible implementation, for the merging block a of the first type of merging block, if there are one or more merging blocks (B1, B2) of the second type of merging block that are not allocated and are in the same plane within the same logical unit as the merging block a, the control unit allocates the merging block B1 closest to the physical address of the merging block a to the merging block a, and takes the merging block a and the allocated merging block B1 as the corresponding first merging block and the second merging block.

Fig. 5C shows a schematic diagram of a first merge block and a second merge block in the same plane of the same logic unit provided by an embodiment of the present application.

As shown in fig. 5C, a plurality of planes (planes) are included in the logical unit LUN0, PL0 … PLN, respectively. If there are the merging blocks A1 and A2 of the first type of merging blocks and the merging blocks B1 and B2 of the second type of merging blocks in PL0, where the merging blocks A1 and A2 include bad physical blocks, the merging blocks B1 and B2 each include good physical blocks, and neither the merging block B1 nor the merging block B2 is allocated with the corresponding first merging block, if the distance between the merging block B1 and the merging block A1 is smaller than the distance between the merging block B2 and the merging block A1, the merging block A1 is taken as the first merging block, the merging block B1 is taken as the corresponding second merging block, and the merging block B2 closest to the merging block A1 is taken as the corresponding second merging block, that is, all the second type of merging blocks in PL0 are allocated, and there is no unallocated second type of merging block.

In yet another possible implementation manner, for the merging block a of the first type of merging block, if there is no merging block B of the second type of merging block that is not allocated and is in the same plane as the merging block a in the same logical unit, the control unit takes the merging block of the big block where the merging block a is located as the merging block of the second type. So that the merge block a and other merge blocks of the chunk where the merge block a is located can be allocated as a second type of merge block to the merge blocks of other chunks.

FIG. 5D is a schematic diagram of a first merge block and a second merge block in the same plane of a further same logic cell according to an embodiment of the present application.

As shown in fig. 5D, a plurality of planes (planes) are included in the logical unit LUN0, which are planes 0 (PL 0) … Plane N (PLN), respectively. If there are the merging blocks A1, A2 and A3 of the first type of merging blocks and the merging blocks B1 and B2 of the second type of merging blocks in PL0, where the merging blocks A1, A2 and A3 contain bad physical blocks, the merging block B1 and the merging block B2 each contain good physical blocks, and the merging block B1 is allocated to the corresponding first merging block A1, the merging block B2 is allocated to the corresponding first merging block A2, that is, all the second type of merging blocks are allocated in PL0, there are no unassigned second type of merging blocks, and for the merging block A3 there is no matching second type of merging block, the merging block of the large block where the merging block A3 is located is taken as the second type of merging block.

In yet another possible implementation manner, the control unit determines a plurality of third merging blocks and a first number thereof from first merging blocks in a same Logical Unit (LUN) and a plurality of fourth merging blocks and a second number thereof from second merging blocks according to a first information table, where the third merging blocks include good physical blocks and bad physical blocks, and the fourth merging blocks include good physical blocks or both good physical blocks and bad physical blocks; the first and second merge blocks are determined based on the first and second numbers.

In yet another possible implementation manner, if the first number is not greater than the second number, the control unit takes each third merging block as a first merging block, and takes a fourth merging block closest to each first merging block as its corresponding second merging block; or if the first number is larger than the second number, the control part makes each fourth merging block be the most one second merging block, and takes the first merging block closest to each second merging block as the corresponding first merging block.

In yet another possible implementation manner, if the first number is greater than the second number, the control unit determines that the fifth merging block of the at least one third merging block does not have the second merging block corresponding to the fifth merging block; and taking all the merging blocks in the row corresponding to the fifth merging block as second-class merging blocks.

In step 403, the control unit determines and records the association between the first physical address of the bad physical block in the first merged block and the second physical address of the good physical block in the corresponding second merged block.

Specifically, the control unit determines a first physical address of a bad physical block in each first merging block and a second physical address of a good physical block in a corresponding second merging block, and records an association relationship between the first physical address and the second physical address. After recording the association relation between the first physical address and the second physical address, the control part can merge the good physical blocks in the first merging block and the second merging block corresponding to the first merging block according to the association relation to obtain a good merging block for secondary merging; the number of physical blocks of the good merging blocks of the secondary merging is the same as that of the physical blocks of the merging blocks, and all the physical blocks of the good merging blocks of the secondary merging are good physical blocks.

Further, there are two cases of bad merge blocks that merge at one time: the first case is that all physical blocks constituting the merge block are bad blocks; the second case is that some physical blocks among all physical blocks constituting the merge block are bad blocks and some physical blocks are good blocks. For example, for the first case of bad merging blocks, that is, all physical blocks in the first merging block are bad physical blocks, a good merging block which is merged once can be selected from the first big block as a second merging block, all good physical blocks in the second merging block and all bad physical blocks in the first merging block are replaced to obtain a good merging block which is merged twice, or a bad merging block which is merged once and at least comprises one good physical block is selected from the first big block as a second merging block, and all bad physical blocks in the first merging block are replaced by good physical blocks in a plurality of second merging blocks to obtain a good merging block which is merged twice; for the second bad merging block, namely, the first merging block comprises good physical blocks and bad physical blocks, the good merging block which is merged once or the bad merging block which comprises the good physical blocks and the bad physical blocks and is merged once can be selected from the first big block to be used as the second merging block, and the good physical blocks in the second merging block and the bad physical blocks of the first merging block are replaced to obtain the good merging block which is merged twice.

Fig. 5E shows a schematic diagram of a good merging block obtained by twice merging according to an embodiment of the present application. Where, for example, the first merge block is a block containing good and bad physical blocks, and the second merge block is a block containing good and bad physical blocks, the schematic diagram of the resulting secondary merged good merge block shown in FIG. 5E is performed.

As shown in fig. 5E, the plane 0 (PL 0) includes four once-merged merging blocks, which are respectively a merging block 0, a merging block 1, a merging block 2 and a merging block 3, wherein the merging block 0 and the merging block 1 are once-merged bad merging blocks, the merging block 2 and the merging block 3 are once-merged good merging blocks, the merging block 0 includes bad physical blocks 0-0 and good physical blocks 0-1, and the merging block 1 includes bad physical blocks 1-0 and good physical blocks 1-1. When the merging block 0 is a first merging block and the merging block 1 is a second merging block, the good physical block 1-1 in the merging block 1 is substituted for the bad physical block 0-0 in the merging block 0 to obtain a good merging block of secondary merging, wherein the good merging block of secondary merging comprises the physical block 0-1 and the physical block 1-1.

Fig. 5F shows a schematic diagram of a good merging block obtained by performing a second merging according to another embodiment of the present application. Where, for example, the first merge block is a block containing good physical blocks and bad physical blocks, and the second merge block is a block containing all physical blocks as good physical blocks, performing the method illustrated in FIG. 5F results in a schematic diagram of a twice merged good merge block.

As shown in fig. 5F, plane 0 (PL 0) includes four once-merged merging blocks, which are respectively merging block 0, merging block 1, merging block 2 and merging block 3, wherein merging block 0 and merging block 1 are once-merged bad merging blocks, merging block 2 and merging block 3 are once-merged good merging blocks, merging block 0 includes bad physical blocks 0-0 and good physical blocks 0-1, and merging block 2 includes good physical blocks 2-0 and good physical blocks 2-1. When the merging block 0 is a first merging block and the merging block 2 is a second merging block, the good physical block 2-0 in the merging block 2 is substituted for the bad physical block 0-0 in the merging block 0 to obtain a good merging block of secondary merging, wherein the good merging block of secondary merging comprises the physical block 0-1 and the physical block 2-0.

FIG. 5G is a schematic diagram of a good merging block obtained by performing a second merging according to an embodiment of the present application. The schematic diagram of the resulting secondary merged good merged block shown in fig. 5E is performed where, for example, the first merged block is a bad physical block that includes all physical blocks and the second merged block is a good physical block that includes all physical blocks.

As shown in fig. 5F, the plane 0 (PL 0) includes four once-merged merging blocks, which are respectively a merging block 0, a merging block 1, a merging block 2 and a merging block 3, wherein the merging block 0 and the merging block 1 are once-merged bad merging blocks, the merging block 2 and the merging block 3 are once-merged good merging blocks, the merging block 0 includes bad physical blocks 0-0 and bad physical blocks 0-1, and the merging block 2 includes good physical blocks 2-0 and good physical blocks 2-1. When the merging block 0 is a first merging block and the merging block 2 is a second merging block, the good physical block 2-0 and the good physical block 2-1 in the merging block 2 are used for replacing the bad physical block 0-0 and the bad physical block 0-1 in the merging block 0 to obtain a good merging block which is merged twice, wherein the good merging block which is merged twice comprises the physical block 2-0 and the physical block 2-1.

Further, after obtaining the twice-merged merging blocks, in order to record the information of the twice-merged merging blocks, the control part adjusts the merging block type corresponding to each first merging block in the first information table from the bad merging block merged once to the good merging block merged twice to obtain a second information table; or generating a second information table, wherein each entry in the second information table contains information of the merging blocks which are merged twice, and the index of each entry in the second information table is the same as the index of the first merging block in the corresponding first information table. As an example, the information of the secondarily merged block in the second information table may include only the type of the secondarily merged good merged block, or may include both the type of the secondarily merged good merged block and the information (source and/or physical address) of each physical block constituting the good merged block of the secondarily merged block.

Fig. 6A is a schematic structural diagram of a second information table according to an embodiment of the present application.

The second information table shown in fig. 6A is constructed by adding an information entry of at least one secondary merge block to the first information table and the information of the secondary merge block in the second information table contains only the type of the secondary merge block. As shown in fig. 6A, the first information table includes 5 entries, namely an entry 0, an entry 1, an entry 2 and an entry 3, wherein the entry 0, the entry 1 and the entry 2 include merging block information of a primary merging block, and the entry 3 includes merging block information of a secondary merging block, wherein information of each physical block in the merging block is 2 bits, and each bit indicates information of one physical block. Specifically, the block number of the merging block corresponding to the entry 0 is 0, the type of the merging block is a good merging block which is merged at one time, the good merging block comprises a physical block 0-0 indicated by high bits and a physical block 0-1 indicated by low bits, and the physical block 0-0 and the physical block 0-1 are both good physical blocks; the block number of the merging block corresponding to the item 1 is 1, the type of the merging block is a bad merging block which is merged at one time, the bad merging block comprises a physical block 1-0 indicated by high bits and a physical block 1-1 indicated by low bits, the physical block 1-0 is a good physical block, and the physical block 1-1 is a bad physical block; the block number of the merging block corresponding to the entry 2 is 2, the type of the merging block is a bad merging block merged at one time, the bad merging block comprises a physical block 2-0 indicated by high bits and a physical block 2-1 indicated by low bits, the physical block 2-0 is a good physical block, and the physical block 2-1 is a bad physical block.

Further, in fig. 6A, the primary merged bad merged block corresponding to the entry 1 is a first type merged block, the primary merged bad merged block corresponding to the entry 2 is a second type merged block, and the primary merged bad merged blocks corresponding to the entries 1 and 2 are merged (the physical block 1-1 corresponding to the entry 1 is replaced by the physical block 2-0 corresponding to the entry 2) to obtain a secondary merged good merged block. And adding a target in the first information table to record a second information table. The index (block number 1) of the merging block indicated by the entry 1 as the first-type merging block in the secondary contract is taken as the index of the entry of the second information table, the type of the merging block in the entry of the second information table is marked as a good merging block for secondary merging, and the information of each physical block of the target merging block is marked as a good merging block.

Alternatively, the second information table is generated by modifying an entry in the first information table, for example, the type of the merge block of the entry indexed as block number 1 in the first information table is updated to a twice-merged good merge block, while the other information is unchanged.

Fig. 6B is a schematic structural diagram of a second information table according to an embodiment of the present application.

The second information table shown in fig. 6B is constructed by generating a separate second information table to record the secondarily-merged block information, and the information of the secondarily-merged block in the second information table contains only the type of the secondarily-merged block.

For example, in the first information table, the merging block corresponding to the entry 0 is a bad merging block for one-time merging, the index is the block number 0, the included physical blocks are the physical blocks 0-0 (bad physical block) indicated by the high bit and the physical blocks 0-1 (good physical block) indicated by the low bit, the merging block corresponding to the entry 1 is a bad merging block for one-time merging, the index is the block number 1, and the included physical blocks are the physical blocks 1-0 (good physical block) indicated by the high bit and the physical blocks 1-1 (bad physical block) indicated by the low bit. If the primary-merged bad merged block corresponding to the entry 0 is the first-class merged block, and the primary-merged bad merged block corresponding to the entry 1 is the second-class merged block, merging the primary-merged bad merged blocks corresponding to the entry 0 and the entry 1 in the first information table to obtain a second information table shown in fig. 6B. Entry 0 is contained in the second information table; the index corresponding to the entry 0 in the second information table is the same as the index corresponding to the entry 0 in the first information table, the entry 0 in the second information table contains good merging blocks of the secondary merging, and all physical blocks in the good merging blocks of the secondary merging are good physical blocks.

Alternatively, in fig. 6B, the index of the entry of the first information table is the position of the entry in the first information table, and the position corresponds one-to-one to the block number of the merge block represented by the entry. And the index of the entry of the second information table is the block number of the merging block represented by the entry, and the entry is provided in the second information table only for the good merging block of the second merging, but not for the bad merging block of the second merging.

Fig. 6C is a schematic diagram showing information of a merging block corresponding to the first merging block in the second information table according to the embodiment of the present application.

As shown in fig. 6C, the merging block information of any first merging block occupies 8 bits, which are a flag bit, a type of the second merging block, and a type of the first merging block in this order, wherein the flag bit occupies 1 bit, and the type of the second merging block and the type of the first merging block each occupy 3 bits. The 3 bits occupied by the type of the first merging block and the type of the second merging block may be consecutive 3 bits or may be separated 3 bits, which is not limited herein.

Further, after the first merging block and the second merging block are merged to obtain a twice-merged good merging block, the control unit may further generate a third information table according to the second information table and the association relationship, where the third information table includes a plurality of entries, and each entry includes source information of each physical block in the twice-merged good merging block.

Fig. 6D shows a schematic structural diagram of a third information table according to an embodiment of the present application.

The third information table shown in fig. 6D is constructed so that a separate second information table is generated to record the information of the secondarily-merged block, and the information of the secondarily-merged block in the second information table contains only the type of the secondarily-merged block. For example, in the first information table, the merging block corresponding to the entry 0 is a bad merging block for one-time merging, the index is the block number 0, the included physical blocks are the physical blocks 0-0 (bad physical block) indicated by the high bit and the physical blocks 0-1 (good physical block) indicated by the low bit, the merging block corresponding to the entry 1 is a bad merging block for one-time merging, the index is the block number 1, and the included physical blocks are the physical blocks 1-0 (good physical block) indicated by the high bit and the physical blocks 1-1 (bad physical block) indicated by the low bit. If the primary-merging bad merging block corresponding to the entry 0 is the first-class merging block, the primary-merging bad merging block corresponding to the entry 1 is the second-class merging block, merging the primary-merging bad merging block corresponding to the entry 0 and the entry 1 in the first information table to obtain the entry 0 in the second information table, wherein the merging block corresponding to the entry 0 in the second information table is the secondary-merging good merging block, the index is the block number 0, and all physical blocks corresponding to the merging blocks are good physical blocks. Obtaining a third information table according to the information of good physical blocks in the bad merging blocks of primary merging corresponding to the entry 0 and the entry 1 in the first information table, wherein the third information table comprises the entry 0, the index of the entry 0 is the block number 0, and the source information of each physical block in the merging block refers to the source of the good merging block of secondary merging corresponding to the entry 0 in the second information table, namely the physical block in the good merging block of secondary merging corresponding to the entry 0 in the second information table is from the physical block (physical block 0-1) indicated by low bits in the bad merging block of primary merging with the block number 0 and the physical block (physical block 1-0) indicated by high bits in the bad merging block of primary merging with the block number 1.

In one possible implementation, the source information includes at least one of the following: of the two physical blocks constituting the good merging block of the secondary merging, the high bit of the information of the respective physical blocks constituting the merging block, which provide the merging block of the first physical block, indicates the good physical block, the low bit indicates the bad physical block, the high bit of the information of the respective physical blocks constituting the merging block, which provide the merging block of the second physical block, indicates the good physical block, and the low bit indicates the bad physical block; providing low bits of information of each physical block constituting the merged block of the first physical block to indicate a good physical block, high bits to indicate a bad physical block, and providing low bits of information of each physical block constituting the merged block of the second physical block to indicate a bad physical block, high bits to indicate a good physical block; providing high bits of information of each physical block constituting the merged block of the first physical block to indicate good physical blocks, low bits to indicate good physical blocks, and low bits of information of each physical block constituting the merged block of the second physical block to indicate good physical blocks, and high bits to indicate bad physical blocks; the high bits of the information of the respective physical blocks constituting the merged block of the first physical block indicate bad physical blocks, the low bits indicate good physical blocks, and the high bits of the information of the respective physical blocks constituting the merged block of the second physical block indicate bad physical blocks.

Specifically, in the scheme provided by the embodiment of the application, different sentences can be used for expressing several scenes for generating the good merging blocks of the secondary merging. For example, rpl_low_low=1 indicates that the twice-merged good merged block is merged by a first merged block whose one LOW bit is a good physical block and a second merged block whose one LOW bit is a good physical block; rpl_low_up=2 indicates that the twice-merged good merged block is merged by a first merged block whose lower bit is a good physical block and a second merged block whose upper bit is a good physical block; rpl_up_low=3 indicates that the twice-merged good merged block is merged by a first merged block whose one high bit is a good physical block and a second merged block whose one LOW bit is a good physical block; rpl_up_up=4 indicates that the twice-merged good merged block is merged by a first merged block whose one high bit is a good physical block and a second merged block whose one high bit is a good physical block.

Further, the control unit stores the second information table, the third information table, and the association relationship corresponding to each logical unit in a specified physical block of each Logical Unit (LUN) after generating the first information table, the second information table, the third information table, and the association relationship. For example, the designated physical block may be the first physical block in each logical unit.

In the scheme provided by the embodiment of the application, various modes of storing the association relationship include, but are not limited to, storing in the form of an address mapping table.

Fig. 7 shows a flowchart of another NVM bad block management method according to an embodiment of the present application. The process illustrated in fig. 7 is performed to build a merge block, for example, on a manufacturing line that manufactures the storage device, or when the storage device is powered up.

In step 701, the control unit scans the NVM chip of the memory device, building a Reserved Block pool (Reserved Block pool). Specifically, the control unit scans each physical block in the NVM chip of the storage device, determines the condition (the number of bad blocks and/or the number of good blocks) of the blocks in the NVM chip, constructs a reserved block pool according to the condition of the blocks in the blocks, determines one or more blocks containing the maximum number of bad blocks in the NVM chip according to the condition of the blocks, obtains the block containing at least one good physical block in the one or more blocks, and takes the block as an element in the reserved block pool, wherein the block (as a second type block) in the reserved block pool can be combined with the block (as a first type block) containing both good physical blocks and bad physical blocks in the NVM chip except the element in the reserved block pool to obtain a logical block space formed by all the good physical blocks.

Further, in order to perform secondary merging on the second type of merging blocks in the reserved block pool and the first type of merging blocks in the NVM chip, a logical block space consisting of all good physical blocks is obtained. The control unit determines a first type of merge block by executing step 702. In step 702, the control unit determines whether there is a large block including at least one non-good merge block in the storage device. Specifically, the control unit determines, one by one, whether a chunk of the NVM chip other than one or more chunks having the largest number of bad chunks includes at least one non-good chunk, where a non-good chunk refers to a chunk that includes both good physical and bad physical chunks, i.e., it is the first type of chunk.

Further, if there is a chunk in the NVM chip that contains at least one non-good chunk, then step 703 is performed where the control component obtains the chunk that includes the at least one non-good chunk. And executing step 704, the control unit determines whether none of the non-good merge blocks in the acquired large block can be replaced by a merge block acquired from the reserved block pool. For example, for each non-good merge block, the control unit determines whether at least one or more unassigned merge blocks can be found from the reserved block pool in the same Plane (Plane) or Logical Unit (LUN) as it is, and if so, takes the merge block closest to the non-good merge block as the merge block with which it is replaced.

Further, if none of the non-good merge blocks in the obtained large Block can be replaced by a merge Block obtained from the Reserved Block pool, step 705 is performed, where the control unit replaces none of the good merge blocks in the obtained large Block with a merge Block obtained from the Reserved Block pool. Specifically, the control section replaces the bad physical blocks in the non-good merge blocks with the good physical blocks in the merge blocks acquired from the reserved block pool to obtain a logical block space composed of all the good physical blocks. Otherwise, step 706 is performed to add all the merged blocks in the obtained chunk to the reserved block pool.

Fig. 8A shows a flowchart of a method for accessing a storage device according to an embodiment of the present application. For example, the access process described in FIG. 8A is performed when the storage device receives a read command, a write command, or an erase command sent by the host.

In step 801, the control unit receives an I/O command sent by the host, and obtains a merge block to be accessed by the I/O command.

In step 802, the control unit obtains one or more physical blocks that constitute a merge block.

In step 803, the control component accesses one or more physical blocks of the merge block in response to the I/O command.

In one possible implementation manner, the merging blocks include a primary merging good merging block and a secondary merging good merging block, wherein the primary merging good merging block refers to a merging block obtained by primary merging of at least two good physical blocks, and the primary merging good merging block is a good physical block for all physical blocks; the good merging block of the secondary merging refers to a merging block obtained by merging the first merging block and the good physical block in the second merging block corresponding to the first merging block, all physical blocks of the good merging block of the secondary merging are good physical blocks, the first merging block and the second merging block are merging blocks which are merged at one time, the first merging block at least comprises a bad physical block, the second merging block at least comprises a good physical block, and the good physical block in the second merging block can replace the bad physical block in the first merging block for data storage.

In yet another possible implementation, obtaining one or more physical blocks that make up a consolidated block includes: judging whether the merging block is a good merging block of primary merging or a good merging block of secondary merging; if the merge block is a one-time-merge good merge block, one or more physical blocks in the one-time-merge good merge block are determined according to the number or index of the one-time-merge good merge block.

Specifically, after receiving the I/O command sent by the host, the control unit determines, according to the index (e.g., the block number of the merge block) indicated by the I/O command, whether the merge block to be accessed by the I/O command is a good merge block for one time or a bad merge block for one time, according to the index and the first information table. If the merging block to be accessed by the I/O command is a good merging block of one-time merging, the address of the physical block to be accessed is directly calculated according to the block number of the merging block, for example, the block number of the good merging block of one-time merging is X, and the physical addresses of the corresponding good physical blocks are 2X and 2x+1.

Further, if the merging block to be accessed by the I/O command is a bad merging block which is merged once, determining an index corresponding to the bad merging block which is merged once, inquiring whether an entry corresponding to the index exists in a second information table, and if so, determining that the merging block which is actually accessed by the I/O command is a good merging block which is merged twice.

In yet another possible implementation manner, if the merge block is a twice-merged good merge block, the third information table is queried to obtain good physical blocks corresponding to the twice-merged good merge block, where each entry in the third information table includes source information of each physical block in the twice-merged good merge block.

Specifically, the corresponding entry is queried in a third information table according to the index corresponding to the good merging block of the secondary merging, and the corresponding physical block is determined according to the source information of the physical block contained in the entry.

In yet another possible implementation, if the I/O command is a read command or a write command, a physical block of the merge block is accessed in response to the I/O command.

FIG. 8B is a schematic diagram of responding to a read command according to an embodiment of the present application.

In a memory device, FTL (Flash Translation Layer ) is utilized to maintain mapping information from logical block addresses (LogicalBlockAddress, LBA) (where "logical blocks" are used to distinguish from "logical block spaces" as used herein) to consolidated block physical addresses. As shown in fig. 8B, the control unit receives an I/O command sent by the host, where the I/O command is a read command, the read command carries a logical block address LBA1, and determines, according to the FTL table, a merge block 5 corresponding to the LBA1, where the merge block 5 is a good merge block that is merged at one time, and the control unit directly calculates a physical block address corresponding to the merge block 5 according to a block number of the merge block 5, reads data from the physical block according to the physical block address, and transmits the data to the host.

FIG. 8C shows a schematic diagram of responding to a write command provided by an embodiment of the application.

As shown in FIG. 8C, the control unit receives an I/O command sent by the host, the I/O command is a write command, and the write command carries a logical block address LBA3. The write command is allocated the logical block space provided by the merge block 1. And then determining that the merging block 1 is a good merging block of secondary merging by inquiring the second information table, inquiring by the control component according to the block number of the merging block 1 and the third information table to obtain the source of each physical block in the merging block 1, determining that the corresponding physical block is a physical block 2 and a physical block 202 respectively according to the source of each physical block, and writing the data corresponding to the write command into the physical block 2 and/or the physical block 202. And recording LBA3 and the address for merge block 1 (e.g., the block number of merge block 1) in the FTL table.

FIG. 8D shows a schematic diagram of yet another response read command provided by an embodiment of the present application.

As shown in fig. 8D, the control unit receives an I/O command sent by the host, where the I/O command is a read command, the read command carries a logical block address LBA100, determines, according to the FTL table, a merge block 3 corresponding to the LBA100, then determines, by querying a second information table, that the merge block 3 is a good merge block for secondary merge, and the control unit queries, according to the block number of the merge block 3 and a third information table, the source of each physical block in the merge block 3, determines, according to the source of each physical block, that the physical block corresponding to the physical block is a physical block 106 and a physical block 107, respectively, reads data according to the physical addresses of the physical blocks 106 and/or the physical blocks 107, and sends the data to the host.

In yet another possible implementation, if the I/O command is an erase command, all physical blocks of the merge block are erased in response to the I/O command.

FIG. 8E shows a schematic diagram of responding to an erase command provided by an embodiment of the present application.

As shown in fig. 8E, the control unit receives an I/O command sent by the host, where the I/O command is an erase command, the erase command carries a logical block address LBA100, determines, according to the FTL table, a merge block 3 corresponding to the LBA100, then determines, by querying a second information table, that the merge block 3 is a good merge block for secondary merge, and the control unit queries, according to the block number of the merge block 3 and a third information table, the source of each physical block in the merge block 3, determines, according to the source of each physical block, that the physical block corresponding to the physical block is a physical block 106 and a physical block 107, and erases data in the physical block 106 and the physical block 107 according to the physical addresses of the physical block 106 and the physical block 107.

In the embodiments illustrated in fig. 8A-8E, the FTL table records addresses (e.g., merge block numbers) for the merge blocks corresponding to Logical Block Addresses (LBAs). When processing a read command, in the case that the merge block corresponding to the address for the merge block recorded in the FTL table is a twice-merged good merge block, it is also necessary to further acquire a physical block constituting the twice-merged good merge block according to the merge block number, and access one or more of the acquired physical blocks to respond to the read command. According to yet another embodiment of the present application, referring to fig. 9A and 9B, the physical address including the physical block number (or physical block address) is recorded in the FTL table, so that it is not necessary to judge whether the merge block is good or bad when processing the read command, thereby further reducing the processing delay.

In yet another possible implementation manner, the method further includes: receiving a write command sent by a host, selecting a merging block from unassigned merging blocks, and assigning a storage space corresponding to the merging block to the write command; and writing data into the storage space according to the write command.

In yet another possible implementation manner, allocating the storage space corresponding to the merge block to the write command includes: identifying whether the merge block is a good merge block for secondary merge; if yes, obtaining source information of each physical block in the merging block by inquiring a third information table, and distributing storage spaces corresponding to part or all of the physical blocks in the merging block to the write command according to the source information.

FIG. 9A shows a schematic diagram of responding to a write command provided by yet another embodiment of the present application.

In the example of fig. 9A, FTL table records correspondence between logical addresses and physical addresses, the physical addresses include physical block addresses instead of merge block numbers. The logical block is still a logical block space, where merge block 1 and merge block 3 are twice-merged good merge blocks, while the other merge blocks are once-merged good merge blocks. When processing a write command, a memory space to which data is not written is allocated for the write command from the logical block space. While the physical address of the allocated memory space (non-consolidated block number) is recorded in the FTL table.

As shown in fig. 9A, the control unit receives a write command sent by the host, where the write command carries a logical block address LBA3. The write command is allocated the memory space provided by the merge block 1. Further, it is also identified that merge block 1 is a good merge block for a secondary merge, such that further querying the third information table results in the source of each physical block (e.g., physical block 2 and physical block 202) in merge block 1, and also determines that it is provided by physical block 2 and/or physical block 202 based on the allocated storage space. By way of example, the allocated physical space is provided by physical block 202. The data corresponding to the write command is written to the physical block 202. And record LBA3 with the physical address comprising physical block 202 in the FTL table.

In yet another possible implementation manner, the method further includes: receiving a read command sent by a host, and inquiring a physical address of a physical block corresponding to a logical block address pair carried by the read command according to an FTL table; and reading data from the physical block corresponding to the physical address according to the read command, and sending the data to the host.

FIG. 9B shows a schematic diagram of responding to a read command provided by another embodiment of the present application.

In the example of fig. 9B, merge block 1 and merge block 3 of the logical block space are good merge blocks of the secondary merge. Merge block 1 is made up of physical blocks 2 and 202, while merge block 3 is made up of physical blocks 106 and 107. The physical blocks constituting the merge block are derived from the first, second and/or third tables of information. The FTL table records the correspondence between the logical address and the physical address, where the physical address includes a physical block address instead of a merge block number.

As shown in fig. 9B, the control unit receives a read command sent by the host, where the read command carries a logical block address LBA3, determines a physical address of the physical block 202 corresponding to the LBA3 according to the FTL table, directly accesses the physical block 202 according to the physical address to obtain data to be read by the read command, and sends the data to the host.

Fig. 10 shows a schematic structural diagram of a control unit according to an embodiment of the present application. The control unit includes a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. Wherein the media interface controller is coupled to the NVM chip, the control section receives, via the host interface, NVMe commands sent by the host for indicating fast diagnostic test (Rapid diagnostic test, RDT) testing and bad block management for physical blocks in the storage device. The host command processing unit (processor) parses the NVMe command and generates a command suitable for the storage command processing unit. In response to receiving the command, the storage command processing unit performs an operation of the media interface controller to access the NVM chip or performs an operation of the storage media management unit to maintain the first information table or the second information table. In this embodiment, the storage medium management unit maintains a third information table in addition to the first information table or the second information table. The application may also be implemented by a media interface controller such that the media management unit operates on logical block space.

In the scheme provided by the embodiment of the application, the control part records the information of the merging block which is obtained by merging at least two physical blocks at one time in each entry of the first information table, namely the control part can record the information of a plurality of physical blocks through each entry of the first information table, so that the control part can consume less memory resources as much as possible to store the physical block information. In addition, the control part records the association relation between the first physical address of the bad physical block in the first merging block and the second physical address of the good physical block in the corresponding second merging block besides the information of the merging blocks which are merged once, merges the good physical block in the first merging block with the good physical block in the second merging block according to the association relation to obtain a good physical block which is merged twice, and constructs a logic block space which does not contain the bad physical block and has continuous addresses under the condition that the natural bad physical block exists in the NVM chip so as to be convenient for upper layer use and further improve the performance of the storage device.

It should be noted that, for the sake of simplicity, the present application represents some methods and embodiments thereof as a series of acts and combinations thereof, but it will be understood by those skilled in the art that the aspects of the present application are not limited by the order of acts described. Thus, those skilled in the art will appreciate, in light of the present disclosure or teachings, that certain steps thereof may be performed in other sequences or concurrently. Further, those skilled in the art will appreciate that the embodiments described herein may be considered as alternative embodiments, i.e., wherein the acts or modules involved are not necessarily required for the implementation of some or all aspects of the present application. In addition, the description of some embodiments of the present application is also focused on according to the different schemes. In view of this, those skilled in the art will appreciate that portions of one embodiment of the application that are not described in detail may be referred to in connection with other embodiments.

In particular implementations, based on the disclosure and teachings of the present application, those skilled in the art will appreciate that several embodiments of the present disclosure may be implemented in other ways not disclosed herein. For example, in terms of the foregoing embodiments of the electronic device or apparatus, the units are split in consideration of the logic function, and there may be another splitting manner when actually implemented. For another example, multiple units or components may be combined or integrated into another system, or some features or functions in the units or components may be selectively disabled. In terms of the connection relationship between different units or components, the connections discussed above in connection with the figures may be direct or indirect couplings between the units or components. In some scenarios, the foregoing direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustical, magnetic, or other forms of signal transmission.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method of NVM bad block management, comprising:

scanning physical blocks in each logical unit LUN to generate a first information table, wherein the first information table comprises a plurality of entries, each entry comprises information of a merging block which is merged at one time, and each merging block comprises at least two physical blocks;

determining a first type of merging block and a second type of merging block according to a first information table, determining at least one first merging block from the first type of merging blocks and determining a second merging block corresponding to each first merging block from the second type of merging blocks, wherein the first type of merging block and the second type of merging block are different merging blocks, the first merging block comprises a bad physical block, the second merging block comprises a good physical block, and the good physical block in the second merging block can replace the bad physical block in the first merging block for data storage;

and determining a first physical address of a bad physical block in each first merging block and a second physical address of a good physical block in a corresponding second merging block, and recording the association relation between the first physical address and the second physical address.

2. The method of claim 1, further comprising:

combining the good physical blocks in the first combined block and the second combined block corresponding to the first combined block to obtain a good combined block for secondary combination; the number of physical blocks of the good merging blocks of the secondary merging is the same as that of the physical blocks of the merging blocks, and all the physical blocks of the good merging blocks of the secondary merging are good physical blocks.

3. A method according to claim 1 or 2, characterized in that determining the first type of merge block and the second type of merge block from the first information table comprises:

and determining the number of bad merging blocks in each big block of the storage device according to the first information table, and determining the first merging blocks and the second merging blocks according to the number.

4. A method according to claim 3, wherein determining the first type of merge block and the second type of merge block based on the number comprises:

taking all the merging blocks in a specified number of first large blocks with the largest bad merging blocks or all the merging blocks comprising at least one good physical block as second-class merging blocks, and acquiring the first-class merging blocks from the merging blocks of other large blocks except the first large blocks in the storage device; or (b)

And taking all the merging blocks in the second large blocks with the quantity larger than the preset threshold value or all the merging blocks comprising at least one good physical block as second merging blocks, and acquiring the first merging blocks from the merging blocks of other large blocks except the second large blocks in the storage device.

5. A method according to claim 1 or 2, characterized in that determining at least one first merging block from the first type of merging blocks and determining a second merging block corresponding to each first merging block from the second type of merging blocks comprises:

For the merging block A of the first merging block, if one or more merging blocks B of the second merging block which is not allocated and is in the same logic unit with the merging block A exist, allocating the merging block B closest to the physical address of the merging block A to the merging block A, and taking the merging block A and the allocated merging block B as corresponding first merging blocks and second merging blocks.

6. A method according to claim 1 or 2, characterized in that determining at least one first merging block from the first type of merging blocks and determining a second merging block corresponding to each first merging block from the second type of merging blocks comprises:

determining a plurality of third merging blocks and the first quantity thereof from first merging blocks in the same logic unit LUN and a plurality of fourth merging blocks and the second quantity thereof from second merging blocks according to a first information table respectively, wherein the third merging blocks comprise good physical blocks and bad physical blocks, and the fourth merging blocks comprise good physical blocks or good physical blocks and bad physical blocks;

the first and second merge blocks are determined based on the first and second numbers.

7. The method of claim 6, wherein determining the first merge block and the second merge block based on the first number and the second number comprises:

If the first number is not greater than the second number, taking each third merging block as a first merging block, and taking a fourth merging block closest to each first merging block as a corresponding second merging block; or (b)

If the first number is larger than the second number, each fourth merging block is used as a second merging block, and the first merging block closest to each second merging block is used as the corresponding first merging block.

8. The method according to claim 1 or 2, further comprising:

adding at least one entry in the first information table to obtain a second information table, wherein the entry contains information of a secondary combined block obtained by replacing a bad physical block in a first combined block by a good physical block in a second combined block corresponding to the bad physical block, the secondary combined block at least comprises the secondary combined good combined block, and the index of the entry is the same as that of the first combined block in the corresponding first information table; or (b)

And generating a second information table, wherein each entry in the second information table contains information of the merging blocks which are merged twice, and the index of each entry in the second information table is the same as the index of the first merging block in the corresponding first information table.

9. The method of claim 8, further comprising:

And generating a third information table according to the second information table and the association relation, wherein each entry in the third information table contains source information of each physical block in the good merging blocks which are merged twice.

10. A control unit comprising a processor and a memory, the memory storing program code which, when executed by the processor, performs the method of any of claims 1-9.