CN113472449A - Optical module and signal polarity definition method - Google Patents

Abstract

In the optical module and the signal polarity defining method provided by the application, the optical module comprises a circuit board and an MCU (microprogrammed control unit), the MCU comprises a register and a signal processing unit, the signal processing unit is used for receiving a level instruction signal from an upper computer and configuring a transmission rate according to the level instruction signal, when data in the register is a first preset value, if the level instruction signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level instruction signal is in a low level state, the transmission rate is configured to be a low transmission rate; when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate. The application adds definition description of the polarity of a rate selection signal on the basis of the existing SFF-8472 protocol by enabling the register in the user-writable area in the SFF-8472 protocol.

Description

Optical module and signal polarity definition method

Technical Field

The present application relates to the field of optical communications technologies, and in particular, to an optical module and a signal polarity defining method.

Background

In order to realize the smooth transition from XGPON to XGSPON for PON-like products, the receiving end of XGSPON OLT should support both 2.5G rate and 10G rate. The system single board provides a path of rate selection signal Ratesel through an electrical interface of the optical module to indicate whether the uplink burst packet comes from an XGPON ONU (2.5G rate) or an XGSON ONU (10G rate) at the moment. Currently, the polarity of the rate select signal Ratesel is different for different customers according to different designs of single boards. The SFF-8472 protocol does not specify the polarity of the rate select signal Ratesel, resulting in no uniform level high/low and output rate high/low correspondence.

Disclosure of Invention

The application provides an optical module and a signal polarity defining method, which are used for adding definition description of rate selection signal polarity on the basis of the existing SFF-8472 protocol.

In one aspect, the present application provides an optical module, comprising:

the circuit board is provided with a golden finger at one end;

MCU, set up on the circuit board, including the I2C interface, through I2C interface connection the golden finger so that MCU and host computer I2C communication still include:

a register for storing data;

the signal processing unit is used for receiving a level instruction signal from an upper computer and configuring a transmission rate according to the level instruction signal, and comprises:

when the data in the register is a first preset value, if the level command signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a low transmission rate;

and when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

In another aspect, the present application provides a signal polarity defining method, including:

receiving a level instruction signal provided by an upper computer, and configuring a transmission rate according to the level instruction signal;

when the data in the register is a first preset value, if the level command signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a low transmission rate;

and when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

Has the advantages that:

in the optical module and the signal polarity definition method provided by the application, the optical module comprises a circuit board and an MCU (microprogrammed control unit), the MCU comprises a register and a signal processing unit, the signal processing unit is used for receiving a level instruction signal from an upper computer and configuring a transmission rate according to the level instruction signal, when data in the register is a first preset value, if the level instruction signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level instruction signal is in a low level state, the transmission rate is configured to be a low transmission rate; and when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

The polarity of a rate selection signal Ratesel of an optical module is indicated by starting a register in a user writable area in an SFF-8472 protocol, and an upper computer MAC reads the value of the corresponding register through I2C to confirm the setting of the optical module and correspondingly carry out correct configuration; and further, the definition description of the polarity of the rate selection signal is added on the basis of the existing SFF-8472 protocol.

Drawings

In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without any creative effort.

Fig. 1 is a schematic diagram of a connection relationship of an optical communication terminal;

fig. 2 is a schematic structural diagram of an optical network terminal;

fig. 3 is a schematic structural diagram of an optical module according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of an exploded structure of an optical module according to an embodiment of the present application;

fig. 5 is a schematic diagram of an internal structure of an optical module according to an embodiment of the present disclosure;

fig. 6 is a schematic view of an interaction relationship between an optical module and an upper computer according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

One of the core links of optical fiber communication is the interconversion of optical and electrical signals. The optical fiber communication uses optical signals carrying information to transmit in information transmission equipment such as optical fibers/optical waveguides, and the information transmission with low cost and low loss can be realized by using the passive transmission characteristic of light in the optical fibers/optical waveguides; meanwhile, the information processing device such as a computer uses an electric signal, and in order to establish information connection between the information transmission device such as an optical fiber or an optical waveguide and the information processing device such as a computer, it is necessary to perform interconversion between the electric signal and the optical signal.

The optical module realizes the function of interconversion of optical signals and electrical signals in the technical field of optical fiber communication, and the interconversion of the optical signals and the electrical signals is the core function of the optical module. The optical module is electrically connected with an external upper computer through a golden finger on an internal circuit board of the optical module, and the main electrical connection comprises power supply, I2C signals, data signals, grounding and the like; the electrical connection mode realized by the gold finger has become the mainstream connection mode of the optical module industry, and on the basis of the mainstream connection mode, the definition of the pin on the gold finger forms various industry protocols/specifications.

Fig. 1 is a schematic diagram of connection relationship of an optical communication terminal. As shown in fig. 1, the connection of the optical communication terminal mainly includes the interconnection among the optical network terminal 100, the optical module 200, the optical fiber 101 and the network cable 103;

one end of the optical fiber 101 is connected with a far-end server, one end of the network cable 103 is connected with local information processing equipment, and the connection between the local information processing equipment and the far-end server is completed by the connection between the optical fiber 101 and the network cable 103; and the connection between the optical fiber 101 and the network cable 103 is made by the optical network terminal 100 having the optical module 200.

An optical port of the optical module 200 is externally accessed to the optical fiber 101, and establishes bidirectional optical signal connection with the optical fiber 101; an electrical port of the optical module 200 is externally connected to the optical network terminal 100, and establishes bidirectional electrical signal connection with the optical network terminal 100; the optical module realizes the interconversion of optical signals and electric signals, thereby realizing the establishment of information connection between the optical fiber and the optical network terminal; specifically, the optical signal from the optical fiber is converted into an electrical signal by the optical module and then input to the optical network terminal 100, and the electrical signal from the optical network terminal 100 is converted into an optical signal by the optical module and input to the optical fiber.

The optical network terminal is provided with an optical module interface 102, which is used for accessing an optical module 200 and establishing bidirectional electric signal connection with the optical module 200; the optical network terminal is provided with a network cable interface 104, which is used for accessing the network cable 103 and establishing bidirectional electric signal connection with the network cable 103; the optical module 200 is connected to the network cable 103 through the optical network terminal 100, specifically, the optical network terminal transmits a signal from the optical module to the network cable and transmits the signal from the network cable to the optical module, and the optical network terminal serves as an upper computer of the optical module to monitor the operation of the optical module.

At this point, a bidirectional signal transmission channel is established between the remote server and the local information processing device through the optical fiber, the optical module, the optical network terminal and the network cable.

Common information processing apparatuses include routers, switches, electronic computers, and the like; the optical network terminal is an upper computer of the optical module, provides data signals for the optical module, and receives the data signals from the optical module, and the common upper computer of the optical module also comprises an optical line terminal and the like.

Fig. 2 is a schematic diagram of an optical network terminal structure. As shown in fig. 2, the optical network terminal 100 has a circuit board 105, and a cage 106 is disposed on a surface of the circuit board 105; an electric connector is arranged in the cage 106 and used for connecting an electric port of an optical module such as a golden finger; the cage 106 is provided with a heat sink 107, and the heat sink 107 has a projection such as a fin that increases a heat radiation area.

The optical module 200 is inserted into the optical network terminal, specifically: the electrical port of the optical module is inserted into an electrical connector inside the cage 106, and the optical port of the optical module is connected to the optical fiber 101.

The cage 106 is positioned on the circuit board, and the electrical connector on the circuit board is wrapped in the cage, so that the electrical connector is arranged in the cage; the optical module is inserted into the cage, held by the cage, and the heat generated by the optical module is conducted to the cage 106 and then diffused by the heat sink 107 on the cage.

Fig. 3 is a schematic structural diagram of an optical module 200 according to an embodiment of the present disclosure, and fig. 4 is an exploded structural diagram of the optical module 200 according to the embodiment of the present disclosure. As shown in fig. 3 and 4, an optical module 200 provided in an embodiment of the present application includes an upper housing 201, a lower housing 202, a circuit board 300, an unlocking handle 203, a light emission sub-module 206, and a light reception sub-module 207.

The upper shell 201 is covered on the lower shell 202 to form a wrapping cavity with two openings; the outer contour of the wrapping cavity is generally a square body, and specifically, the lower shell comprises a main plate and two side plates which are positioned at two sides of the main plate and are perpendicular to the main plate; the upper shell comprises a cover plate, and the cover plate covers two side plates of the upper shell to form a wrapping cavity; the upper shell can also comprise two side walls which are positioned at two sides of the cover plate and are perpendicular to the cover plate, and the two side walls are combined with the two side plates to realize that the upper shell covers the lower shell.

The two openings can be two ends (204, 205) in the same direction, or two openings in different directions; one opening is an electric port 204, and a gold finger of the circuit board extends out of the electric port 204 and is inserted into an upper computer such as an optical network unit; the other opening is an optical port 205 for external optical fiber access to connect the tosa 206 and the rosa 207 inside the optical module; optoelectronic devices such as the circuit board 300, the tosa 206, and the rosa 207 are located in the package cavity.

The assembly mode of combining the upper shell and the lower shell is adopted, so that the circuit board 300, the transmitter sub-module 206, the receiver sub-module 207 and other devices can be conveniently installed in the shells, and the outermost packaging protection shell of the optical module is formed by the upper shell and the lower shell; the upper shell and the lower shell are made of metal materials generally, so that electromagnetic shielding and heat dissipation are facilitated; generally, the shell of the optical module cannot be made into an integrated structure, so that when devices such as a circuit board and the like are assembled, the positioning component, the heat dissipation structure and the electromagnetic shielding structure cannot be installed, and the production automation is not facilitated.

The unlocking handle 203 is located on the outer wall of the wrapping cavity/lower shell 202 and used for realizing the fixed connection between the optical module and the upper computer or releasing the fixed connection between the optical module and the upper computer.

The unlocking handle 203 is provided with a clamping structure matched with the upper computer cage; the tail end of the unlocking handle is pulled to enable the unlocking handle to move relatively on the surface of the outer wall; the optical module is inserted into a cage of the upper computer, and the optical module is fixed in the cage of the upper computer through a clamping structure of the unlocking handle; by pulling the unlocking handle, the clamping structure of the unlocking handle moves along with the unlocking handle, so that the connection relation between the clamping structure and the upper computer is changed, the clamping relation between the optical module and the upper computer is relieved, and the optical module can be drawn out from the cage of the upper computer.

The tosa 206 and the rosa 207 are respectively configured to transmit an optical signal and receive an optical signal. The tosa 206 and the rosa 207 may also be combined together to form an integrated optical transceiver. The tosa 206 includes a light emitting chip and a backlight detector, and the rosa 207 includes a light receiving chip.

The circuit board 300 is located in a package cavity formed by the upper shell 201 and the lower shell 202, and circuit traces, electronic elements (such as capacitors, resistors, triodes and MOS transistors) and chips (such as a microprocessor MCU, a laser driving chip, a limiting amplifier, a clock data recovery CDR, a power management chip and a data processing chip DSP) are disposed on the circuit board 300.

In the embodiment of the application, the transimpedance amplifier is closely associated with the light receiving chip. The transimpedance amplifier chip can be independently packaged on the circuit board 300, and the light receiving chip and the transimpedance amplifier are electrically connected with the circuit board 300 through the independent package; the transimpedance amplifier and the light receiving chip can be packaged together in an independent package body, such as the same coaxial tube shell TO or the same square cavity; the light receiving chip and the transimpedance amplifier can be arranged on the surface of the circuit board without adopting an independent packaging body; the light receiving chip can be independently packaged, the trans-impedance amplifier is arranged on the circuit board, and the quality of a received signal can meet certain relatively low requirements.

The chip on the circuit board can be an all-in-one chip, for example, a laser driving chip and an MCU chip are fused into a chip, and a laser driving chip, a limiting amplification chip and an MCU chip are also fused into a chip, wherein the chip is the integration of the circuit, but the functions of all the circuits do not disappear due to the integration, and only the integration of the circuit forms occurs. Therefore, when the circuit board is provided with three independent chips, namely the MCU, the laser driving chip and the amplitude limiting amplification chip, the scheme is equivalent to that of arranging a single chip with three functions in one on the circuit.

The circuit board 300 connects the electrical devices in the optical module together according to the circuit design through circuit wiring to realize the electrical functions of power supply, electrical signal transmission, grounding and the like. The circuit board 300 is a carrier of main electrical components of the optical module, and the electrical components not arranged on the circuit board are finally electrically connected with the circuit board, and the electrical connector on the circuit board 300 realizes the electrical connection between the optical module and the host computer thereof.

The circuit board 300 is generally a rigid circuit board, which can also perform a bearing function due to its relatively rigid material, for example, the rigid circuit board can stably bear a chip; when the tosa 206 and the rosa 207 are located on the circuit board, the rigid circuit board can also provide a smooth load; the hard circuit board can also be inserted into an electric connector in the upper computer cage, and specifically, a metal pin/golden finger is formed on the surface of the tail end of one side of the hard circuit board and is used for being connected with the electric connector; these are not easily implemented with flexible circuit boards.

The circuit board 300 has a gold finger 301 on the surface of the end, the gold finger is composed of a pin independent from each other, the circuit board 300 is inserted into the electric connector in the cage, and the gold finger is electrically connected with the upper computer. The upper computer and the optical module can adopt an I2C protocol to carry out information transmission through I2C pins. The upper computer can write information into the optical module, and particularly, the upper computer can write the information into a register of the optical module; the optical module cannot write information into the upper computer, when the optical module needs to provide the information to the upper computer, the optical module can write the information into a preset register in the optical module, the register is read by the upper computer, and the register of the optical module is generally integrated in an MCU of the optical module and can also be independently arranged on a circuit board 300 of the optical module.

A flexible circuit board is also used in a part of the optical module to supplement a rigid circuit board; the flexible circuit board is generally used in combination with a rigid circuit board, for example, the rigid circuit board may be connected to the optical transceiver device through the flexible circuit board.

The tosa 206 and the rosa 207 are respectively configured to transmit an optical signal and receive an optical signal. In this embodiment, the tosa 206 may be a coaxial TO package physically separated from the pcb and electrically connected TO the pcb by a flexible board; the rosa 207 is also in a coaxial TO package, physically separated from the circuit board, and electrically connected by a flexible board. In another common implementation, may be disposed on a surface of the circuit board 300; in addition, the tosa 206 and the rosa 207 may be combined together to form an integrated optical transceiver.

Fig. 5 is a schematic partial structure diagram of an optical module according to an embodiment of the present invention. As shown in fig. 5, in the optical module provided in this embodiment of the application, a row of gold fingers 301 is disposed on a surface of one end of a circuit board 300, an MCU302 is disposed on the circuit board 300, the row of gold fingers 301 is composed of one gold finger which is independent from each other, the circuit board 300 is inserted into an electrical connector in a cage, the gold fingers 301 are electrically connected to an upper computer, and the MCU302 is electrically connected to the gold fingers 301. The rosa 207 includes an APD, a transimpedance amplifier chip (TIA), a limiting amplifier chip (LA), and an MCU 302. The chip is essentially the integration of circuits, the circuits can be integrated into the chip, and part of functions in the chip can also be realized by the circuits on the circuit board. The functions of the chip can be realized by the chip, the circuit or the main chip combined with the peripheral circuit. Different functions can be integrated by the same chip, and the change of the circuit integration form still belongs to the protection scope of the invention.

In the process of receiving the optical signal, the optical receive sub-module 207 is internally provided with an optical receive chip, where a common optical receive chip may be an APD, and is configured to receive the optical signal sent by the external device and convert the optical signal sent by the external device into an electrical signal; an input pin of the transimpedance amplifier chip is connected with an output pin of the optical receive submodule 207, and is used for converting an electrical signal output by the optical receive submodule 207 into a voltage signal; the high-frequency signal input pin of the amplitude limiting amplification chip is connected with the output pin of the transimpedance amplification chip and is used for amplifying a first voltage signal output by the transimpedance amplification chip; an input pin of the clock data recovery chip is connected with a high-frequency signal output pin of the amplitude limiting amplification chip and used for shaping a voltage signal output by the amplitude limiting amplification chip, and an output pin of the clock data recovery chip is connected with the golden finger 301. The connecting finger 301 is connected with an upper computer, and then signals received by the optical module can be sent to the upper computer.

The SFF-8472 protocol does not specify the polarity of the rate selection signal Ratesel, so that there is no uniform correspondence between the level of the output rate and the level of the output rate, and for this reason, the application provides a relevant scheme about the definition of the polarity of the rate selection signal, so as to add a definition description of the polarity of the rate selection signal on the basis of the existing SFF-8472 protocol.

In the method, a register in a user writable area is started, a first preset value or a second preset value is stored in the register, when the upper computer monitors that the first preset value is stored in the register, a high level or a low level is configured for a rate selection signal, a level instruction signal is generated and sent to a signal processing unit in an optical module, the signal processing unit judges the level state of the level instruction signal, judges whether the level state is the high level state or the low level state, and then configures corresponding transmission rate according to the judgment result of the level state; and when the upper computer monitors that a second preset value is stored in the register, corresponding processing is performed similarly.

Specifically, when the data stored in the register is a first preset value, the signal processing unit receives a level instruction signal provided by the upper computer, when the level instruction signal is in a high level state, the signal processing unit configures the transmission rate to be a high transmission rate, and when the level instruction signal is in a low level state, the signal processing unit configures the transmission rate to be a low transmission rate; when the register is in a second preset value, the signal processing unit receives a level instruction signal provided by the upper computer, when the level instruction signal is in a high level state, the signal processing unit configures the transmission rate to be a low transmission rate, and when the level instruction signal is in a low level state, the signal processing unit configures the transmission rate to be a high transmission rate.

It is understood that the level command signal in the present application is generated after configuring the level state for the rate selection signal, and is not a specific digital data signal, but a level state signal maintained by the rate selection signal for a long time.

The related scheme provided by the present application with respect to the definition of the polarity of the rate selection signal is described below with reference to fig. 6.

The optical module provided by the application comprises the MCU, the MCU comprises a register, and as the application is an extension of the existing SFF-8472 protocol, the register within the range of the SFF-8472 protocol can not be used in the application, but the register outside the range of the SFF-8472 protocol is adopted, such as the register in a user-writable area, and it can be understood that when the extension content of the existing SFF-8472 protocol provided by the application is absorbed by the protocol, the register in the application can be brought into the range of the SFF-8472 protocol.

For describing the scheme, the register in this application is exemplified by the a0[64] bit6 register, and it should be understood that the application is not limited to a specific register, and registers in other user-writable areas are within the scope of the embodiments of the application.

In the embodiment of the present application, the first preset value or the second preset value is stored in the register a0[64] bit6, where the first preset value is "1" as an example, and the second preset value is "0" as an example. It should be understood that, in the embodiment of the present application, the first preset value is taken as "1" as an example, the second preset value is taken as "0" as an example only for convenience of description, and the first preset value and the second preset value are other numbers and also belong to the protection scope of the present application, and the present application does not limit the corresponding specific values of the first preset value and the second preset value.

When a first preset value "1" is written into an a0[64] bit6 register, an upper computer monitors that data stored in an a0[64] bit6 is 1, then the upper computer configures corresponding level for a rate selection signal to obtain a level instruction signal, the upper computer provides the level instruction signal in a high level state or the level instruction signal in a low level state, and then the level instruction signal is sent to a signal processing unit inside an optical module through a golden finger. When the level instruction signal is in a high level state, the signal processing unit configures the transmission rate to be a high transmission rate, and when the level instruction signal is in a low level state, the signal processing unit configures the transmission rate to be a low transmission rate.

When a second preset value "0" is written into the register a0[64] bit6, the upper computer monitors that data stored in the register a0[64] bit6 is 0, then the upper computer configures corresponding level for the rate selection signal to obtain a level instruction signal, the upper computer provides the level instruction signal in a high level state or the level instruction signal in a low level state, and then the level instruction signal is sent to the signal processing unit inside the optical module through a golden finger. When the level instruction signal is in a high level state, the signal processing unit configures the transmission rate to be a low transmission rate, and when the level instruction signal is in a low level state, the signal processing unit configures the transmission rate to be a high transmission rate.

The above description is related to the execution content of the optical module after receiving the level command signal, and the following description is directed to the execution content of the upper computer side.

The upper computer reads data stored in the register, and then when the upper computer allocates a high transmission rate in a first time period in the embodiment of the application, the upper computer further combines whether the data stored in the register of a0[64] bit6 is 1 or 0, if the data stored in the register of a A0[64] bit6 is 1, the upper computer allocates a high level for the rate selection signal to generate a level instruction signal in a high level state, the level instruction signal in the high level state is sent to the signal processing unit, the signal processing unit allocates the transmission rate to the high transmission rate, if the data stored in the register of the A0[64] bit6 is 0, the upper computer allocates a low level for the rate selection signal to generate a level instruction signal in a low level state, the level instruction signal in the low level state is sent to the signal processing unit, and the signal processing unit allocates the transmission rate to the high transmission rate.

In this embodiment of the application, when the upper computer allocates a low transmission rate in the second time period, the upper computer further combines whether the data stored in the register of a0[64] bit6 is 1 or 0, if the data is 1, the upper computer configures a low level for the rate selection signal to generate a level instruction signal in a low level state, and sends the level instruction signal in the low level state to the signal processing unit, and the signal processing unit configures the transmission rate to be the low transmission rate, and if the data is 0, the upper computer configures a high level for the rate selection signal to generate a level instruction signal in a high level state, and sends the level instruction signal in the high level state to the signal processing unit, and the signal processing unit configures the transmission rate to be the low transmission rate.

Specifically, a single board of the upper computer is provided with an MAC chip, and the upper computer is used as an execution main body through the MAC chip.

When a first preset value 1 is written into an a0[64] bit6 register, an MAC chip of an upper computer monitors that data stored in an a0[64] bit6 is 1, then the MAC chip of the upper computer generates a level instruction signal after configuring a high level or a low level for a rate selection signal, and then sends the level instruction signal to a signal processing unit inside an optical module through a golden finger.

When the second preset value 0 is written into the register of a0[64] bit6, the MAC chip of the upper computer monitors that data stored in the register of a0[64] bit6 is 0, then the MAC chip of the upper computer configures corresponding level for the rate selection signal to obtain a level instruction signal, and then the level instruction signal is sent to the signal processing unit inside the optical module through a golden finger.

The specific implementation means that the upper computer configures specific level for the rate selection signal, the signal processing unit judges the level and configures the transmission rate according to the level is a common means, and description is not repeated.

According to the above, in the present application, a signal processing unit receives a level instruction signal from an upper computer, and configures a transmission rate according to the level instruction signal, when data in a register is a first preset value, if the level instruction signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level instruction signal is in a low level state, the transmission rate is configured to be a low transmission rate; and when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

The polarity of a rate selection signal Ratesel of an optical module is indicated by starting a register in a user writable area in an SFF-8472 protocol, and an upper computer MAC reads the value of the corresponding register through I2C to confirm the setting of the optical module and correspondingly carry out correct configuration; and further, the definition description of the polarity of the rate selection signal is added on the basis of the existing SFF-8472 protocol.

In a second aspect, based on the foregoing optical module, the present application provides a signal polarity defining method, including:

receiving a first rate selection signal generated by an upper computer according to a register value, and judging whether the level of the first rate selection signal is a high level or a low level;

the transmission rate is configured to be a high transmission rate when the level of the first rate selection signal is a high level, and configured to be a low transmission rate when the level of the first rate selection signal is a low level.

Receiving a second rate selection signal generated by an upper computer according to a register value, and judging whether the level of the second rate selection signal is a high level or a low level;

the transmission rate is configured to be a low transmission rate when the level of the second rate selection signal is a high level, and configured to be a high transmission rate when the level of the second rate selection signal is a low level.

Wherein the register is A0[64] bit 6.

Specifically, when the upper computer monitors that a0[64] bit6 is 1, the upper computer generates a first rate selection signal for a rate selection signal configuration level and sends the first rate selection signal to a signal processing unit;

the signal processing unit configures a transmission rate according to a level value of the first rate selection signal, including:

configuring a transmission rate to a high transmission rate when the level of the first rate selection signal is a high level;

when the level of the first rate selection signal is a low level, the transmission rate is configured to be a low transmission rate.

When the upper computer monitors that A0[64] bit6 is 0, the upper computer generates a second rate selection signal for a rate selection signal configuration level and sends the second rate selection signal to a signal processing unit;

said signal processing unit configures a transmission rate according to a level value of said second rate selection signal, including

Configuring a transmission rate to a low transmission rate when the level of the second rate selection signal is a high level;

when the level of the second rate selection signal is a low level, the transmission rate is configured to be a high transmission rate.

The upper computer comprises an MAC chip, wherein the MAC chip is used for reading the register value, configuring the level for the rate selection signal according to the register value, and sending the rate selection signal after the level is configured to the signal processing unit through the golden finger.

In summary, in the optical module and the signal polarity defining method provided by the present application, the optical module includes an MCU and a signal processing unit, the MCU includes an I2C interface and a register, wherein a gold finger is connected through an I2C interface to enable the MCU to communicate with an upper computer I2C, the register is any one of registers of reserved bits of a storage unit in the MCU, when the register is a first preset value, the signal processing unit receives a first rate selection signal generated by the upper computer according to a register value, and when a level of the first rate selection signal is a high level, the signal processing unit configures a high transmission rate, and when a level of the first rate selection signal is a low level, the signal processing unit configures a low transmission rate; when the register is a second preset value, the signal processing unit receives a second rate selection signal generated by the upper computer according to the register value, and configures a low transmission rate when the level of the second rate selection signal is a high level, and configures a high transmission rate when the level of the second rate selection signal is a low level.

The polarity of a rate selection signal Ratesel of an optical module is indicated by starting a register in a reserved byte, namely a reserved bit of a reserved bit storage unit of a storage unit, in an SFF-8472 protocol, and an upper computer MAC reads the value of the corresponding register through I2C to confirm the setting of the optical module and correspondingly carry out correct configuration; and further, the definition description of the polarity of the rate selection signal is added on the basis of the existing SFF-8472 protocol.

For the inexhaustible part of the signal polarity definition method provided in the embodiment of the present application, reference may be made to the optical module provided in the above embodiment.

Finally, it should be noted that: the embodiment is described in a progressive manner, and different parts can be mutually referred; in addition, the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (8)

1. A light module, comprising:

the circuit board is provided with a golden finger at one end;

MCU, set up on the circuit board, including I2C interface, I2C interface is connected with I2C pin electricity on the golden finger, includes:

a register for storing data;

the signal processing unit is used for receiving a level instruction signal from an upper computer and configuring a transmission rate according to the level instruction signal, and comprises:

when the data in the register is a first preset value, if the level command signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a low transmission rate;

and when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

2. The optical module according to claim 1, wherein the data stored in the register is read by an upper computer;

when the data in the register is a first preset value, the upper computer generates a corresponding level instruction signal, wherein the level instruction signal comprises a high level state and a low level state;

and when the data in the register is a second preset value, the upper computer generates a corresponding level instruction signal, wherein the level instruction signal comprises a high level state and a low level state.

3. The optical module of claim 1, wherein the register is a register in a user-writable area.

4. The optical module according to claim 1, wherein the data stored in the register is 1 or 0;

when the data in the register is 1, if the level command signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a low transmission rate;

when the data in the register is 0, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

5. The optical module of claim 1, wherein the register is a0[64] bit 6.

6. A method for defining signal polarity, the method comprising:

receiving a level instruction signal provided by an upper computer, and configuring a transmission rate according to the level instruction signal;

when the data in the register is a first preset value, if the level command signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a low transmission rate;

when the data in the register is a second preset value, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

7. The signal polarity definition method according to claim 6, wherein the data stored in the register is read by an upper computer;

when the data in the register is a first preset value, the upper computer generates a corresponding level instruction signal, wherein the level instruction signal comprises a high level state and a low level state;

and when the data in the register is a second preset value, the upper computer generates a corresponding level instruction signal, wherein the level instruction signal comprises a high level state and a low level state.

8. The signal polarity definition method according to claim 7, wherein the data stored in the register is 1 or 0;

when the data in the register is 1, if the level command signal is in a high level state, the transmission rate is configured to be a high transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a low transmission rate;

when the data in the register is 0, if the level command signal is in a high level state, the transmission rate is configured to be a low transmission rate, and if the level command signal is in a low level state, the transmission rate is configured to be a high transmission rate.

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