CN113471171A - 半导体元件 - Google Patents

半导体元件 Download PDF

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Publication number
CN113471171A
CN113471171A CN202110274972.XA CN202110274972A CN113471171A CN 113471171 A CN113471171 A CN 113471171A CN 202110274972 A CN202110274972 A CN 202110274972A CN 113471171 A CN113471171 A CN 113471171A
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connection
isolation layer
contacts
layer
semiconductor
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CN113471171B (zh
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黄则尧
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体元件，包括一第一半导体结构、一第一连接结构、一第二连接结构以及一第二半导体结构；该第一连接结构包括一第一连接隔离层、多个第一连接接触点以及多个第一支撑接触点，该第一连接隔离层位于该第一半导体结构上，该多个第一连接接触点位于该第一连接隔离层中，该多个第一支撑接触点位于该第一连接隔离层中。该第二连接结构位于该第一连接结构上，该第二半导体结构位于该第二连接结构上，其中该第二连接结构包括一第二连接隔离层、多个第二连接接触点以及多个第二支撑接触点，该第二连接隔离层位于该第一连接结构上，该多个第二连接接触点位于该第二连接隔离层中，该多个第二支撑接触点位于该第二连接隔离层中。

Description

半导体元件
技术领域
本公开主张2020年3月31日申请的美国正式申请案第16/836,081号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
背景技术
半导体元件是使用在不同的电子应用中，例如个人电脑、移动电话、数码相机，以及其他电子设备。半导体元件的尺寸持续地等比例缩小，以符合运算力(computingability)的需求。然而，许多的问题的变异是出现在等比例缩小工艺期间，且这些问题的数量及复杂度不断增加。因此，在达到改善品质、良率、效能与可靠度以及降低复杂度上仍具有挑战性。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体元件，包括一第一半导体结构、一第一连接结构、一第二连接结构以及一第二半导体结构；该第一连接结构包括一第一连接隔离层、多个第一连接接触点以及多个第一支撑接触点，该第一连接隔离层位于该第一半导体结构上，该多个第一连接接触点位于该第一连接隔离层中，该多个第一支撑接触点位于该第一连接隔离层中。该第二连接结构位于该第一连接结构上，该第二半导体结构位于该第二连接结构上，其中该第二连接结构包括一第二连接隔离层、多个第二连接接触点以及多个第二支撑接触点，该第二连接隔离层位于该第一连接结构上，该多个第二连接接触点位于该第二连接隔离层中，该多个第二支撑接触点位于该第二连接隔离层中；其中该多个第一连接接触点接触该多个第二连接接触点，形成多个信号传送接触；以及其中该多个第一支撑接触点接触该多个第二支撑接触点，在所述多个信号传送接触之间形成多个电气浮置接触。
在本公开的一实施例中，该第一连接隔离层的一上表面、该多个第一连接接触点的上表面以及该多个第一支撑接触点的上表面大致共面；以及其中该多个第一连接接触点的下表面接触该第一半导体结构的一上表面。
在本公开的一实施例中，该多个第一连接接触点具有一厚度，大于该多个第一支撑接触点的一厚度。
在本公开的一实施例中，该第一半导体结构包括一第一基底以及一第一内连接结构，该第一基底位于该第一连接结构下，该第一内连接结构位于该第一基底与该第一连接结构之间，其中该第一连接隔离层位于该第一内连接结构上。
在本公开的一实施例中，该第一内连接结构包括一第一隔离层以及多个第一导电特征，该第一隔离层位于该第一基底上，该多个第一导电特征位于该第一隔离层中，其中该多个第一连接接触点的下表面接触该多个第一导电特征的上表面，而该多个第一导电特征的上表面与该第一隔离层的一上表面为共面。
在本公开的一实施例中，该多个第一连接接触点的上表面接触该第二半导体结构的一下表面。
在本公开的一实施例中，该第二半导体结构包括一第二内连接结构以及一第二基底，该第二内连接结构位于该第一连接结构上，该第二基底位于该第二内连接结构上，其中该第二内连接结构包括一第二隔离层以及多个第二导电特征，该第二隔离层位于该第一连接结构上，该多个第二道店特征位于该第二隔离层中，其中该多个底一连接接触点的上表面接触该多个第二导电特征的下表面，而该多个第二特征的下表面与该第二隔离层的一下表面为共面。
在本公开的一实施例中，该第二内连接结构包括多个保护环，位于该第二隔离层中，其中该多个保护环的下表面接触该多个第一支撑接触点的上表面。
在本公开的一实施例中，该半导体元件还包括多个第一衬垫，位于该多个第一连接接触点的侧壁上，并位于该多个第一连接接触点下表面上。
在本公开的一实施例中，该半导体元件还包括一第一多孔层，位于该第一连接隔离层与该第二隔离层之间、该第一连接隔离层与该多个第一连接接触点之间，以及该第一连接隔离层与该多个第一支撑接触点之间，其中该第一多孔层的一孔隙率介于大约25％到大约100％之间。
在本公开的一实施例中，该半导体元件还包括多个第一衬垫，位于该第一多孔层与该多个第一连接接触点之间以及在该第一多孔层与所述多个第一支撑接触点之间。
在本公开的一实施例中，该半导体元件还包括一贯穿基底通孔，位于该第二基底中。
在本公开的一实施例中，该第一连接隔离层包括一第一下隔离层、一第一中间隔离层以及一第一上隔离层，该第一下隔离层位于该第一半导体结构的该上表面上，该第一中间隔离层位于该第一下隔离层上，该第一上隔离层位于该第一中间隔离层上，其中该多个第一连接接触点穿过该第一下隔离层、该第一中间隔离层以及该第一上隔离层，且该多个第一支撑接触点位于该第一上隔离层中。
在本公开的一实施例中，该多个第二连接接触点的下表面接触该多个第一连接接触点的上表面。
在本公开的一实施例中，该多个第一连接接触点的侧壁的一剖面轮廓呈倾斜的。
在本公开的一实施例中，该第一上隔离层包含一基础材料以及一可分解成孔剂材料
在一些实施例中，该基础材料包括甲基硅酸盐(methylsilsesquioxane)、低介电材料或氧化硅。
在一些实施例中，该能量处理的一能量源为热、光或其组合。
由于本公开的半导体元件的设计，多个半导体元件可经由该第一连接结构而连接在一起，以在占据较小体积时，提供更复杂的功能。因此，可降低该半导体元件的成本，并可增加该半导体元件的利润(profit)。此外，该多个第一支撑接触点可改善在该第一连接结构与该多个半导体结构之间的接合强度(bonding strength)。再者，所述多个电气浮置接触在所述多个电气信号传送接触之间实现电磁干扰屏蔽(electro-magneticinterference shielding)。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本公开的公开内容，附图中相同的元件符号是指相同的元件。
图1为依据本公开一些实施例的一种半导体元件的剖视示意图。
图2到图10为依据本公开一些实施例的各个半导体元件的剖视示意图。
图11为依据本公开一些实施例的一种半导体元件的制备方法的流程示意图。
图12到图16为依据本公开一实施例中制备该半导体元件的一流程的剖视示意图。
图17到图20为依据本公开另一实施例中制备一半导体元件的一流程的剖视示意图。
图21到图23为依据本公开另一实施例中制备一半导体元件的一流程的剖视示意图。
附图标记说明：
10A：半导体元件
10B：半导体元件
10C：半导体元件
10D：半导体元件
10E：半导体元件
10F：半导体元件
10G：半导体元件
10H：半导体元件
10I：半导体元件
10J：半导体元件
20：制备方法
100：第一半导体结构
101：第一基底
103：第一内连接结构
105：第一隔离层
107：第一导电线
109：第一导电通孔
111：第一导电接触点
113：第一阻障层
115：第一保护环
117：贯通基底通孔
121：第一下钝化层
200：第二半导体结构
201：第二基底
203：第二内连接结构
205：第二隔离层
207：第二导电线
209：第二导电通孔
211：第二导电接触点
213：第二阻障层
215：第二保护环
217：第二贯穿基底通孔
219：第二隔离侧壁
221：第二下钝化层
223：第二上钝化层
225：第二重分布层
227：第二上凸块金属化层
229：第二导电凸块
231：第二垫结构
400：第一连接结构
401：第一连接隔离层
403：第一下隔离层
405：第一中间隔离层
407：第一上隔离层
409：第一连接接触点
411：第一支撑接触点
413：第一衬垫
415：第一多孔层
417：能量可移除材料
500：第二连接结构
501：第二连接隔离层
503：第二下隔离层
505：第二中间隔离层
507：第二上隔离层
509：第二连接接触点
511：第二支撑接触点
513：第二衬垫
515：第二多孔层
S11：步骤
S13：步骤
S15：步骤
S17：步骤
Z：方向
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
以下描述了组件和配置的具体范例，以简化本公开的实施例。当然，这些实施例仅用以例示，并非意图限制本公开的范围。举例而言，在叙述中第一部件形成于第二部件之上，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不会直接接触的实施例。另外，本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚，除非内文中特别说明，其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所示出的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
此外，在本公开中形成一个部件在另一个部件之上(on)、与另一个部件相连(connected to)、及/或与另一个部件耦合(coupled to)，其可能包含形成这些部件直接接触的实施例，并且也可能包含形成额外的部件介于这些部件之间，使得这些部件不会直接接触的实施例。
应当理解，尽管这里可以使用术语第一，第二，第三等来描述各种元件、部件、区域、层或区段(sections)，但是这些元件、部件、区域、层或区段不受这些术语的限制。相反，这些术语仅用于将一个元件、组件、区域、层或区段与另一个区域、层或区段所区分开。因此，在不脱离本发明进部性构思的教导的情况下，下列所讨论的第一元件、组件、区域、层或区段可以被称为第二元件、组件、区域、层或区段。
除非内容中另有所指，否则当代表定向(orientation)、布局(layout)、位置(location)、形状(shapes)、尺寸(sizes)、数量(amounts)，或其他测量(measures)时，则如在本文中所使用的例如“同样的(same)”、“相等的(equal)”、“平坦的(planar)”，或是“共面的(coplanar)”等术语(terms)并非必要意指一精确地完全相同的定向、布局、位置、形状、尺寸、数量，或其他测量，但其意指在可接受的差异内，是包含差不多完全相同的定向、布局、位置、形状、尺寸、数量，或其他测量，而举例来说，所述可接受的差异是可因为制造流程(manufacturing processes)而发生。术语“大致地(substantially)”是可被使用在本文中，以表现出此意思。举例来说，如大致地相同的(substantially the same)、大致地相等的(substantially equal)，或是大致地平坦的(substantially planar)，为精确地相同的、相等的，或是平坦的，或者是其是可为在可接受的差异内的相同的、相等的，或是平坦的，而举例来说，所述可接受的差异是可因为制造流程而发生。
在本公开中，一半导体元件通常意指可通过利用半导体特性(semiconductorcharacteristics)运行的一元件，而一光电元件(electro-optic device)、一发光显示元件(light-emitting display device)、一半导体线路(semiconductor circuit)以及一电子元件(electronic device)，是均包括在半导体元件的范围中。特别地是，本街漏的所述多个实施例的所述多个半导体元件可为动态随机存取存储器元件。
需注意的是，在本公开的描述中，上方(above)(或之上(up))是对应Z方向箭头的该方向，而下方(below)(或之下(down))是对应Z方向箭头的相对方向。
图1为依据本公开一些实施例的一种半导体元件10A的剖视示意图。
请参考图1，半导体元件10A可包括一第一半导体结构100、一第二半导体结构200以及一第一连接结构400。第一半导体结构100与第二半导体结构200可为一半导体晶圆、一半导体晶圆的一部分或是一半导体晶粒。在所述的实施例中，第一半导体结构100与第二半导体结构200为半导体晶粒。第一半导体结构100可包括一第一基底101以及一第一内连接结构103。第一内连接结构103可设置在第一基底101上。
请参考图1，举例来说，第一基底101可由下列材料所制：硅、碳化硅(siliconcarbide)、锗硅锗(germanium silicon germanium)、砷化镓、砷化铟(indium arsenide)或其他包含III族、IV族以及V族的半导体材料。在一些实施例中，第一基底101可包括一绝缘体上覆硅(silicon-on-insulator)结构。举例来说，第一基底101可包括一埋入氧化物层，通过使用例如氧离子注入分离(separation by implanted oxygen)的一工艺所形成。
请参考图1，第一内连接结构103可包括一第一隔离层105、多个装置元件(deviceelements)(为了清楚故并未显示在图1中)以及多个第一导电特征。第一隔离层105可设置在第一基底101上。在一些实施例中，第一隔离层105可为一堆叠层结构。第一隔离层105可包括多个第一隔离子层。每一第一隔离子层可具有一厚度，介于大约0.5微米到大约3.0微米之间。举例来说，多个第一隔离子层可由下列材料所制：氧化硅、硼磷硅酸盐玻璃(borophosphosilicate glass)、未掺杂硅酸盐玻璃(undoped silicate glass)、掺杂氟的硅酸盐玻璃(fluorinated silicate glass)、低介电常数(low-k)的介电材料、其类似物或其组合。多个隔离子层可由不同材料所制，但并不以此为限。低介电常数的介电材料可具有小于3.0或甚至小于2.5的一介电常数。在一些实施例中，低介电常数的介电材料可具有小于2.0的一介电常数。
在一些实施例中，多个装置元件可设置在第一隔离层105的一下部中。多个装置元件可设置在第一基底101上。举例来说，多个装置元件可为双极接面晶体管(bipolarjunction transistor)、金属氧化物半导体场效晶体管(metal oxide semiconductorfield effect transistor)、二极管、系统大规模集成电路(system large-scaleintegration)、快闪存储器(flash memories)、动态随机存取存储器、静态随机存取存储器、电性可抹除可程序化只读存储器(electrically erasable programmable read-onlymemories)、影像感测器、微机电系统(micro-electro-mechanical-systems)、主动元件或无源元件。在一些实施例中，装置元件的一部分可设置在第一基底101中。举例来说，一金属氧化物半导体场效晶体管的源极/漏极区可设置在第一基底101中。在一些实施例中，所述多个装置元件可通过隔离结构而电性隔离邻近的装置元件，而隔离结构是例如浅沟隔离(shallow trench isolations)。
应当理解，在本公开的描述中，沿着Z方向位于最高垂直高度(level)的一元件(或一特征)的一表面，是表示该元件(或该特征)的一上表面。沿着Z方向位于最低垂直高度的一元件(或一特征)的一表面，是表示该元件(或该特征)的一下表面。
请参考图1，多个第一导电特征可设置在第一隔离层105中。举例来说，多个第一导电特征可包括多个第一导电线107、多个第一导电通孔109以及多个第一导电接触点111。所述多个导电通孔109沿着Z方向可连接邻近的所述多个导电线。所述多个导电通孔109可改善在第一内连接结构103中的散热，并提供结构性支撑给第一内连接结构103。在一些实施例中，多个装置元件可经由多个第一导电特征而进行内连接。在一些实施例中，一些第一导电特征可包括较宽的部分。所述多个较宽的部分可表示为第一导电垫。在一些实施例中，多个第一阻障层113可设置在多个第一导电特征与第一隔离层105之间。每一第一阻障层113可覆盖相对应的第一导电特征的侧壁以及一下表面。一些第一阻障层113可设置在一些第一导电特征之间。举例来说，其中一第一阻障层113可设置在相互邻近的一第一导电线107与一第一导电通孔109之间。
请参考图1，第一内连接结构103可包括多个第一保护环(first guard rings)115。多个第一保护环115由一些第一导电线107以及一些第一导电通孔109电性连接所组成。多个第一保护环115可为虚拟(dummies)。多个第一保护环115可具有与第一隔离层105相同的一厚度。换言之，多个第一保护环115沿Z方向可穿过第一隔离层105。在多个第一导电特征形成期间，多个第一保护环115可促进平坦化工艺。多个第一保护环115亦可促进与其他结构的一接合(bonding)工艺，该其他结构是例如第一连接结构400或第二半导体结构200。再者，多个第一保护环115可改善第一内连接结构103的机械强度(mechanicalstrength)。在一些实施例中，第一保护环115可由沿着Z方向并相互分开设置的一些导电线107所组成。
应当理解，一元件表示成一“虚拟(dummy)”元件是意指该元件电性隔离所有的装置元件。此外，当半导体元件在操状状态下，将不会有外部电压或电流施加到该元件。
请参考图1，第一隔离层105的上表面以及一些第一导电线107的上表面可大致共面。在一些实施例中，第一隔离层105的上表面、一些第一导电线107的上表面以及一些第一保护环115的上表面可大致共面。在一些实施例中，第一隔离层105的上表面、一些第一导电线107的上表面、一些第一保护环115的上表面以及一些第一阻障层113的上表面可大致共面。由第一隔离层105的上表面、一些第一导电线107的上表面、一些第一保护环115的上表面以及一些第一阻障层113的上表面所组成的平面可表示为第一内连接结构103的上表面。
在一些实施例中，一些第一导电接触点111的下表面以及第一隔离层105的下表面可大致共面。在一些实施例中，一些第一导电接触点111的下表面、一些其他第一保护环115的下表面、第一隔离层105的下表面以及第一基底101的上表面可大致共面。由一些第一导电接触点111的下表面、一些其他第一保护环115的下表面以及第一隔离层105的下表面所构成的平面可表示为第一内连接结构103的下表面。
举例来说，多个第一导电线107、多个第一导电通孔109以及多个第一导电接触点111可由下列材料所制：铜、铝、钛、其类似物或其组合。多个第一导电线107、多个第一导电通孔109以及多个第一导电接触点111可由不同材料所制，但并不以此为限。举例来说，多个第一阻障层113可由下列材料所制：氮化钛、氮化钽、钛、钽、钛钨(titanium tungsten)、其类似物或其组合。
请参考图1，第二半导体结构200可与第一半导体结构100相对设置，且第一连接结构400夹置在第二半导体结构200与第一半导体结构100之间。第一半导体结构100与第二半导体结构200可提供不同功能。举例来说，第一半导体结构100可提供一逻辑功能，且第二半导体结构200可提供一存储器功能。在一些实施例中，第一半导体结构100与第二半导体结构200可提供相同功能。
请参考图1，第二半导体结构200可包括一第二基底201、一第二内连接结构203、一第二贯穿基底通孔(through substrate via)217、多个第二隔离侧壁219、一第二上钝化层223、一第二重分布层225、一第二上凸块金属化层227以及一第二导电凸块229。
请参考图1，第二基底201与第一连接结构400可相对设置，且第二内连接结构203夹置在第二基底201与第一连接结构400之间。第二基底201具有类似于第一基底101的一结构，但并不以此为限。第二基底201可由与第一基底101相同的材料所制，但并不以此为限。第二内连接结构203可具有类似于第一内连接结构103的一结构，但并不以此为限。在本实施例中，第二内连接结构203可具有类似于第一内连接结构103的一结构，但可以上下颠倒的方式设置。第二内连接结构203可包括一第二隔离层205、多个装置元件(为了清楚故并未显示在图1中)、多个第二导电特征、多个第二阻障层213以及多个第二保护环215。第二半导体结构200的多个装置元件可设置在邻近第二隔离层205的一上部处。
请参考图1，多个第二导电特征可设置在第二隔离层205中。多个第二导电特征可包括多个第二导电线207、多个第二导电通孔209以及多个第二导电接触点211。多个保护环215可由一些第二导电线207连接到一些第二导电通孔209所组成。多个第二保护环215可为虚拟(dummies)。
请参考图1，一些第二导电线207的下表面、第二隔离层205的下表面、一些第二保护环215的下表面以及一些第二阻障层213的下表面可大致共面。由一些第二导电线207的下表面、第二隔离层205的下表面、一些第二保护环215的下表面以及一些第二阻障层213的下表面所组成的平面可表示成第二内连接结构203的下表面。一些第二导电接触点211的上表面、一些第二保护环215的上表面以及第二隔离层205的上表面可大致共面。由一些第二导电接触点211的上表面、一些第二保护环215的上表面以及第二隔离层205的上表面所组成的平面可表示成第二内连接结构203的上表面。
请参考图1，第二贯穿基底通孔217可设置在第二基底201中，并电性连接到其中一第二导电接触点211。在一些实施例中，第二贯穿基底通孔217可经由一些第二导电特征而电性连接到第一半导体结构100的其中一装置元件。在一些实施例中，第二贯穿基底通孔217可经由一些导电特征而电性连接到第一内连接结构400。在一些实施例中，第二贯穿基底通孔217可不穿经第二隔离层205。在一些实施例中，第二贯穿基底通孔217可不占用第二半导体结构200的多余的空间。因此，更多的装置元件可设置在第二半导体结构200中，以提供一更复杂的半导体元件。举例来说，第二贯穿基底通孔217可由下列材料所制：铜、铝、钛、其类似物或其组合。
请参考图1，所述多个第二隔离侧壁219可设置在第二贯通基底通孔217的侧壁上。所述多个第二隔离侧壁219可电性绝缘第二贯通基底通孔217与邻近的装置元件，而邻近的所述多个装置元件设置在邻近第二贯通基底通孔217的两侧处。第二下钝化层221可设置在第二基底201上。第二上钝化层223可设置在第二下钝化层221上。一第二重分布层225可设置在第二下钝化层221中。第二下钝化层221的一部分以及第二上钝化层223的一部分可凹陷以暴露第二重分布层225的一上表面的一部分。举例来说，第二下钝化层221与第二上钝化层223可由下列材料所制：氮化硅、氮氧化硅、氮化氧化硅(silicon oxide nitride)、聚亚酰胺(polyimide)、聚苯并恶唑(polybenzoxazole)或其组合。第二下钝化层221与第二上钝化层223可由不同材料所制，但并不以此为限。第二重分布层225可电性连接到第二贯通基底通孔217。举例来说，第二重分布层225可由下列材料所制：钨、钛、锡、镍、铜、金、铝、铂、钴或其组合。
应当理解，在本公开中，氮氧化硅表示一物质(substance)，其是包含硅、氮以及氧，且氧的一比率大于氮的一比率。氧化氮化硅(Silicon nitride oxide)表示一物质，其是包含硅、氧以及氮，且氮的一比率大于氧的一比率。
请参考图1，第二下凸块金属化层227可设置在第二上钝化层223与第二重分布层225的上表面的该部分上。第二导电凸块229可设置在第二下凸块金属化层227上，并电性连接到第二重分布层225。举例来说，第二下凸块金属化层227可由下列材料所制：铬(chromium)、钨、钛、铜、镍、铝、钯(palladium)、金、钒(vanadium)或其组合。第二导电凸块229可为一焊料凸块(solder bump)。
第二下凸块金属化层227可为一单一层结构或多层的一堆叠结构。举例来说，第二下凸块金属化层227可包括按序堆叠的一第一导电层、一第二导电层以及一第三导电层。第一导电层可当作是一粘着层，用于稳定贴合第二导电凸块229到第二重分布层225与第二上钝化层223。举例来说，第一导电层可包含以下至少其中之一：钛、钛钨(titanium-tungsten)、铬以及铝。第二导电层可当作是一阻障层，以避免包含在第二导电凸块229中的一导电材料扩散进入第二重分布层225或第二上钝化层223。第二导电层可包含以下至少其中之一：铜、镍、铬铜(chromium-copper)以及镍钒(nickel-vanadium)。第三导电层可当作是一晶种层(seed layer)，用以形成第二导电凸块229，或者是当作是一润湿层(wettinglayer)，用以改善第二导电凸块229的湿润特性(wetting characteristics)。第三导电层可包含以下至少其中之一：镍、铜以及铝。
请参考图1，第一连接结构400可设置在第一半导体结构100与第二半导体结构200之间。第一连接结构400可包括一第一连接隔离层401、多个第一连接接触点409、多个第一支撑接触点411以及多个第一衬垫413。第一连接隔离层401可设置在第一内连接结构103的上表面上。
请参考图1，多个第一连接接触点409与多个第一支撑接触点411可设置在第一连接隔离层401中。多个第一支撑接触点411可为虚拟(dummies)。多个第一连接接触点409可具有一厚度，大于多个第一支撑接触点411的一厚度。多个第一连接接触点409的上表面可接触或接合到一些第二导电线207的下表面，而所述多个第二导电线207的下表面是与第二内连接结构203共面。多个第一连接接触点409的上表面可具有一宽度，是等于或小于一些第二导电线207的下表面的一宽度，而所述多个第二导电线207的下表面是与第二内连接结构203的下表面共面。多个第一连接接触点409的下表面可接触或接合到一些第一导电线107的上表面，所述多个第一导电线107的上表面是与第一内连接结构103的上表面共面。多个第一连接接触点409的下表面可具有一宽度，是等于或小于一些第一导电线107的上表面的一宽度，而所述多个第一导电线107的上表面是与第一内连接结构103的上表面共面。
请参考图1，多个第一支撑接触点411的上表面可接触或接合到多个第二保护环215的下表面，而该多个第二保护环215的下表面是与第二内连接结构203的下表面共面。在一些实施例中，多个第一支撑接触点411的一些上表面可接触或接合到多个第二保护环215的下表面，而该多个第二保护环215的下表面是与第二内连接结构203的下表面共面。在一些实施例中，多个第一支撑接触点411的下表面可接触或接合到一些第二保护环215，所述多个第二保护环215是与第二内连接结构203的下表面共面。
在一些实施例中，多个第一连接接触点409可沿着Z方向而穿过第一连接隔离层401，并经由一些第一导电特征以及一些第二导电特征而电性连接第一半导体结构100的装置元件以及第二半导体结构200的装置元件。在一些实施例中，第一连接隔离层401可为一多层结构，包含一第一下隔离层403、一第一中间隔离层405以及一第一上隔离层407。第一下隔离层403可设置在第一内连接结构103的上表面上。第一下隔离层403可为一蚀刻终止层，举例来说，并可由下列材料所制：氮化硅、碳化硅、氧化硅、低介电常数(low-k)的介电材料、极低介电常数的介电材料、其类似物或其组合。举例来说，低介电常数的介电材料可为掺碳氧化物(carbon doped oxides)。举例来说，极低介电常数的介电材料可为多孔掺碳氧化硅(porous carbon doped silicon oxide)。
请参考图1，第一中间隔离层405可设置在第一下隔离层403上。第一上隔离层407可设置在第一中间隔离层405上。第二内连接结构203可设置在第一上隔离层407上。举例来说，第一中间隔离层405与第一上隔离层407可由下列材料所制：氧化硅、氮氧化硅、氮化硅、硼硅酸盐玻璃(borosilicate glass)、硼磷硅酸盐玻璃(borophosphosilicate glass)、磷硅酸盐玻璃(phosphoric silicate glass)、氟化硅玻璃(fluorinated silicate glass)、低介电常数介电材料或其组合。第一中间隔离层405与第一上隔离层407可由相同材料所制，但并不以此为限。举例来说，多个第一连接接触点409与多个第一支撑接触点411可由下列材料所制：铝、铜、钨或钴。
请参考图1，多个第一连接接触点409沿着Z方向可穿过第一上隔离层407、第一中间隔离层405以及第一下隔离层403。多个第一支撑接触点411沿着Z方向可穿过第一上隔离层407。在一些实施例中，多个第一支撑接触点411可穿过第一上隔离层407与第一中间隔离层405的一上部。多个第一支撑接触点411可促进与第二半导体结构200的一接合工艺。
请参考图1，多个第一衬垫413可设置在多个第一连接接触点409的侧壁上、在多个第一连接接触点409的下表面上、在多个第一支撑接触点411的侧壁上以及多个第一支撑接触点411的下表面上。举例来说，多个第一衬垫413可由下列材料所制：氮化钛、氮化钽、钛、钽、钛钨(titanium tungsten)、其类似物或其组合。
请参考图1，多个第一连接接触点409的上表面、多个第一支撑接触点411的上表面、多个第一衬垫413的上表面以及第一上隔离层407的一上表面可大致共面。由多个第一连接接触点409的上表面、多个第一支撑接触点411的上表面、多个第一衬垫413的上表面以及第一上隔离层407的上表面所构成的平面，可表示为第一连接结构400的上表面。
请参考图1，在本公开的实施例中，该多个第一连接接触点409接触该多个第二连接接触点509，形成多个信号传送接触。在本公开的实施例中，该多个第一支撑接触点411接触该多个第二支撑接触点511，在所述多个信号传送接触之间形成多个电气浮置接触。在本公开的实施例中，该第一上隔离层407包含一基础材料以及一可分解成孔剂材料，该基础材料包括甲基硅酸盐(methylsilsesquioxane)、低介电材料或氧化硅，该能量处理的一能量源为热、光或其组合。
图2到图10为依据本公开一些实施例的各个半导体元件10B、10C、10D、10E、10F、10G、10H、10I以及10J的剖视示意图。
请参考图2，在半导体元件10B中，一第一多孔层415可设置在第一上隔离层407的一上表面上、在多个第一支撑接触点411的侧壁与下表面上以及多个第一连接接触点409的侧壁上。在一些实施例中，多个第一衬垫413可设置在第一多孔层415与多个第一连接接触点409之间，以及在第一多孔层415与多个第一支撑接触点411之间。第一多孔层415可由一能量可移除材料所制，将于后详述。
第一多孔层415可包括一骨架(skeleton)以及多个空的空间，而多个空的空间设置在骨架各处。多个空的空间可相互连接，并充填有空气。举例来说，骨架可包含氮化硅、低介电材料或甲基硅酸盐(methylsilsesquioxane)。第一多孔层415可具有一孔隙率(porosity)，介于25％到100％之间。应当理解，当孔隙率为100％时，其是指第一多孔层415紧包括一空的空间，且第一多孔层415可当成是一气隙。在一些实施例中，第一多孔层415的孔隙率可介于45％到95％之间。第一多孔层415的多个空的空间可充填有空气。结果，举例来说，第一多孔层415的一介电常数可甚低于由氧化硅所制的一层。因此，第一多孔层415可大大地降低在多个第一连接接触点409与多个第一支撑接触点411之间的寄生电容(parasitic capacitance)。意即，第一多孔层415可大大地减轻在由第一连接结构400所产生的电子信号与施加到第一连接结构400的电子信号之间的一干涉效应(interferenceeffect)。
能量可移除材料可包含一材料，例如一热可分解材料、一光可分解材料、一电子束可分解材料或其组合。举例来说，能量可移除材料可包括一基础材料以及一可分解成孔剂材料(decomposable porogen material)，而该可分解成孔剂材料是在暴露在一能量源时而被牺牲地移除。
请参考图3，在半导体元件10C中，第一多孔层415可仅设置在第一上隔离层407上。第一连接隔离层401与能量可移除材料的一层可按序形成在第一内连接结构103上。接下来，多个第一连接接触点409、多个第一支撑接触点411以及多个第一衬垫413可通过执行一单一或双镶嵌(damascene)工艺的单一或多个叠代(iterations)并经由图案化在第一多孔层415上所形成。
请参考图4，在半导体元件10D中，多个第一连接接触点409的侧壁以及多个第一支撑接触点411的侧壁可具有一倾斜剖面轮廓。在一些实施例中，每一第一连接接触点409的一宽度或是每一第一支撑接触点411的一宽度，可沿着Z方向从下到上逐渐变宽。在一些实施例中，每一第一连接接触点409的整体或每一第一支撑接触点411的整体可具有一均匀斜率。
请参考图5，在半导体元件10E中，第一半导体结构100可以上下颠倒的方式置放。第一连接结构400可设置在第一基底101上。多个第一贯通基底通孔117可设置在第一基底101中。多个第一贯通基底通孔117可电性连接多个第一连接接触点409到一些第一导电接触点111。一第一下钝化层121可设置在第一内连接结构103下方。举例来说，第一下钝化层121可由下列材料所制：氮化硅、氮氧化硅、氮化氧化硅、聚亚酰胺、聚苯并恶唑或其组合。第一半导体结构100与第二半导体结构200可以面对背(face-to-back)的方式堆叠。
请参考图6，在半导体元件10F中，一第二下钝化层221可设置在第二基底201上。举例来说，第二下钝化层221可由下列材料所制：氮化硅、氮氧化硅、氮化氧化硅、聚亚酰胺、聚苯并恶唑或其组合。一第二垫结构231可穿过第二下钝化层221、第二基底201以及第二内连接结构203的一上部。第二垫结构231可电性连接到其中一个第二导电线207。
请参考图7，在半导体元件10G中，第二半导体结构200可以类似于第一半导体结构100的方式置放。第二基底201可设置在第一连接结构400上。第二下钝化层221可设置在第二内连接结构203上。第二贯通基底通孔217可设置在第二基底201中。第二贯通基底通孔217可电性连接一些第二导电接触点211到负多个第一连接接触点409。第一半导体结构100与第二半导体结构200可以背对面(back-to-face)方式堆叠。
请参考图8，在半导体元件10H中，第一连接结构400可以上下颠倒方式置放。第一上隔离层407可设置在第一内连接结构103上。第二内连接结构203可设置在第一下隔离层403上。多个第一支撑接触点411的下表面可接触所述多个第一保护环115的上表面。
请参考图9，在半导体元件10I中，一第二连接结构500可设置在第二半导体结构200与第一连接结构400之间。第二连接结构500可具有类似于第一连接结构400的一结构，但以上下颠倒方式置放。第二连接结构500可包括一第二连接隔离层501、多个第二连接接触点509、多个第二支撑接触点511以及多个第二衬垫513。第二连接隔离层501可包括一第二下隔离层503、一第二中间隔离层505以及一第二上隔离层507。第二上隔离层507可设置在第一连接结构400上。第二中间隔离层505可设置在第二上隔离层507上。第二下隔离层503可设置在第二中间隔离层505上，并可为一蚀刻终止层。
请参考图9，多个第二连接接触点509可穿过第二下隔离层503、第二中间隔离层505以及第二上隔离层507。多个第二连接接触点509可电性连接一些第二导电线207到多个第一连接接触点409。所述多个第二支撑接触点511可设置在第二下隔离层503中。多个第二支撑接触点511的下表面可接触或接合到多个第一支撑接触点411的上表面。多个第二衬垫513可设置在多个第二连接接触点509与第二连接隔离层501之间、在多个第二支撑接触点511与第二连接隔离层501之间以及在多个第二连接接触点509与一些第二导电线207之间。
请参考图10，在半导体元件10J中，一第二多孔层515可设置在第二上隔离层507的下表面上、在多个第二支撑接触点511的侧壁与下表面上以及在多个第二连接接触点509的侧壁上。第二多孔层515可由与第一多孔层415相同的材料所制。第二多孔层515可具有一孔隙率，介于25％到100％之间。设置在第二上隔离层507的下表面上的第二多孔层515以及设置在第一上隔离层407的上表面上的第一多孔层407可相互接触或接合。在一些实施例中，第一多孔层415可仅设置在第一上隔离层407的上表面上，且第二多孔层515可仅设置在第二上隔离层507的下表面上。
请参考图10，在贴合过程中，第一多孔层415与第二多孔层515的厚度因其多孔特性而减少；如此，第一支撑接触点411与第二支撑接触点511可形成突部，其可避免电气介电的上隔离材料在金属-金属贴合之间形成电气隔离。因此，可在第一半导体结构100与第二半导体结构200之间形成更稳定可靠的贴合结构。
应当理解，“正在形成(forming)”、“已经形成(formed)”以及“形成(form)”的术语，可表示并包括任何产生(creating)、构建(building)、图案化(patterning)、植入(implanting)或沉积(depositing)一零件(element)、一掺杂物(dopant)或一材料的方法。形成方法的例子可包括原子层沉积(atomic layer deposition)、化学气相沉积(chemicalvapor deposition)、物理气相沉积(physical vapor deposition)、喷溅(sputtering)、旋转涂布(spin coating)、扩散(diffusing)、沉积(depositing)、生长(growing)、植入(implantation)、光刻(photolithography)、干蚀刻以及湿蚀刻，但并不以此为限。
图11为依据本公开一些实施例的一种半导体元件10A的制备方法的流程示意图。图12到图16为依据本公开一实施例中制备该半导体元件的的一流程的剖视示意图。
请参考图11及图12，在步骤S11，可提供一第一半导体结构100。第一半导体结构100可包括一第一基底101以及一第一内连接结构103，而第一内连接结构103形成在第一基底101上。第一内连接结构103可包括一第一隔离层105、多个装置元件、多个第一导电特征、多个第一阻障层113以及多个第一保护环115。第一半导体结构100的多个装置元件可形成在第一隔离层105的一下部中。一些装置元件的一部分可形成在第一基底101的一上部中。多个第一导电特征、多个第一阻障层113以及多个第一保护环115可形成在第一隔离层105中。举例来说，多个第一导电特征可包括多个第一导电线107、多个第一导电通孔109以及多个第一导电接触点111。一些第一导电线107、一些第一导电通孔109以及一些第一阻障层113可一起形成多个第一保护环115。第一半导体结构100的多个装置元件与多个第一导电特征可电性连接。
请参考图11及图13，在步骤S13，一第一连接结构400可形成在第一半导体结构100上。第一连接结构400可包括一第一连接隔离层401、多个第一连接接触点409、多个第一支撑接触点411以及多个第一衬垫413。第一连接隔离层401可包括一第一下隔离层403、一第一中间隔离层405以及一第一上隔离层407。第一下隔离层403、第一中间隔离层405以及第一上隔离层407可按序形成在第一内连接结构103上。
可执行一系列的光刻工艺、蚀刻工艺、沉积工艺以及平坦化工艺，以形成多个第一连接接触点409、多个第一支撑接触点411以及多个第一衬垫413。可形成多个第一连接接触点409以便穿过第一上隔离层407、第一中间隔离层405以及第一下隔离层403，并可电性连接到邻近第一内连接结构103的一上表面的一些第一导电特征。多个第一支撑接触点411可形成在第一上隔离层407中。多个第一衬垫413可形成在多个第一连接接触点409与第一连接隔离层401之间、在多个第一支撑接触点411与第一连接隔离层401之间以及在多个第一连接接触点409与邻近第一内连接结构103的一上表面的一些第一导电特征之间。
请参考图11、图14及图15，在步骤S15，一第二半导体结构200可经由一接合工艺而接合到第一连接结构400。请参考图14，可提供一第二半导体结构200。第二半导体结构200可通过一类似于用于形成第一半导体结构100的一程序(procedure)所形成，并可具有类似于第一半导体结构100的结构。第二半导体结构200可以上下颠倒的方式置放。请参考图15，上下颠倒的第二半导体结构200可置放在第一连接结构400的上表面上。可执行一热处理以达到在第二半导体结构200与用于接合工艺的第一连接结构400的元件之间的一混合接合(hybrid bonding)。混合接合可包括一氧化物与氧化物接合(oxide-to-oxide bonding)以及一金属与金属接合(metal-to-metal bonding)。氧化物与氧化物接合可源自于在第二隔离层205与第一上隔离层407之间的接合。金属与金属接合可源自于在多个第一连接接触点409与一些第二导电线207之间的接合，以及源自于在多个第一支撑接触点411与多个第二保护环215之间的接合。接合工艺的一温度可介于大约300℃到大约450℃之间。一薄化(thinning)工艺可执行在第二基底201上，而薄化工艺可使用一蚀刻工艺、一化学机些研磨工艺或一抛光(polishing)工艺，以缩减第二基底201的一厚度。
请参考图11及图16，在步骤S17，一第二贯通基底通孔217与多个第二隔离侧壁219可形成在第二半导体结构200的第二基底201上，且一第二下钝化层221、一第二上钝化层223、一第二重分布层225、一第二下凸块金属化层227以及一第二导电凸块229可形成在第二半导体结构200的第二基底201上。第二下钝化层221与第二上钝化层223可按序形成在第二基底201上。第二重分布层225可形成在第二下钝化层221中。第二贯通基底通孔217可形成在第二基底201中，并可电性连接第二重分布层225到其中一个第二导电接触点211。第二下钝化层221的一部分与第二上钝化层223的一部分可凹陷，以形成一开孔，进而暴露第二重分布层225的一上表面的一部分。第二下凸块金属化层227与第二导电凸块229可按序形成在该开孔中。
图17到图20为依据本公开另一实施例中制备一半导体元件10B的的一流程的剖视示意图。
请参考图17，一能量可移除材料417的一层可形成在第一上隔离层407的上表面上、形成在多个第一连接接触点409与第一连接隔离层401之间，以及形成在多个第一支撑接触点411与第一连接隔离层401之间。能量可移除材料417可包含一材料，例如一热可分解材料、一光可分解材料、一电子束可分解材料或其组合。举例来说，能量可移除材料417可包括一基础材料以及一可分解成孔剂材料，而该可分解成孔剂材料是在暴露在一能量源时而被大致地移除。基础材料包含一甲基硅酸盐(methylsilsesquioxane)基础材料。可分解成孔剂材料则可包含一成孔剂有机化合物，其隙提供孔隙率给能量可移除材料的基础材料。在能量可移除材料417的该层形成之后，通过使用能量源，一能量处理可执行在图17的中间半导体元件上。能量源可包括热、光或其组合。当热被用来当作能量源时，能量处理的一温度可介于大约800℃到大约900℃之间。当光被用来当作能量源时，可使用一紫外光(ultraviolet light)。能量处理可从能量可移除材料移除可分解成孔剂材料，以产生空的空间(孔洞(pores))，且基础材料保留在原处。
或者是，在另一实施例中，基础材料可为氧化硅。可分解成孔剂材料可包括化合物，化合物包含多个不饱和键(unsaturated bonds)，例如双键或三键。在能量处理期间，可分解成孔剂材料的所述多个不饱合键可交联(cross-link)基础材料的氧化硅。因此，可分解成孔剂材料可收缩并产生多个空的空间，且基础材料保留在原处。所述多个空的空间可充填有空气，以使所述多个空的空间的一介电常数可为极低。在一些实施例中，基础材料可为低介电常数(low-k)的介电材料。
在一些实施例中，能量可移除材料417可包括一相对高浓度的可分解成孔剂材料以及一相对低浓度的基础材料，但并不以此为限。举例来说，能量可移除材料417可包含大约75％或更高的可分解成孔剂材料以及大约25％或更低的基础材料。在其他的例子中，能量可移除材料417可包含大约95％或更高的可分解成孔剂材料以及大约5％或更低的基础材料。在另外的例子中，能量可移除材料417可包含大约100％的可分解成孔剂材料，且没有基础材料。在另外的例子中，能量可移除材料417可包含大约45％或更高的可分解成孔剂材料以及大约55％或更低的基础材料。
请参考图18，在能量处理之后，能量可移除材料417的该层可转变成一第一多孔层415。基础材料可转变成第一多孔层415的一骨架，且所述多个空的空间可分布在第一多孔层415的骨架的各处。依据能量可移除材料417的成分，第一多孔层415可具有一孔隙率，孔隙率为45％、75％、95％或100％。在能量处理之后，可执行一平坦化工艺，例如化学机械研磨，以提供一大致平坦表面给接下来的处理步骤。
请参考图19，在第一连接结构400与第二半导体结构200之间的一接合工艺期间，由于其多孔特性，所以可薄化形成在第一上隔离层407的上表面上的第一多孔层415。结果，多个第一连接接触点409的上表面、多个第一支撑接触点411的上表面以及多个第一衬垫413的上表面可形成多个突部(protrusions)(以虚线圆圈凸显在图19中)。多个突部可避免金属与金属接合与第一上隔离层407或第二隔离层205的介电干涉。因此，可达到在第二半导体结构200与第一连接结构400之间一还可靠的接合。请参考图20，多个元件可以类似于如图16所图例的一程序(procedure)所形成。
图21到图23为依据本公开另一实施例中制备一半导体元件10H的的一流程的剖视示意图。
请参考图21，一第一半导体结构100与一第二半导体结构200可以类似于如图12所图例的一程序所形成。第一连接结构400可以类似于如图13所图例的一程序而形成在第二半导体结构200上。接下来，第二半导体结构200与第一连接结构400可以上下颠倒的方式置放，并位于第一半导体结构100上方。
请参考图22，可执行一接合工艺以接合第一连接结构400到第一半导体结构100。一热处理可使用在图22中的中间半导体元件，以达到第一半导体结构100到第一连接结构400的一混合接合。请参考图23，一第二下钝化层221可形成在第二基底201上。可形成一第二垫结构231以便穿过第二下钝化层221、第二基底201以及第二隔离层205的一上部。第二垫结构231可电性连接到其中一个第二导电线207。
本公开的一实施例提供一种半导体元件，包括一第一半导体结构、一第一连接结构、一第二连接结构以及一第二半导体结构；该第一连接结构包括一第一连接隔离层、多个第一连接接触点以及多个第一支撑接触点，该第一连接隔离层位于该第一半导体结构上，该多个第一连接接触点位于该第一连接隔离层中，该多个第一支撑接触点位于该第一连接隔离层中。该第二连接结构位于该第一连接结构上，该第二半导体结构位于该第二连接结构上，其中该第二连接结构包括一第二连接隔离层、多个第二连接接触点以及多个第二支撑接触点，该第二连接隔离层位于该第一连接结构上，该多个第二连接接触点位于该第二连接隔离层中，该多个第二支撑接触点位于该第二连接隔离层中；其中该多个第一连接接触点接触该多个第二连接接触点，形成多个信号传送接触；以及其中该多个第一支撑接触点接触该多个第二支撑接触点，在所述多个信号传送接触之间形成多个电气浮置接触。
由于本公开的半导体元件的设计，多个半导体结构可经由第一连接结构而连接在一起，以在占据较小体积时，提供更复杂的功能。因此，可降低该半导体元件的成本，并可增加该半导体元件的利润(profit)。此外，该多个第一支撑接触点可改善在该第一连接结构与多个第一半导体结构之间的接合强度(bonding strength)。再者，所述多个电气浮置接触在所述多个电气信号传送接触之间实现电磁干扰屏蔽(electro-magneticinterference shielding)。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。

Claims (15)

1.一种半导体元件，包括：
一第一半导体结构；以及
一第一连接结构，设置于该第一半导体结构上，包括一第一连接隔离层、多个第一连接接触点以及多个第一支撑接触点，该第一连接隔离层位于该第一半导体结构上，该多个第一连接接触点位于该第一连接隔离层中，该多个第一支撑接触点位于该第一连接隔离层中；
一第二连接结构以及一第二半导体结构，该第二连接结构位于该第一连接结构上，该第二半导体结构位于该第二连接结构上，其中该第二连接结构包括一第二连接隔离层、多个第二连接接触点以及多个第二支撑接触点，该第二连接隔离层位于该第一连接结构上，该多个第二连接接触点位于该第二连接隔离层中，该多个第二支撑接触点位于该第二连接隔离层中；
其中该多个第一连接接触点接触该多个第二连接接触点，形成多个信号传送接触；以及
其中该多个第一支撑接触点接触该多个第二支撑接触点，在所述多个信号传送接触之间形成多个电气浮置接触。
2.如权利要求1所述的半导体元件，其中该第一连接隔离层的一上表面、该多个第一连接接触点的上表面以及该多个第一支撑接触点的上表面大致共面；以及其中该多个第一连接接触点的下表面接触该第一半导体结构的一上表面。
3.如权利要求2所述的半导体元件，其中该多个第一连接接触点具有一厚度，大于该多个第一支撑接触点的一厚度。
4.如权利要求3所述的半导体元件，其中该第一半导体结构包括一第一基底以及一第一内连接结构，该第一基底位于该第一连接结构下，该第一内连接结构位于该第一基底与该第一连接结构之间，其中该第一连接隔离层位于该第一内连接结构上。
5.如权利要求4所述的半导体元件，其中该第一内连接结构包括一第一隔离层以及多个第一导电特征，该第一隔离层位于该第一基底上，该多个第一导电特征位于该第一隔离层中，其中该多个第一连接接触点的下表面接触该多个第一导电特征的上表面，而该多个第一导电特征的上表面与该第一隔离层的一上表面为共面。
6.如权利要求5所述的半导体元件，其中该多个第一连接接触点的上表面接触该第二半导体结构的一下表面。
7.如权利要求6所述的半导体元件，其中该第二半导体结构包括一第二内连接结构以及一第二基底，该第二内连接结构位于该第一连接结构上，该第二基底位于该第二内连接结构上，其中该第二内连接结构包括一第二隔离层以及多个第二导电特征，该第二隔离层位于该第一连接结构上，该多个第二道店特征位于该第二隔离层中，其中该多个底一连接接触点的上表面接触该多个第二导电特征的下表面，而该多个第二特征的下表面与该第二隔离层的一下表面为共面。
8.如权利要求7所述的半导体元件，其中该第二内连接结构包括多个保护环，位于该第二隔离层中，其中该多个保护环的下表面接触该多个第一支撑接触点的上表面。
9.如权利要求8所述的半导体元件，还包括多个第一衬垫，位于该多个第一连接接触点的侧壁上，并位于该多个第一连接接触点下表面上。
10.如权利要求8所述的半导体元件，还包括一第一多孔层，位于该第一连接隔离层与该第二隔离层之间、该第一连接隔离层与该多个第一连接接触点之间，以及该第一连接隔离层与该多个第一支撑接触点之间，其中该第一多孔层的一孔隙率介于大约25％到大约100％之间。
11.如权利要求10所述的半导体元件，还包括多个第一衬垫，位于该第一多孔层与该多个第一连接接触点之间以及在该第一多孔层与所述多个第一支撑接触点之间。
12.如权利要求11所述的半导体元件，还包括一贯穿基底通孔，位于该第二基底中。
13.如权利要求1所述的半导体元件，其中该第一连接隔离层包括一第一下隔离层、一第一中间隔离层以及一第一上隔离层，该第一下隔离层位于该第一半导体结构的该上表面上，该第一中间隔离层位于该第一下隔离层上，该第一上隔离层位于该第一中间隔离层上，其中该多个第一连接接触点穿过该第一下隔离层、该第一中间隔离层以及该第一上隔离层，且该多个第一支撑接触点位于该第一上隔离层中。
14.如权利要求13所述的半导体元件，其中该多个第二连接接触点的下表面接触该多个第一连接接触点的上表面。
15.如权利要求13所述的半导体元件，其中该多个第一连接接触点的侧壁的一剖面轮廓呈倾斜的。
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US11107775B1 (en) 2021-08-31
TWI786535B (zh) 2022-12-11

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