CN113470709B

CN113470709B - Temperature sensing circuit and sensing method thereof

Info

Publication number: CN113470709B
Application number: CN202010247617.9A
Authority: CN
Inventors: 佐藤贵彦
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2024-04-12
Anticipated expiration: 2040-03-31
Also published as: CN113470709A

Abstract

In one aspect of the present invention, a temperature sensing circuit and a sensing method are provided, the sensing circuit is suitable for a memory device. The temperature sensing circuit comprises an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit. The oscillator provides an oscillating signal. The counting circuit counts the oscillating signals to generate a first counting signal and generates a second counting signal. The control circuit performs logic operation on the second count signal to generate an enable signal and a sensing adjustment signal. The sensing circuit divides the reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and compares the reference temperature voltage with the monitoring voltage according to the enabling signal to generate a determination signal. The selection circuit dynamically selects one of the oscillation signal and the first count signal according to the determination signal, and generates a pulse of the refresh request signal according to the dynamically selected one of the oscillation signal and the first count signal.

Description

Temperature sensing circuit and sensing method thereof

Technical Field

The present invention relates to a memory device, and more particularly, to a temperature sensing circuit for providing a refresh request signal and a sensing method thereof.

Background

A Dynamic Random Access Memory (DRAM) includes a plurality of memory cells (memory cells) for storing bits of data, each bit being determined according to a level of a potential accumulated on a capacitor of the memory cell. The charge accumulated on the capacitor gradually discharges to cause difficulty in potential judgment after a certain period of time. The period of time from the start of discharge of the charge on the capacitor to the logic potential ("0" or "1") at which the data cannot be judged with certainty is called a refresh time. The refresh request signal must be provided every a period of time shorter than the refresh time to refresh (refresh) the memory cells and hold (hold) data. And the refresh interval (refresh interval) refers to a time interval between two refresh request signals.

In DRAM, the memory cells have different retention times (refresh times) for different temperatures, so that different refresh intervals are applicable. For example, when a DRAM memory cell is reduced from 55℃to 20℃its retention time is increased by a factor of about 4, which is suitable for a 4-fold refresh interval. Thus, the prior art utilizes multiple temperature thresholds to divide the operating temperature into multiple zones, each zone having a different refresh interval. The operating temperature is divided into three temperature zones, for example using two temperature thresholds of 55 ℃ and 20 ℃): more than 55 ℃, less than 55 ℃ and more than 20 ℃, and less than 20 ℃, and adjusting the time interval of the temperature sections of less than 55 ℃ and more than 20 ℃ to be 4 times of the temperature section of more than 55 ℃, and adjusting the time interval of less than 20 ℃ to be 16 times of the temperature section of more than 55 ℃ to provide refresh request signals of different refresh intervals according to different temperatures.

However, current consumption of the prior art at slightly above the temperature threshold increases. For example, at a temperature slightly higher than 55 ℃ but not yet varying the refresh interval, and at a temperature slightly higher than 20 ℃ but not yet varying the refresh interval, the refresh frequency of the refresh request signal is 4 times higher than 55 ℃ and 20 ℃ respectively, resulting in a larger refresh current consumption. Another approach is to use more temperature thresholds to separate the operating temperature into more temperature zones, however more counters, temperature sensing circuits and selectors are added to the circuit. In addition to increasing costs, more counters will also cause the counter bits to be reduced, resulting in lower refresh interval resolution.

Disclosure of Invention

Therefore, the present invention provides a temperature sensing circuit capable of providing an average refresh interval corresponding to a temperature with high resolution without increasing clock frequency and current consumption.

In one aspect of the present invention, a temperature sensing circuit is provided, suitable for use in a memory device. The temperature sensing circuit comprises an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit. The oscillator is used for providing an oscillating signal. The counting circuit is coupled to the oscillator for counting the oscillating signal to generate a first counting signal and for generating a second counting signal. The control circuit is coupled to the counting circuit and is used for performing logic operation on the second counting signal to generate an enabling signal and a sensing adjustment signal. The sensing circuit is coupled to the control circuit, divides the reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and compares the reference temperature voltage with the monitoring voltage according to the enable signal to generate a determination signal. The selection circuit is coupled to the oscillator, the counting circuit and the sensing circuit, dynamically selects one of the oscillating signal and the first counting signal according to the determination signal, and generates a pulse of the refresh request signal according to the dynamically selected one of the oscillating signal and the first counting signal.

In another aspect of the present invention, a sensing method is provided, suitable for a memory device. The memory device is provided with a temperature sensing circuit, wherein the temperature sensing circuit is provided with an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit. The sensing method comprises the following steps: providing an oscillating signal; the oscillating signal is counted to generate a first count signal and a second count signal. The second counting signal is logically operated to generate an enabling signal and a sensing adjustment signal. The reference voltage is divided according to the sensing adjustment signal to generate a reference temperature voltage, and the reference temperature voltage is compared with the monitoring voltage according to the enabling signal to generate a determination signal. One of the oscillation signal and the first count signal is dynamically selected according to the determination signal, and a pulse of the refresh request signal is generated according to the dynamically selected one of the oscillation signal and the first count signal.

Based on the above, the temperature sensing circuit of the present invention can dynamically adjust the proportion of the pulses with different refresh intervals in the refresh request signal according to the temperature of the memory cell, so as to provide a high average refresh interval and a high resolution of the average refresh interval with respect to the temperature without increasing the clock frequency and the consumption current.

So that the manner in which the above recited features and advantages of the present invention are attained and can be understood in detail, exemplary embodiments thereof are described in detail. It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.

However, it should be understood that this summary may not contain all aspects and embodiments of the present invention, and thus is not meant to be limiting or restrictive in any way. Further, the present invention will include improvements and modifications apparent to those skilled in the art.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a block diagram of a temperature sensing circuit according to an embodiment of the invention;

FIG. 2 is a schematic circuit diagram of a temperature sensing circuit according to an embodiment of the invention;

FIG. 3 is a control timing diagram of a temperature sensing circuit according to an embodiment of the invention;

fig. 4 is a conversion table of the count signal cnt_n and the sensing adjustment signal ST in the control circuit according to an embodiment of the invention;

FIG. 5 is a timing diagram illustrating generation of a refresh request signal according to an embodiment of the present invention;

FIG. 6A is a table of average interval statistics for estimated refresh requests, according to one embodiment of the present invention;

FIG. 6B is an X-Y plot of estimated average interval of refresh requests versus temperature, according to an embodiment of the present invention;

FIG. 7 is a block diagram of a temperature sensing circuit according to another embodiment of the present invention;

FIG. 8 is a schematic circuit diagram of a temperature sensing circuit according to another embodiment of the present invention;

FIG. 9 is a timing diagram of a temperature sensing circuit according to another embodiment of the present invention;

FIG. 10A is a table of average interval statistics for estimated refresh requests, according to another embodiment of the present invention;

FIG. 10B is an X-Y plot of estimated average interval of refresh requests versus temperature, according to another embodiment of the present invention;

FIG. 11A is a table of average interval statistics for estimated refresh requests, according to yet another embodiment of the present invention; FIG. 11B is an X-Y plot of estimated average interval of refresh requests versus temperature, in accordance with yet another embodiment of the present invention;

FIG. 12 is a flow chart of a method of operating a temperature sensing circuit according to an embodiment of the invention.

Description of the reference numerals

10. 20: temperature sensing circuit

110: oscillator

120: counting circuit

130: control circuit

140: sensing circuit

150: selection circuit

210 to 230: counter

240: voltage dividing circuit

250: switch string

251 to 252: selector

260: monitoring voltage generating circuit

270: comparator with a comparator circuit

280: latch device

Cnt_1, cnt_ N, CNT _4: counting signal

COUNT: refresh pulse count

D1: diode

DET: determining a signal

EN: enable signal

GND: ground voltage

IC: current source

OSC: oscillation signal

R1 to R8: voltage dividing resistor

REFREQ: refresh request signal

S1210 to S1250: step (a)

ST: sensing an adjustment signal

SUM: sum of refresh pulses

SW1 to SW7: switch

T0-T3: time of

VC: compared voltage

VMON: monitoring voltage

VREF: reference voltage

VRT: reference temperature voltage VT 20-VT 80: default temperature voltage

Detailed Description

Referring to fig. 1, a temperature sensing circuit 10 is adapted for use with a memory device (not shown). The temperature sensing circuit 10 includes an oscillator 110, a counting circuit 120, a control circuit 130, a sensing circuit 140, and a selection circuit 150. In this embodiment, the temperature sensing circuit 10 is used to provide a refresh request signal REFREQ to a refresh circuit (not shown) in the memory device to drive the refresh circuit to refresh memory cells (not shown) in the memory device. In the present invention, the temperature sensing circuit 10 counts the oscillation signal OSC to generate the reference temperature voltage VRT corresponding to each temperature of the memory cell, and dynamically adjusts the average refresh interval of the refresh request signal refeq by comparing the monitor voltage VMON corresponding to the current temperature of the memory cell with the reference temperature voltage VRT corresponding to each temperature, so that the refresh request signal refeq has a relatively high average refresh interval and provides a refresh interval with high resolution for temperature without increasing the frequency of the oscillation signal OSC.

Please refer to fig. 1 and fig. 2 at the same time. The oscillator 110 is used for providing an oscillation signal OSC to the counting circuit 120 and the selecting circuit 150. In one embodiment, the oscillator 110 may be a voltage-controlled oscillator (VCO), and the oscillation signal OSC may be a pulse signal with a fixed frequency, but the invention is not limited thereto.

The counting circuit 120 is coupled to the oscillator 110, and the counting circuit 120 receives the oscillation signal OSC and counts the oscillation signal OSC to generate the count signals cnt_1 and cnt_n. In an embodiment, the counting circuit 120 may count the pulse number of the oscillation signal OSC, and the counting circuit 120 may be a conventional synchronous counter or other counter, but the invention is not limited thereto. Specifically, in one embodiment, the counting circuit 120 includes counters 210-230.

The counter 210 is coupled to the oscillator 110 for receiving and counting the pulse number of the oscillation signal OSC to generate the count signal cnt_4. In one embodiment, the counter 210 generates a pulse of the count signal cnt_4 every 4 rising edges of the oscillation signal OSC, so that the period of the count signal cnt_4 is 4 times that of the oscillation signal OSC. And the count of the counter 210 is reset to 0 each time the counter 210 counts the pulses of the 4 oscillation signals OSC.

The counter 220 is coupled between the counter 210 and the selection circuit 150, and is used for receiving and counting the pulse number of the count signal cnt_4 to generate the count signal cnt_1. In one embodiment, the counter 220 generates a pulse of the count signal cnt_1 every 4 count edges of the count signal cnt_4, so that the period of the count signal cnt_1 is 4 times that of the count signal cnt_4, and the period of the count signal cnt_1 is 16 times that of the oscillation signal OSC. And the count of the counter 210 is reset to 0 each time the counter 220 counts 4 count signals cnt_4.

The counter 230 is used for receiving and counting the pulse number of the oscillation signal OSC to generate the count signal cnt_n. In one embodiment, the counter 230 generates a pulse of the count signal cnt_n every time the counter counts the upper edges of the N oscillation signals OSC, so that the period of the count signal cnt_n is N times that of the oscillation signal OSC. And the count of the counter 230 is reset to 0 each time the counter 230 counts the N oscillation signals OSC. In one embodiment, N may be a multiple of 16, such as 16, 64.

It should be noted that the counters 210 and 220 are used to assist the selection circuit 150 in adjusting the refresh interval of the refresh request signal REFREQ, and the counter 230 is used to generate the selected reference temperature voltage VRT through the control circuit 130, which will be described later. The invention is not limited to the manner in which the counters 210 to 230 count signals.

The control circuit 130 is coupled to the counting circuit 120, and in one embodiment, the control circuit 130 may be a central processing unit, a microprocessor, an application specific integrated circuit, a field programmable gate array, or the like, or a combination thereof. Wherein the control circuit 130 is programmed to perform functions or steps that will be described below: the control circuit 130 receives the count signal cnt_n, and performs a logic operation on the count signal cnt_n to generate the enable signal EN and the sensing adjustment signal ST.

In one embodiment, when the control circuit 130 detects that the number of pulses of the oscillation signal OSC is equal to a default number according to the count signal cnt_n, the control circuit 130 enables (enables) the enable signal EN and provides the enable signal EN to the sensing circuit 140. Specifically, in one embodiment, each time the control circuit 130 receives the pulse of the count signal cnt_n, i.e. when the counter 230 counts the pulses of the 16 oscillation signals OSC, the control circuit 130 enables the enable signal EN provided to the sensing circuit 140 to a high logic level (high logic level) so as to enable the sensing circuit 140.

Referring to fig. 2 and fig. 4, in an embodiment, the control circuit 130 performs logic conversion on the count signal cnt_n according to a default conversion table shown in fig. 4 to generate the sensing adjustment signal ST, wherein the logic value of the sensing adjustment signal ST corresponds to a plurality of default temperatures of the memory. Specifically, referring to fig. 4, in one embodiment, the count signal cnt_n has 4 bits, i.e., bit0A to bit3A, and the sense adjustment signal ST has 3 bits, i.e., bit0B to bit2B. For example, when the count signal cnt_n is 6, i.e. 0110, the control circuit 130 performs logic conversion on the count signal cnt_n according to fig. 4, and takes the values of bits 0A to 2A of the count signal cnt_n to generate the sensing adjustment signal ST, so that the sensing adjustment signal ST is 6 (i.e. 110). When the count signal cnt_n is 7, i.e. 0111, the control circuit 130 performs logic conversion on the count signal cnt_n according to fig. 4, and takes the values of bits 0A to bit2A of the count signal cnt_n, i.e. 111, to generate the sensing adjustment signal ST, but the logic conversion defaults to convert 111 to 000, so that the sensing adjustment signal ST is 0 (i.e. 000).

Referring to the conversion table of fig. 4 and the timing sequence of the count signal cnt_n and the sensing adjustment signal ST in fig. 5, the logic value of each count signal cnt_n corresponds to the logic value of the sensing adjustment signal ST. In one embodiment, when the count signal cnt_n is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, the control circuit 130 performs a logic operation to generate the sensing adjustment signal ST as 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 0, 1, 0. However, the invention is not limited thereto.

Referring to fig. 2, the sensing circuit 140 is coupled to the control circuit 130 and receives the enable signal EN, the sensing adjustment signal ST and the reference voltage VREF. The sensing circuit 140 divides the reference voltage VREF according to the sensing adjustment signal ST to generate the reference temperature voltage VRT, and the sensing circuit 140 compares the reference temperature voltage VRT with the monitor voltage VMON according to the enable signal EN to generate the determination signal DET. In one embodiment, the sensing circuit 140 includes a voltage divider circuit 240, a switch string 250, a monitor voltage generating circuit 260, a comparator 270 and a latch 280.

Specifically, the sensing circuit 140 may divide the reference voltage VREF by the voltage dividing circuit 240, and turn on one switch in the switch string 250 according to the sensing adjustment signal ST to generate the reference temperature voltage VRT. The sensing circuit 140 can generate the monitor voltage VMON through the monitor voltage generating circuit 260, compare the reference temperature voltage VRT with the monitor voltage VMON through the enable signal EN enable the comparator 250, and generate the compared voltage VC according to the comparison result and provide the compared voltage VC to the latch 280. The sensing circuit 140 latches (latch) the compared voltage VC through the latch 280 to generate the decision signal DET and provide it to the selection circuit 150.

The voltage dividing circuit 240 has a plurality of voltage dividing resistors R1 to R8 connected in series, wherein the voltage dividing resistors R1 to R8 are coupled between the reference voltage VREF and the ground voltage GND, and generate a plurality of default temperature voltages VT20 to VT80 by dividing a voltage difference between the reference voltage VREF and the ground voltage GND. The voltage division between the voltage dividing resistors R1 and R2 is a default temperature voltage VT20, the voltage division between the voltage dividing resistors R2 and R3 is a default temperature voltage VT30, the voltage division between the voltage dividing resistors R3 and R4 is a default temperature voltage VT40, the voltage division between the voltage dividing resistors R4 and R5 is a default temperature voltage VT50, the voltage division between the voltage dividing resistors R5 and R6 is a default temperature voltage V60, the voltage division between the voltage dividing resistors R6 and R7 is a default temperature voltage VT70, and the voltage division between the voltage dividing resistors R7 and R8 is a default temperature voltage VT80.

The switch string 250 is coupled to the control circuit 130 and the voltage divider 240, and has a plurality of switches SW1 to SW7. The first terminal of each of the plurality of switches SW1 to SW7 receives one of a plurality of default temperature voltages VT20 to VT80. In one embodiment, the first terminal of switch SW1 receives the default temperature voltage VT20, the first terminal of switch SW2 receives the default temperature voltage VT30, the first terminal of switch SW3 receives the default temperature voltage VT40, the first terminal of switch SW4 receives the default temperature voltage VT50, the first terminal of switch SW5 receives the default temperature voltage VT60, the first terminal of switch SW6 receives the default temperature voltage VT70, and the first terminal of switch SW7 receives the default temperature voltage VT80. The second ends of all switches SW1 to SW7 are coupled to each other. The switch string 250 turns on one of the switches SW1 to SW7 according to the sensing adjustment signal ST, and provides one of the default temperature voltages VT20 to VT80 corresponding to the turned-on one of the switches SW1 to SW7 to the second end of the switches SW1 to SW7 so as to generate the reference temperature voltage VRT. In one embodiment, when switch SW1 is turned on, reference temperature voltage VRT equals default temperature voltage VT20, and so on. In one embodiment, the corresponding relation between the logic value of the sensing adjustment signal ST and the reference temperature voltage VRT is VRT [10 x (8-i) ]=st [ i ], i=0-6. For example, when i is 0, VRT [80 ])=st [0]. In one embodiment, the detailed correspondence between the logic value of the sensing adjustment signal ST and the reference temperature voltage VRT is as follows.

< Table I >

ST	0	1	2	3	4	5	6
								VRT	VT 80	VT 70	VT 60	VT 50	VT 40	VT 30	VT 20

The monitor voltage generating circuit 260 is used for providing the monitor voltage VMON. In one embodiment, the monitor voltage generating circuit 260 includes a constant current source IC and a diode D1. The constant current source IC is configured to provide a constant current, and the diode D1 is coupled between the constant current source IC and the ground voltage GND for generating the monitor voltage VMON according to the constant current. The present invention is not limited to the type of constant current source IC.

The comparator 270 is coupled to the switch string 250 and the monitor voltage generating circuit 260 for comparing the reference temperature voltage VRT with the monitor voltage VMON according to the enable signal EN so as to generate the compared voltage VC. In one embodiment, the comparator 270 has a positive input, a negative input, an enable, and an output. The positive input of the comparator 270 is coupled to the monitor voltage generating circuit 260 to receive the monitor voltage VMON, and the negative input of the comparator 270 is coupled to the switch string 250 to receive the reference temperature voltage VRT. The enable terminal of the comparator 270 is coupled to the control circuit 130 for receiving the enable signal EN to determine whether to perform the comparison operation. When the enable signal EN is disabled (e.g., low logic level), the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON. When the enable signal EN is enabled (e.g., high logic level), the comparator 270 compares the reference temperature voltage VRT with the monitor voltage VMON, and outputs the comparison result as the compared voltage VC. When the monitor voltage VMON is less than the reference temperature voltage VRT, the comparator 270 outputs a disabled compared voltage VC (e.g., low logic level). When the monitor voltage VMON is greater than the reference temperature voltage VRT, the comparator 270 outputs an enabled compared voltage VC (e.g., high logic level).

The latch 280 is coupled to the comparator 270 for latching the compared voltage VC to generate the decision signal DET and providing the decision signal DET to the selection circuit 150. In one embodiment, when the enable signal EN is disabled, the latch 280 takes the hold state as the determination signal DET and outputs the determination signal DET to the selection circuit 150. When the enable signal EN is enabled, the latch 280 latches the comparison voltage VC and outputs the refresh determination signal DET to the selection circuit 150.

Referring to fig. 1 and 2, the selecting circuit 150 is coupled to the oscillator 110, the counting circuit 120 and the sensing circuit 140, and the selecting circuit 150 dynamically selects one of the oscillating signal OSC and the counting signal cnt_1 according to the determination signal DET and generates a pulse of the refresh request signal refeq according to the dynamically selected oscillating signal OSC and the counting signal cnt_1. In one embodiment, the selection circuit 150 includes selectors 251 and 252, the selector 251 is coupled between the oscillator 110 and the sensing circuit 140, and the selector 252 is coupled between the counting circuit 120 and the sensing circuit 140. The selectors 251 and 252 are alternately activated according to the logic level of the determination signal DET to generate the refresh request signal refresh together, and the specific timing is described later.

In one embodiment, when the determination signal DET is enabled, the selector 251 outputs the pulse of the oscillation signal OSC and the selector 252 does not output the signal, and when the determination signal DET is disabled, the selector 252 outputs the pulse of the count signal cnt_1 and the selector 251 does not output the signal to collectively generate the refresh request signal REFREQ.

FIG. 3 is a control timing diagram of a temperature sensing circuit according to an embodiment of the invention. Referring to fig. 2 and 3, in an embodiment, the period of the count signal cnt_4 is 4 times that of the oscillation signal OSC, the period of the count signal cnt_1 is 4 times that of the count signal cnt_4, and the period of the count signal cnt_n is 4 times that of the count signal cnt_1. Thus, in one embodiment, the period of the count signal cnt_n is 64 times that of the oscillation signal OSC. The control circuit 130 logically converts the count signal cnt_n according to the conversion table of fig. 4, and generates the sensing adjustment signal ST. The switch string 250 in the sensing circuit 140 turns on one of the switches SW1 to SW7 according to the sensing adjustment signal ST to receive one of the default temperature voltages VT20 to VT80, and thereby generates the reference temperature voltage VRT. Taking fig. 3 as an example, the values of the reference temperature voltages VRT are sequentially equal to the default temperature voltages VT60, VT50, VT80, and VT70 from left to right. The monitor voltage generating circuit 260 in the sensing circuit 140 generates the monitor voltage VMON. In this embodiment, the monitor voltage VMON corresponds to a default temperature voltage VT55 (not shown) between the default temperature voltages VT60 and VT 50.

Between time T0 and time T1, the enable signal EN is disabled, and the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON, and the determination signal DET is disabled (e.g., at a low logic level).

At time T1, the enable signal EN is enabled, and the comparator 270 compares the reference temperature voltage VRT with the monitor voltage VMON. Since the reference temperature voltage VRT (which is equal to VT 50) is greater than the monitor voltage VMON, the comparator 270 generates an enabled compared voltage VC (not shown), and since the enable signal EN is enabled, the latch 280 generates an enabled determination signal DET (e.g., high logic level).

Then, between time T1 and time T2, since the enable signal EN is disabled, the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON, and the latch 280 latches the previously enabled compared voltage VC, so that the latch 280 maintains the logic level of the enabled determination signal DET.

At time T2, the enable signal EN is enabled, and the comparator 270 compares the reference temperature voltage VRT with the monitor voltage VMON. Since the reference temperature voltage VRT at this time (which is equal to VT80 at this time) is smaller than the monitor voltage VMON, the comparator 270 generates the disabled compared voltage VC (not shown), and since the enable signal EN is enabled, the latch 280 generates the disabled determination signal DET.

Then, between time T2 and time T3, since the enable signal EN is disabled, the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON, and the latch 280 latches the previously disabled compared voltage VC, so that the latch 280 maintains the logic level of the disabled determination signal DET.

Referring to fig. 2 and 3, the selection circuit 150 dynamically selects one of the oscillation signal OSC and the count signal cnt_1 according to the determination signal DET, and generates the refresh request signal REFREQ according to the dynamically selected one of the oscillation signal OSC and the count signal cnt_1. For example, between time T0 and time T1, the determination signal DET is disabled, so the selector 252 in the selection circuit 150 outputs the pulse of the count signal CNT_1 and the selector 251 does not output the signal. Between time T1 and time T2, the determination signal DET is enabled, so that the selector 251 in the selection circuit 150 outputs the pulse of the oscillation signal OSC and the selector 252 does not output the signal. Between time T2 and time T3, the decision signal DET is disabled, so the selector 252 in the selection circuit 150 outputs the pulse of the count signal cnt_1 and the selector 251 does not output the signal.

FIG. 5 is a timing diagram illustrating generation of refresh request signals according to an embodiment of the present invention. Fig. 6A is a table of average interval statistics for estimated refresh requests, according to one embodiment of the present invention. Referring to fig. 2, 4, 5 and 6A, in an embodiment, the control circuit 130 logically converts the count signal cnt_n according to the conversion table of fig. 4 to generate the sensing adjustment signal ST, which corresponds to the count signal cnt_n and the sensing adjustment signal ST of fig. 5. The switch string 250 in the sensing circuit 140 turns on one of the switches SW1 to SW7 according to the sensing adjustment signal ST to receive one of the default temperature voltages VT20 to VT80 and thereby generate the reference temperature voltage VRT, which corresponds to the sensing adjustment signal ST and the reference temperature voltage VRT in fig. 5. When the monitor voltage VMON is between the default temperature voltages VT50 and VT60 (e.g., VT 55), and when the reference temperature voltage VRT is between the default temperature voltages VT 20-VT 50, the sensing circuit 140 enables the determination signal DET (i.e., the high logic level H); when the reference temperature voltage VRT is the default temperature voltages VT 60-VT 80, the sensing circuit 140 disables the determination signal DET (i.e., the low logic level L). When the decision signal DET is disabled, the selector 252 in the selection circuit 150 outputs the pulse of the count signal cnt_1 and the selector 251 does not output the signal; when the determination signal DET is enabled, the selector 251 in the selection circuit 150 outputs a pulse of the oscillation signal OSC and the selector 252 does not output a signal. Accordingly, the selectors 251 and 252 are alternately activated according to the logic level of the determination signal DET to generate the refresh request signal refresh in common, which corresponds to the determination signal DET and the refresh request signal refresh in fig. 5. In one embodiment, the refresh pulse COUNT of the refresh request signal REFREQ in each period is shown in FIG. 5, and the SUM of the refresh pulses SUM of the refresh request signal REFREQ in the whole period (i.e. the COUNT signal CNT_N is from logic value 0 to 15) is 91, please refer to the SUM of the refresh pulses 91 corresponding to the temperature 55 ℃ in FIG. 6A. In another scenario, when the monitor voltage VMON is between the default temperature voltages VT60 and VT70 (e.g., VT 65), the corresponding determination signal is changed to the high logic level H when the reference temperature voltage VRT is the default temperature voltage VT 60. Therefore, the SUM of refresh pulses SUM corresponds to 121, please refer to the SUM of refresh pulses 121 in fig. 6A at 65 ℃.

Referring to fig. 6A, taking the memory as an example with a temperature of 55 ℃, the refresh pulse COUNT [1] (i.e., the number of refresh pulse COUNTs of 1 pulse for a refresh request signal refeq of a single period in the whole period) is 11, the refresh pulse COUNT [16] (i.e., the number of refresh pulse COUNTs of 16 pulses for a refresh request signal refeq of a single period in the whole period) is 5, the SUM of refresh pulses SUM is 91, the average number of refresh pulses SUM is 5.69 (i.e., the SUM of refresh pulses SUM divided by 16), the average refresh interval is 2.81 (i.e., 16 divided by the average number of refresh pulses), and the other temperatures are the same, and are not repeated. As can be seen from FIG. 6A, the temperature sensing circuit 10 can provide refresh request signals REFREQ with different average refresh intervals at different temperatures of the memory device.

FIG. 6B is an X-Y plot of estimated average interval of refresh requests versus temperature, in accordance with an embodiment of the present invention. Referring to fig. 6A and 6B, the temperature sensing circuit 10 provides different average refresh intervals every 10 ℃ in a temperature range of 20 ℃ to 80 ℃ to achieve high refresh interval resolution. In other words, the temperature sensing circuit 10 can dynamically adjust the ratio of the refresh pulse count [1] to the refresh pulse count [16] in the whole period according to the memory temperature, so as to adjust the average refresh interval, thereby improving the resolution of the average refresh interval to the temperature. The current consumption can be further reduced since no more selection circuits, counters and temperature sensors (not shown) need to be added for multi-temperature step-wise control.

FIG. 7 is a block diagram of a temperature sensing circuit according to another embodiment of the invention. Fig. 7 is substantially the same as fig. 1, and will not be described again. The difference between fig. 7 and fig. 1 is that the counting circuit 120 in the temperature sensing circuit 20 in fig. 7 also receives the refresh request signal REFREQ and generates the counting signal cnt_n according to the refresh request signal REFREQ.

FIG. 8 is a circuit diagram of a temperature sensing circuit according to another embodiment of the invention. Fig. 8 is substantially the same as fig. 2, and will not be described again. The difference between fig. 8 and fig. 2 is that the counter 230 in the temperature sensing circuit 20 in fig. 8 is configured to receive and count the number of pulses of the refresh request signal REFREQ to generate the count signal cnt_n. In another embodiment, the counter 230 generates a pulse of the count signal cnt_n every 1 refresh request signal refresh every time the counter counts the upper edges of the refresh request signal refresh, so that the period of the count signal cnt_n is 1 time the refresh request signal refresh.

FIG. 9 is a timing diagram of a temperature sensing circuit according to another embodiment of the invention. Referring to fig. 9, in another embodiment, a counter 230 in the temperature sensing circuit 20 is configured to receive and count the number of pulses of the refresh request signal REFREQ to generate a count signal cnt_n. The control circuit 130 in the temperature sensing circuit 20 logically converts the count signal cnt_n according to the conversion table of fig. 4, so as to generate the sensing adjustment signal ST and generate the enable signal EN. It corresponds to the count signal cnt_n and the sensing adjustment signal ST in fig. 9. The switch string 250 of the sensing circuit 140 of the temperature sensing circuit 20 turns on one of the switches SW1 to SW7 according to the sensing adjustment signal ST to receive one of the default temperature voltages VT20 to VT80 and generate the reference temperature voltage VRT, which corresponds to the sensing adjustment signal ST and the reference temperature voltage VRT of fig. 9. When the monitor voltage VMON is between the default temperature voltages VT50 and VT60 (e.g., VT 55), and when the reference temperature voltage VRT is the default temperature voltages VT 20-VT 50, the sensing circuit 140 disables the decision signal DET; when the reference temperature voltage VRT is the default temperature voltages VT 60-VT 80, the sensing circuit 140 enables the determination signal DET. When the determination signal DET is enabled, the selector 252 in the selection circuit 150 outputs the pulse of the count signal cnt_1 and the selector 251 does not output the signal; when the decision signal DET is disabled, the selector 251 in the selection circuit 150 outputs a pulse of the oscillation signal OSC and the selector 252 does not output a signal. Accordingly, the selectors 251 and 252 are alternately activated according to the logic level of the determination signal DET to generate the refresh request signal refresh in common, which corresponds to the determination signal DET and the refresh request signal refresh in fig. 9. In another embodiment, the refresh interval of the refresh request signal REFREQ for each period is shown in fig. 9, and the total refresh interval of the refresh request signal REFREQ for the whole period (i.e. the count signal cnt_n is from logic value 0 to 15) is 61.

Fig. 10A is a table of average interval statistics for estimated refresh requests, according to another embodiment of the present invention. Referring to fig. 10A, taking the memory as an example with the temperature of 55 ℃, the refresh pulse count [16] is 3, the refresh pulse count [1] is 13, the average refresh interval is 3.81, and the other temperatures are the same, and the details are not repeated. Thus, as can be seen from FIG. 10A, in another embodiment, the temperature sensing circuit 20 can provide refresh request signals REFREQ with different average refresh intervals when the memory devices are at different temperatures.

FIG. 10B is an X-Y plot of estimated average interval of refresh requests versus temperature, according to another embodiment of the present invention. Referring to fig. 10A and 10B, the temperature sensing circuit 20 provides different average refresh intervals every 10 ℃ in a temperature range of 20 ℃ to 80 ℃ to achieve high refresh interval resolution. In other words, the temperature sensing circuit 20 can dynamically adjust the ratio of the refresh pulse count [16] to the refresh pulse count [1] in the whole period according to the memory temperature, so as to adjust the average refresh interval, thereby improving the resolution of the average refresh interval to the temperature. The current consumption can be further reduced since no more selection circuits, counters and temperature sensors (not shown) need to be added for multi-temperature step-wise control.

Fig. 11A is a table of average interval statistics for estimated refresh requests, according to yet another embodiment of the present invention. FIG. 11B is an X-Y plot of estimated average interval of refresh requests versus temperature, in accordance with yet another embodiment of the present invention. Referring to fig. 11A and 11B, the difference between fig. 6A, 6B, 10A and 10B is that the step (step) between the default temperatures of the temperature sensing circuit 10 or the temperature sensing circuit 20 in fig. 11A and 11B is adjustable instead of fixing the step to 10 ℃. In yet another embodiment, a smaller step may be used, for example, at a temperature near room temperature, for example, 5 ℃, and a higher average refresh interval to temperature resolution may be obtained near room temperature. For example, as shown in fig. 11A and 11B, in yet another embodiment, the temperature is only 5 ℃ in steps between 30 ℃ and 50 ℃, while the temperature is greater than 5 ℃ in steps outside 30 ℃ and 50 ℃, it is obvious that the resolution of the average refresh interval versus temperature is improved between 30 ℃ and 50 ℃. That is, the present invention may also make the resolution of the average refresh interval of the refresh request signal REFREQ different at different temperatures by adjusting the step between the plurality of default temperature voltages VT 20-VT 80 of the temperature sensing circuit 10 or the temperature sensing circuit 20. In other words, the resolution may be non-uniform, so that the present invention may vary the resolution of a particular temperature interval without a change in the number of circuit components.

FIG. 12 is a flow chart of a method of operating a temperature sensing circuit according to an embodiment of the invention. Referring to fig. 12, in step S1210, the oscillator 110 provides an oscillation signal OSC. In step S1220, the counting circuit 120 counts the oscillation signal OSC to generate the count signal cnt_1, and the counting circuit 120 generates the count signal cnt_n. Next, in step S1230, the control circuit 130 performs a logic operation on the count signal cnt_n to generate the enable signal EN and the sensing adjustment signal ST. In step S1240, the sensing circuit 140 divides the reference voltage VREF according to the sensing adjustment signal ST to generate the reference temperature voltage VRT, compares the reference temperature voltage VRT with the monitor voltage VMON according to the logic level of the enable signal EN, and generates the determination signal DET according to the comparison result. In step S1250, the selecting circuit 150 dynamically selects one of the oscillation signal OSC and the count signal cnt_1 according to the determination signal DET, and generates a pulse of the refresh request signal REFREQ according to the dynamically selected one of the oscillation signal OSC and the count signal cnt_1.

In summary, the temperature sensing circuit and the sensing method thereof of the present invention can dynamically adjust the average refresh interval of the refresh request signal to improve the resolution of the average refresh interval to the temperature. The invention adjusts the proportion of the refresh pulse with different refresh intervals in the whole period by dynamically selecting the oscillation signal and the counting signal, thereby adjusting the average refresh interval and further improving the resolution of the average refresh interval to temperature. Since the multi-temperature gradual control is not needed to be performed by adding more selection circuits, counters and temperature sensors, the current consumption can be further reduced, and the frequency of the oscillating signal is not needed to be increased. In addition, according to an embodiment of the present invention, the resolution of the average refresh interval to the temperature may be configured unevenly, so as to improve the resolution to the target temperature region.

Those skilled in the art will appreciate that various modifications and changes may be made to the structures of the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

Claims

1. A temperature sensing circuit suitable for use in a memory device, comprising:

an oscillator for providing an oscillation signal;

the counting circuit is coupled with the oscillator and used for counting the oscillating signal to generate a first counting signal and generating a second counting signal;

the control circuit is coupled with the counting circuit and used for carrying out logic operation on the second counting signal to generate an enabling signal and a sensing adjustment signal;

the sensing circuit is coupled with the control circuit, divides the reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and compares the reference temperature voltage with the monitoring voltage according to the enabling signal to generate a decision signal; and

a selection circuit coupled to the oscillator, the counting circuit and the sensing circuit, the selection circuit dynamically selecting one of the oscillation signal and the first counting signal according to the determination signal and generating a pulse of a refresh request signal according to the dynamically selected one of the oscillation signal and the first counting signal,

wherein the sensing circuit comprises:

the voltage dividing circuit is provided with a plurality of voltage dividing resistors connected in series, and the voltage dividing resistors connected in series are coupled with the reference voltage and generate a plurality of default temperature voltages by dividing the reference voltage;

a switch string coupled to the control circuit and the voltage dividing circuit, having a plurality of switches, wherein a first end of each of the plurality of switches receives one of a plurality of default temperature voltages, and second ends of all of the plurality of switches are coupled to each other, and the switch string turns on one of the plurality of switches according to the sensing adjustment signal to generate the reference temperature voltage;

a monitor voltage generating circuit for providing the monitor voltage;

the comparator is coupled with the switch string and the monitoring voltage generating circuit and is used for determining whether to compare the reference temperature voltage with the monitoring voltage according to the enabling signal so as to generate a compared voltage;

a latch coupled to the comparator for determining whether to latch the compared voltage according to the enable signal to generate a determination signal,

wherein the selection circuit comprises:

a first selector coupled between the oscillator and the sensing circuit; and

a second selector coupled between the counting circuit and the sensing circuit,

the first selector and the second selector are alternately activated according to the logic level of the decision signal to jointly generate the refresh request signal.

2. The temperature sensing circuit of claim 1, wherein the counting circuit comprises:

a first counter coupled to the oscillator for receiving the oscillation signal and counting the number of pulses of the oscillation signal to generate a third counting signal;

a second counter coupled between the first counter and the selection circuit for receiving the third counting signal and counting the pulse number of the third counting signal to generate the first counting signal; and

and the third counter is used for receiving the oscillation signal and counting the pulse number of the oscillation signal to generate the second counting signal.

3. The temperature sensing circuit of claim 1, wherein the control circuit enables the enable signal whenever the control circuit detects that the number of pulses of the oscillating signal is equal to a first preset number in accordance with the second count signal.

4. The temperature sensing circuit of claim 1, wherein the control circuit logically converts the second count signal according to a default conversion table to generate the sensing adjustment signal, wherein the logic value of the sensing adjustment signal corresponds to a plurality of default temperature voltages of the memory device.

5. The temperature sensing circuit of claim 1, wherein the monitor voltage generation circuit comprises:

the constant current source is used for providing constant current; and

the diode is coupled with the constant current source and used for generating the monitoring voltage according to the constant current.

6. The temperature sensing circuit of claim 1, wherein the first selector outputs a pulse of the oscillation signal and the second selector does not output a signal when the decision signal is enabled, and the second selector outputs a pulse of the first count signal and the first selector does not output a signal when the decision signal is disabled to collectively generate the refresh request signal.

7. The temperature sensing circuit of claim 4, wherein the resolution of the average refresh interval of the refresh request signal at different temperatures is varied by adjusting the step between the plurality of default temperature voltages.

8. A sensing method for a memory device having a temperature sensing circuit with an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit, the sensing method comprising:

providing an oscillating signal with the oscillator;

counting the oscillation signals by the counting circuit to generate a first counting signal and a second counting signal;

performing logic operation on the second counting signal by using the control circuit to generate an enabling signal and a sensing adjustment signal;

dividing a reference voltage by the sensing circuit according to the sensing adjustment signal to generate a reference temperature voltage, and comparing the reference temperature voltage with a monitoring voltage according to the enabling signal to generate a determination signal; and

dynamically selecting one of the oscillation signal and the first count signal by the selection circuit according to the decision signal, generating a pulse of a refresh request signal according to the dynamically selected one of the oscillation signal and the first count signal,

the control circuit performs logic conversion on the second count signal according to a default conversion table to generate the sensing adjustment signal, wherein the logic value of the sensing adjustment signal corresponds to a plurality of default temperatures of the storage device;

the step of generating a reference temperature voltage according to the sensing adjustment signal and comparing the reference temperature voltage with a monitor voltage according to the enable signal to generate a determination signal comprises the following steps:

turning on one of the switches in the sensing circuit according to the sensing adjustment signal, and generating the reference temperature voltage by dividing the reference voltage;

providing the monitor voltage;

determining whether to compare the reference temperature voltage with the monitor voltage according to the enable signal to generate a compared voltage; and

latching the compared voltages to generate a decision signal;

the selection circuit comprises a first selector and a second selector, and the first selector and the second selector are alternately started according to the logic level of the decision signal so as to jointly generate the refresh request signal.

9. The sensing method of claim 8, wherein the step of counting the oscillation signals to generate a first count signal and generating a second count signal comprises:

receiving the oscillation signal and counting the pulse number of the oscillation signal to generate a third counting signal;

receiving the third counting signal and counting the pulse number of the third counting signal to generate the first counting signal; and

the oscillation signal is received and the number of pulses of the oscillation signal is counted to generate the second count signal.

10. The sensing method of claim 8, wherein the control circuit enables the enable signal whenever the control circuit detects that the number of pulses of the oscillation signal is equal to a first preset number according to the second count signal.

11. The sensing method of claim 8, wherein the step of providing the monitor voltage comprises:

providing a constant current; and

and generating the monitoring voltage according to the constant current.

12. The sensing method of claim 8, wherein the first selector outputs a pulse of the oscillation signal and the second selector does not output a signal when the decision signal is enabled, and the second selector outputs a pulse of the first count signal and the first selector does not output a signal when the decision signal is disabled to collectively generate the refresh request signal.

13. The sensing method of claim 8, wherein the resolution of the average refresh interval of the refresh request signal at different temperatures is varied by adjusting the step between the plurality of default temperature voltages.