CN113467591B - Composite signal reset circuit, method and server - Google Patents
Composite signal reset circuit, method and server Download PDFInfo
- Publication number
- CN113467591B CN113467591B CN202110775070.4A CN202110775070A CN113467591B CN 113467591 B CN113467591 B CN 113467591B CN 202110775070 A CN202110775070 A CN 202110775070A CN 113467591 B CN113467591 B CN 113467591B
- Authority
- CN
- China
- Prior art keywords
- signal
- reset
- circuit
- signal input
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a composite signal reset circuit, a method and a server, wherein the reset circuit comprises a first signal input circuit for acquiring a first reset signal and a second signal input circuit for acquiring a second reset signal, and the output end of the first signal input circuit is electrically connected with the output end of the second signal input circuit to form a target reset signal output end; a signal input end of the second signal input circuit is provided with a differential circuit; when the server needs to generate a target reset signal according to the first reset signal and the second reset signal, if the second reset signal is abnormal (continuously kept at a high level or a low level), the second reset signal is shielded by the differentiating circuit arranged at the signal input end of the second signal input circuit, so that the server can be reset independently according to the first reset signal without being influenced by the abnormal second reset signal, and further the server can work normally.
Description
Technical Field
The invention relates to the technical field of reset circuits, in particular to a composite signal reset circuit, a method and a server.
Background
A reset circuit belongs to a basic part of a hardware circuit architecture, particularly for a server with a main control system and a programmable control system, the reset circuit generally resets according to two signals, such as a server with a programmable logic Controller (CPLD) and a board controller (BMC), and the reset circuit resets the server according to the comprehensive action of a power-on reset signal and an active reset signal sent by the CPLD, namely, the power-on reset signal and an active reset signal line sent by the CPLD and a target reset signal is generated later. In use, for such a reset circuit, the following disadvantages exist: when the CPLD is hung up or the CPLD software is blocked during upgrading, the CPLD can be randomly kept at a high level or a low level, if the CPLD is at the high level, a target reset signal can be always kept at the low level state, the reset cannot be completed, and the BMC cannot work, so that the whole server system with the CPLD cannot work, the FW (firmware, program written in the CPLD) of the CPLD cannot be upgraded again, and a user more hopes that the BMC can work normally when the CPLD is abnormal, so that the upgrading work of the CPLD can be carried out from new.
Disclosure of Invention
The present invention provides a composite signal reset circuit, a method and a server, which can perform normal reset according to other reset signals when one of the reset signals is abnormal.
In order to achieve the above object, the present invention discloses a composite signal reset circuit, which includes a first signal input circuit and a second signal input circuit, wherein the first signal input circuit is used for collecting a first reset signal, the second signal input circuit is used for collecting a second reset signal, and an output end of the first signal input circuit is electrically connected with an output end of the second signal input circuit to form a target reset signal output end; and a signal input end of the second signal input circuit is provided with a differential circuit.
Preferably, the differentiating circuit includes a capacitor and an operational amplifier connected in series.
Preferably, the capacitor is 0.8-2 uF, and the feedback resistance between the output end and the inverting input end of the operational amplifier is 0.8-1.5 Komega.
Preferably, the second signal input circuit further includes a first switch tube electrically connected to the output terminal of the operational amplifier.
Preferably, the first signal input circuit includes a second switching tube and a third switching tube, and both the second switching tube and the third switching tube are reverse output switching elements; the control end of the second switch tube is electrically connected with the signal input end and is used for receiving the first reset signal; the output end of the second switching tube is electrically connected with the control end of the third switching tube, and the output end of the third switching tube is electrically connected with the output end of the first signal input circuit.
Preferably, the first reset signal is a power reset signal, and the second reset signal is a reset signal output by the programmable controller.
Preferably, the first switch tube is a triode.
The invention also discloses a composite signal resetting method, which comprises the following steps:
collecting two reset signals in real time, wherein the two reset signals are a first reset signal and a second reset signal respectively;
judging whether the second reset signal is a state change waveform signal or not, if so, performing line and logic operation on the first reset signal and the second reset signal and outputting the first reset signal and the second reset signal to obtain a target reset signal; if not, the second reset signal is shielded, and the target reset signal is output according to the first reset signal.
Preferably, the second reset signal is acquired through a second signal input circuit, and a differentiating circuit for performing judgment processing on the second reset signal is arranged in the second signal input circuit.
The invention also discloses a server, which comprises a main body, wherein a system mainboard is arranged in the main body, a main control system, a programmable control system and the composite signal reset circuit are arranged on the system mainboard, the first signal input circuit is electrically connected with the main control system, and the second signal input circuit is electrically connected with the programmable control system.
Compared with the prior art, the server adopting the composite signal reset circuit has the beneficial technical effects that: when the server needs to comprehensively generate a target reset signal according to two paths of reset signals, namely a first reset signal generated by a main control system (BMC) and a second reset signal generated by a programmable logic Controller (CPLD), if the second reset signal is abnormal (continuously kept at a high level or a low level), the second reset signal is shielded by a differential circuit arranged at a signal input end of a second signal input circuit, so that the server can be reset independently according to the first reset signal without being influenced by the abnormal second reset signal, the BMC can normally work, and the upgrading work of the CPLD can be carried out newly.
Drawings
Fig. 1 is a schematic diagram of a composite signal resetting method according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a composite signal reset circuit according to an embodiment of the present invention.
FIG. 3 is a graph of the differential circuit impulse response in an embodiment of the present invention.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
The embodiment discloses a server, which comprises a main body, wherein a system mainboard is arranged in the main body, a main control system (BMC) and a programmable logic device (CPLD) are arranged on the system mainboard, the BMC and the CPLD can both send reset signals, the server resets according to the composite reset signals of the BMC and the CPLD, and in order to prevent the BMC from not working normally when the CPLD is abnormal (such as upgrading and hanging up), the server is reset by adopting the composite reset method.
As shown in fig. 1, the composite reset method includes:
the method comprises the steps that two reset signals, namely a first reset signal and a second reset signal, are collected in real time, and for the server, the first reset signal is sent out by a BMC, and the second reset signal is sent out by a CPLD;
judging whether the second reset signal is a state change waveform signal, namely whether the second reset signal is in a high-low level change state, if so, performing line and logic operation on the first reset signal and the second reset signal and outputting the first reset signal and the second reset signal to obtain a target reset signal, and resetting the server through the target reset signal; if not, the second reset signal is shielded, and the target reset signal is output according to the first reset signal.
The following specifically describes the working principle of the server adopting the composite reset method:
when the last power supply of the power supply power-on sequence of the server is normally output, the BMC outputs a first reset signal ALL _ PWR _ GOOD signal, the second reset signal is a CPLD _ RST signal actively sent by the CPLD, the target reset signal is an IC _ RST _ N signal with effective low level, and when the ALL _ PWR _ GOOD signal and the CPLD _ RST signal are in a normal state, the IC _ RST _ N signal for resetting the server is generated by performing line and logic operation on the ALL _ PWR _ GOOD signal and the CPLD _ RST signal. When the CPLD fails to upgrade and enters a hang-up state, the CPLD _ RST signal is abnormal, which makes the BMC inoperable, and further causes that the FW (firmware, program written in the CPLD) of the CPLD cannot be upgraded again.
As shown in fig. 2, in order to effectively implement the above-mentioned reset method, the present invention further discloses a composite signal reset circuit, which includes two signal input circuits, namely a first signal input circuit 10 and a second signal input circuit 20, wherein the first signal input circuit 10 is used for collecting a first reset signal, the second signal input circuit 20 is used for collecting a second reset signal, and an output terminal of the first signal input circuit 10 is electrically connected to an output terminal of the second signal input circuit 20 to form a target reset signal output terminal OUT. The signal input terminal of the second signal input circuit 20 is provided with a differential circuit CW. By this differentiating circuit CW, only the instant when the input waveform of the second reset signal abruptly changes is outputted, and no output is outputted to the constant portion, thereby forming a mask to the constant portion. For the server in the above embodiment, the first signal input circuit 10 is electrically connected to the main control system, and the second signal input circuit 20 is electrically connected to the programmable control system.
Specifically, the differential circuit CW includes a capacitor C1 and an operational amplifier U1 connected in series, thereby constituting an operational amplifier differential circuit. The capacitor C1 is electrically connected to the signal input terminal IN2 for receiving a second reset signal. Referring to fig. 3, as can be seen from the impulse response diagram of the operational amplifier differential circuit CW, when the CPLD actively resets the server, the CPLD sends a CPLD _ RST signal (pulse signal), and the CPLD _ RST signal resets the server after passing through the differential circuit CW. When the CPLD is suspended, the CPLD _ RST signal is at a fixed level, and the capacitor C1 plays a role in isolation, so that the output of the operational amplifier U1 is zero, and the shielding of the CPLD _ RST signal is completed. More specifically, the capacitor C1 is 0.8 to 2uF, and the feedback resistor R6 between the output terminal and the inverting input terminal of the operational amplifier U1 is 0.8 to 1.5K Ω, and in this embodiment, the capacitor C1 is preferably 1uF, and the feedback resistor R6 is preferably 1K Ω. It should be noted that those skilled in the art may also make adjustments to the configuration of the differential circuit CW, such as using an RC element to configure the differential circuit CW.
Further, as shown in fig. 2, the second signal input circuit 20 further includes a first switch Q1 electrically connected to the output terminal of the operational amplifier U1. In this embodiment, the first switch tube Q1 is an NPN type triode, the output terminal of the operational amplifier U1 is electrically connected to the base of the first switch tube Q1, the emitter of the first switch tube Q1 is grounded, the collector is an output terminal, and the first switch tube Q1 is electrically connected to the output terminal of the first signal input circuit 10. Specifically, the operational amplifier UI is electrically connected to the first switch Q1 through a current limiting resistor R5.
Further, referring to fig. 2 again, for the first signal input circuit 10, it includes a second switch Q2 and a third switch Q3, the second switch Q2 and the third switch Q3 are all inverse output switch devices, that is, the output level state is opposite to the input level state, when the input bit is low level, the output is high level, when the input bit is high level, the output is low level. The control end of the second switch tube Q2 is electrically connected to the signal input end IN1 for receiving the first reset signal. The output end of the second switch tube Q2 is electrically connected to the control end of the third switch tube Q3, specifically, a current limiting resistor R1 is arranged between the second switch tube Q2 and the third switch tube Q3, and a current limiting resistor R3 is arranged between the second switch tube Q2 and the signal input end IN 1. The output terminal of the third switching tube Q3 is electrically connected to the output terminal of the first signal input circuit 10. In this embodiment, the second switching tube Q2 and the third switching tube Q3 are both N-channel MOS tubes, a voltage source VCC1 is disposed between the gates and the sources of the second switching tube Q2 and the third switching tube Q3, and the voltage source VCC1 is electrically connected to the gates of the second switching tube Q2 and the third switching tube Q3 through current-limiting resistors R4 and R2, respectively. In addition, the target reset signal output end OUT is also electrically connected with a voltage source VCC2, and the voltage source VCC2 is electrically connected with the target reset signal output end OUT through a current limiting resistor R7.
Through the series design of the second switching tube Q2 and the third switching tube Q3, the high level of the first reset signal is effective, and therefore when the first reset signal is a power supply power-on completion signal, the automatic reset of power supply power-on completion can be effectively guaranteed.
In summary, as shown in fig. 1 to fig. 3, the working process of the composite signal reset circuit disclosed in the above embodiment is as follows: when the power-on sequence in the server is completed, the ALL _ PWR _ GOOD signal is at a high level, and the ALL _ PWR _ GOOD signal changes to a low level after passing through the second switching tube Q2 and changes to a high level again after passing through the third switching tube Q3. When the CPLD is actively reset, a CPLD _ RST signal (200 ms low level pulse) is sent out, and the CPLD _ RST signal passes through the differential circuit CW and then turns on the first switch tube Q1, so that from the falling edge of the CPLD _ RST signal, the first switch tube Q1 outputs a low level to pull down the IC _ RST _ N signal, and then, at the rising edge of the CPLD _ RST signal, the first switch tube Q1 outputs a high level to complete the reset action. When the CPLD is abnormal, the CPLD _ RST signal is continuously in a high level, and the first switch tube Q1 cannot be started through the differential circuit CW, so that the server can be normally reset under the action of the ALL _ PWR _ GOOD signal, and the normal work of the BMC is ensured.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, therefore, the present invention is not limited by the appended claims.
Claims (10)
1. A composite signal reset circuit is characterized by comprising a first signal input circuit and a second signal input circuit, wherein the first signal input circuit is used for acquiring a first reset signal, the second signal input circuit is used for acquiring a second reset signal, and the output end of the first signal input circuit is electrically connected with the output end of the second signal input circuit to form a target reset signal output end; and a signal input end of the second signal input circuit is provided with a differential circuit, and the differential circuit is used for isolating signals in a fixed level state.
2. The composite signal reset circuit of claim 1, wherein the differentiating circuit comprises a capacitor and an operational amplifier connected in series.
3. The composite signal reset circuit of claim 2, wherein the capacitor is 0.8-2 uF, and the feedback resistance between the output terminal and the inverting input terminal of the operational amplifier is 0.8-1.5K Ω.
4. The composite signal reset circuit of claim 2, wherein the second signal input circuit further comprises a first switch transistor electrically connected to the output of the operational amplifier.
5. The composite signal reset circuit according to claim 1, wherein the first signal input circuit comprises a second switching tube and a third switching tube, and the second switching tube and the third switching tube are both inverted output switching elements; the control end of the second switch tube is electrically connected with the signal input end and is used for receiving the first reset signal; the output end of the second switching tube is electrically connected with the control end of the third switching tube, and the output end of the third switching tube is electrically connected with the output end of the first signal input circuit.
6. The composite signal reset circuit of claim 1, wherein the first reset signal is a power supply reset signal and the second reset signal is a reset signal output by a programmable controller.
7. The composite signal reset circuit of claim 4, wherein the first switch transistor is a triode.
8. A composite signal reset method, comprising:
acquiring a first reset signal and a second reset signal in real time;
judging whether the second reset signal is a state change waveform signal or not, if so,
performing a wired and logical operation on the first reset signal and the second reset signal and outputting the result to obtain a target reset signal; if the result is no, then,
the second reset signal is masked and the target reset signal is output according to the first reset signal.
9. The composite signal resetting method according to claim 8, wherein the second reset signal is acquired by a second signal input circuit, and a differentiating circuit for performing determination processing on the second reset signal is provided in the second signal input circuit.
10. A server, comprising a main body, wherein a system main board is disposed in the main body, a main control system and a programmable control system are disposed on the system main board, and the composite signal reset circuit according to any one of claims 1 to 7, the first signal input circuit is electrically connected to the main control system, and the second signal input circuit is electrically connected to the programmable control system.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110775070.4A CN113467591B (en) | 2021-07-08 | 2021-07-08 | Composite signal reset circuit, method and server |
| PCT/CN2021/129247 WO2023279606A1 (en) | 2021-07-08 | 2021-11-08 | Composite signal reset circuit and method, and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110775070.4A CN113467591B (en) | 2021-07-08 | 2021-07-08 | Composite signal reset circuit, method and server |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113467591A CN113467591A (en) | 2021-10-01 |
| CN113467591B true CN113467591B (en) | 2023-04-11 |
Family
ID=77879243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110775070.4A Active CN113467591B (en) | 2021-07-08 | 2021-07-08 | Composite signal reset circuit, method and server |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113467591B (en) |
| WO (1) | WO2023279606A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113467591B (en) * | 2021-07-08 | 2023-04-11 | 南昌华勤电子科技有限公司 | Composite signal reset circuit, method and server |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6449444A (en) * | 1987-08-20 | 1989-02-23 | Oki Electric Ind Co Ltd | Reset signal discrimination circuit |
| CN1781066A (en) * | 2003-04-25 | 2006-05-31 | 日本电气株式会社 | Reset circuit and digital communication apparatus |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008288950A (en) * | 2007-05-18 | 2008-11-27 | Elpida Memory Inc | Reset pulse generating circuit |
| CN103023463B (en) * | 2012-11-27 | 2016-01-13 | 华为技术有限公司 | A kind of ramp signal generative circuit and ramp signal generator |
| JP2015154437A (en) * | 2014-02-19 | 2015-08-24 | 株式会社東芝 | power-on reset circuit |
| CN106849920A (en) * | 2017-02-16 | 2017-06-13 | 中国人民解放军国防科学技术大学 | A kind of repositioning method, reset signal output circuit and reset system |
| CN107846208A (en) * | 2017-09-30 | 2018-03-27 | 深圳市艾特智能科技有限公司 | Stabilization reset circuit |
| CN109669524B (en) * | 2018-12-14 | 2020-06-05 | 上海贝岭股份有限公司 | Power-on reset circuit of chip |
| CN110690883A (en) * | 2019-10-28 | 2020-01-14 | 无锡闻泰信息技术有限公司 | EC reset circuit and electronic equipment based on composite signal |
| CN110890879A (en) * | 2019-12-02 | 2020-03-17 | 江苏嘉擎信息技术有限公司 | Mainboard virtual switch circuit and working method thereof |
| CN212435663U (en) * | 2020-05-07 | 2021-01-29 | 深圳市理邦精密仪器股份有限公司 | Reset circuit and reset system |
| CN111736678B (en) * | 2020-06-12 | 2022-06-10 | 浪潮(北京)电子信息产业有限公司 | Chip reset circuit, method and equipment |
| CN111781872A (en) * | 2020-06-30 | 2020-10-16 | 山东信通电子股份有限公司 | Power-on reset circuit and method of chip |
| CN113054966B (en) * | 2021-03-15 | 2021-09-24 | 上海物骐微电子有限公司 | Low-power consumption state control circuit |
| CN113467591B (en) * | 2021-07-08 | 2023-04-11 | 南昌华勤电子科技有限公司 | Composite signal reset circuit, method and server |
-
2021
- 2021-07-08 CN CN202110775070.4A patent/CN113467591B/en active Active
- 2021-11-08 WO PCT/CN2021/129247 patent/WO2023279606A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6449444A (en) * | 1987-08-20 | 1989-02-23 | Oki Electric Ind Co Ltd | Reset signal discrimination circuit |
| CN1781066A (en) * | 2003-04-25 | 2006-05-31 | 日本电气株式会社 | Reset circuit and digital communication apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113467591A (en) | 2021-10-01 |
| WO2023279606A1 (en) | 2023-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113467591B (en) | Composite signal reset circuit, method and server | |
| US10649820B2 (en) | Method of managing event generation for an industrial controller | |
| CN106610712B (en) | Substrate management controller resetting system and method | |
| CN111736678B (en) | Chip reset circuit, method and equipment | |
| US10719106B2 (en) | Factory reset apparatus and method | |
| US9797947B2 (en) | Arrangement for selective enabling of a debugging interface | |
| TWI592872B (en) | Server and firmware updating method thereof | |
| CN107357619B (en) | Method, device, equipment and storage medium for generating card configuration file | |
| US20090323241A1 (en) | Input Protection Method with Variable Tripping Threshold and Low Parasitic Elements | |
| CN109408151B (en) | Automatic switching device and switching method for configuration mode of field programmable gate array | |
| CN202887168U (en) | Watchdog circuit suitable for unattended operation device | |
| WO2016061959A1 (en) | Undervoltage protection circuit processing method and apparatus, and undervoltage protection system | |
| CN106936891B (en) | Remote touch control monitoring system and controlled device thereof, monitoring device and control method thereof | |
| CN217787755U (en) | Combined reset device based on watchdog | |
| JP2002063080A (en) | Interface device | |
| CN111611768B (en) | Method and device for monitoring clock signals | |
| CN219436968U (en) | IGBT driving pulse protection circuit | |
| US20180032461A1 (en) | Control circuit board, micro-server, control system and control method thereof | |
| CN111382101B (en) | Communication bus circuit, communication bus and master-slave communication system | |
| JP6060775B2 (en) | Reset circuit | |
| TW201928703A (en) | Server system | |
| DE102013106697B3 (en) | Motherboard for a computer system, in particular for a desktop PC, and a computer system | |
| JP2893876B2 (en) | Digital signal processing circuit | |
| CN106843778A (en) | Display automatic switchover system and its method | |
| DE102021116541A1 (en) | Device for controlling a household appliance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |