CN113466649B

CN113466649B - Method for judging failure reason of SiC MOSFET in surge current test

Info

Publication number: CN113466649B
Application number: CN202110732566.3A
Authority: CN
Inventors: 王振宇; 李运甲; 孙晓华; 金吉振; 窦伟滔; 王毓柱; 朱郑允; 郭清; 刘晔
Original assignee: Zhejiang University ZJU; Xian Jiaotong University
Current assignee: Zhejiang University ZJU; Xian Jiaotong University
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2022-10-25
Anticipated expiration: 2041-06-29
Also published as: CN113466649A

Abstract

The invention discloses a method for judging failure reasons of SiC MOSFET in surge current test, wherein in high-power converters such as motor drivers and grid-connected systems, the SiC power MOSFET and a body diode thereof are likely to suffer from the impact of large surge current, and the surge current capability and surge current reliability of the SiC power MOSFET need to be researched and the failure reasons thereof need to be judged. The failure reason of the SiC MOSFET in the surge current test is mainly judged by means of failure observation after the device is unpacked, and a judgment method related to electrical performance is lacked. The invention provides a method for judging failure reasons possibly existing in a positive gate bias surge current test of a SiC MOSFET, which is related to electrical performance, can judge the failure reasons of the SiC MOSFET according to the change rule of the surge voltage waveform in the surge current test, verifies the failure reasons of a device by comparing the maximum surge current capacity, avoids deblocking observation of the device, reduces the workload, is beneficial to understanding the failure process of the device, and supplements the reliability research of the SiC MOSFET.

Description

Method for judging failure reason of SiC MOSFET in surge current test

Technical Field

The invention belongs to the field of SiC power semiconductor devices, and particularly relates to a method for judging the failure reason of a SiC MOSFET in a surge current test.

Background

Compared with a semiconductor Si material, the wide-bandgap semiconductor SiC has more excellent material characteristics such as larger forbidden bandwidth (3 times of Si), higher thermal conductivity (3 times of Si), high critical breakdown field strength (10 times of Si), higher electron saturation velocity (2 times of Si) and the like, has stronger temperature resistance, radiation resistance, heat dissipation and pressure resistance, is higher in applicable frequency, and is widely applied to power electronic systems with high power density and high conversion efficiency. In power electronic application, if the parasitic anti-parallel PIN body diode inside the SiC MOSFET is directly used, rather than additionally adding an anti-parallel SiC SBD, the chip cost and the volume of a power assembly module can be greatly reduced, and the EMI characteristic of a system is improved.

In high-power converters such as motor drivers and grid-connected systems, the SiC power MOSFET and its body diode may be subjected to impact of large surge current, and it is necessary to study the surge current capability and surge current reliability of the SiC power MOSFET and determine the cause of failure thereof.

The failure reasons of the SiC MOSFET in the surge current test can be summarized as gate oxide layer failure and package failure caused by aluminum melting, but at present, researches on the failure reasons of the SiC MOSFET in the surge current test mainly focus on package failure, reports on the failure of the gate oxide layer of the SiC MOSFET in the surge current test are few, the failure reasons are mainly judged by means of failure observation after the device is unpacked, and a judgment method related to electrical performance is lacked.

Disclosure of Invention

The invention provides a method for judging the possible failure reason of a SiC MOSFET in a positive gate bias surge current test, which is related to electrical performance. The failure reason of the SiC MOSFET can be judged according to the change rule of the surge voltage waveform in the surge current test, the failure reason of the device can be verified by comparing the maximum surge current capability, the decapsulation observation of the device is avoided, the workload is reduced, the failure process of the device is favorably known, and the reliability research of the SiC MOSFET is supplemented.

In order to achieve the purpose, the invention provides the following technical scheme:

1. gate voltage V _GS A fixed value within 15 to 20V was set, and a surge current was applied to the SiC MOSFET from the source to the drain, and the corresponding surge voltage waveform was recorded. And gradually increasing the peak value of the surge current to test, and recording the waveform of the surge voltage in each test process until the device fails. And defining the surge current peak value when the device fails as the maximum surge current capacity of the device, and recording the maximum surge current capacity of the device.

2. Analyzing the change of a surge voltage waveform in the positive gate bias surge current testing process, and judging that the device is subjected to packaging failure due to aluminum melting if the surge voltage waveform has obvious peak voltage before the device fails and the position of the peak voltage gradually moves to the upper left along with the surge test;

3. and analyzing the change of the surge voltage waveform in the positive gate bias surge current test process, and judging that the device fails due to gate oxide breakdown if the surge voltage waveform does not have peak voltage before the device fails.

4. Gate voltage V _GS And setting the value to be a certain fixed value within-5 to-1V, carrying out surge current test on SiC MOSFETs of the same type until the device fails, and recording the maximum surge current capability of the device.

5. And comparing the maximum surge current capability of the device in the positive gate bias surge current test and the negative gate bias surge current test, and verifying the judgment of the failure reason of the device. According to prior studies, siC MOSFETs suffer package failures due to aluminum melting during negative gate bias testing. If the maximum surge current capability of the device in the positive gate bias surge current test is similar to that in the negative gate bias surge current test (not more than 10%), verifying that the device in the positive gate bias surge current test is subjected to packaging failure due to aluminum melting; if the maximum surge current capability of the device in the positive gate bias surge current test is obviously smaller than that in the negative gate bias surge current test (more than 10%), the device in the positive gate bias surge current test fails in advance due to gate oxide breakdown.

The invention has the advantages that: the failure reason of the SiC MOSFET can be judged according to the change rule of the surge voltage waveform in the surge current test, the decapsulation observation of the device is avoided, the workload is reduced, the failure process of the device is facilitated to be known, and the reliability research of the SiC MOSFET is supplemented.

Drawings

Fig. 1 is a schematic diagram of an inrush current test circuit.

Fig. 2 is a diagram illustrating an inrush current.

Fig. 3 shows the change of the surge voltage waveform of the class a device in the positive gate bias surge current test.

Fig. 4 shows the change of the surge voltage waveform of the B-type device in the positive gate bias surge current test.

Detailed Description

The present invention is a method for determining a failure cause of a SiC MOSFET in a surge current test, and a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

An embodiment comprises the steps of:

1) Fig. 1 is a schematic diagram of an inrush current test circuit according to the present invention, which is based on an LC oscillation method, and an LC resonant circuit including a capacitor and an inductor in fig. 1 generates an inrush current. The surge current generated by the circuit is a positive half cycle sinusoidal current pulse with a pulse width of 10ms, as shown in fig. 2, and the peak value of the surge current pulse can pass through a direct current voltage V _DC And (6) carrying out adjustment.

2) In the example, siC MOSFET commercial devices of two manufacturers are selected and numbered as A-type devices and B-type devices respectively. Gate voltage V _GS Set at 20V, and applied to SiC MOSFET from source to drainAnd adding surge current and recording corresponding surge voltage waveform. Gradually increasing the surge current peak value for testing until the device fails,

3) The surge voltage waveform during each test is recorded. The maximum surge current capability of the A-type device in a positive gate bias surge current test is 85A, and the maximum surge current capability of the B-type device in the positive gate bias surge current test is 64A.

4) Fig. 3 shows the change of the surge voltage waveform of a class-a device in a positive gate bias surge current test, before the device fails, the surge voltage waveform has obvious peak voltage, the position of the peak voltage gradually moves to the upper left along with the surge test, and the symmetry of the surge voltage waveform is poor. The peak voltage corresponds to the body diode starting voltage when the grid is positively biased, when the surge voltage value exceeds the body diode starting voltage, the body diode is also conducted on the basis of reverse channel conduction, and finally the device is subjected to packaging failure due to aluminum melting; fig. 4 shows the change of the surge voltage waveform of a class B device in a positive gate bias surge current test, and before the device fails, the peak voltage does not exist, and the symmetry of the surge voltage waveform is good. The reverse channel of the device is conductive, the body diode is not conductive all the time, and finally the device fails due to gate oxide breakdown.

5) Gate voltage V _GS And setting the voltage to be-5V, respectively carrying out surge current test on A, B devices until the devices fail, and recording the maximum surge current capability of the devices. The maximum surge current capacity of the A-type device in the negative gate bias surge current test is 86A, and the maximum surge current capacity of the B-type device in the positive gate bias surge current test is 100A. The maximum surge current capability of the A-type device in the positive gate bias surge current test is similar to that in the negative gate bias surge current test (not more than 10%), and the A-type device in the positive gate bias surge current test is verified to be subjected to packaging failure due to aluminum melting; the maximum surge current capability of the B-type device in the positive gate bias surge current test is obviously smaller than that in the negative gate bias surge current test (more than 10 percent), and the advanced failure of the B-type device in the positive gate bias surge current test due to the breakdown of a gate oxide is verified.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

In conclusion, the failure reason of the SiC MOSFET can be judged according to the change rule of the surge voltage waveform in the surge current test, the failure reason of the device can be verified by comparing the maximum surge current capability, the decapsulation observation of the device is avoided, the workload is reduced, the failure process of the device is facilitated to be known, and the reliability research of the SiC MOSFET is supplemented.

Claims

1. A method for judging failure reasons of a SiC MOSFET in surge current test is characterized in that the failure reasons of a device are judged according to a surge voltage waveform, and the method comprises the following steps:

1) Gate voltage V _GS Applying surge current to the SiC MOSFET from a source electrode to a drain electrode, recording corresponding surge voltage waveform, gradually increasing the surge current peak value for testing, recording the surge voltage waveform in each testing process until the device fails, defining the surge current peak value when the device fails as the maximum surge current capacity of the device, and recording the maximum surge current capacity of the device;

2) Analyzing the change of a surge voltage waveform in the positive gate bias surge current testing process, and judging that the device is subjected to packaging failure due to aluminum melting if the surge voltage waveform has obvious peak voltage before the device fails and the position of the peak voltage gradually moves to the upper left along with the surge test;

3) Analyzing the change of a surge voltage waveform in the positive gate bias surge current testing process, and judging that the device fails due to gate oxide breakdown if the surge voltage waveform does not have peak voltage before the device fails;

4) Gate voltage V _GS Setting the voltage to a certain fixed value within-5 to-1V, carrying out surge current test on SiC MOSFETs of the same type until the device fails, recording the maximum surge current capability of the device, and carrying out surge current test on the SiC MOSFETs of the same type until the device failsVerifying the judgment of the failure reason of the device according to the maximum surge current capability of the device in the positive gate bias surge current test and the negative gate bias surge current test;

5) If the maximum surge current capability of the device in the positive gate bias surge current test is close to that in the negative gate bias surge current test and is not more than 10 percent compared with the situation in the negative gate bias surge current test, the SiC MOSFET verifies that the device in the positive gate bias surge current test has packaging failure due to aluminum melting; if the maximum surge current capability of the device in the positive gate bias surge current test is obviously smaller than that in the negative gate bias surge current test and exceeds 10 percent, the device in the positive gate bias surge current test fails in advance due to gate oxide breakdown.

2. The method for judging the failure reason of the SiC MOSFET in the surge current test as claimed in claim 1, wherein the gate voltage V in the step 1) _GS Set at 15-20V.