CN1134600A

CN1134600A - Method and apparatus for fabricating thin-film transistors

Info

Publication number: CN1134600A
Application number: CN 96104073
Authority: CN
Inventors: 山崎舜平
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 1995-01-13
Filing date: 1996-01-12
Publication date: 1996-10-30

Abstract

To improve the characteristics and reliability of a thin film transistor having an active layer consisting of a silicon film crystallized using a catalyst element. A catalyst element, such as nickel, is added to an amorphous silicon film to anneal the film, whereby this film is crystallized at a temperature lower than the distortion temperature of a glass substrate to form an active layer of a TFT. N-type or P-type impurity ions are implanted in the film in a state that the layer is heated at 100 to 400 DEG C. As the layer is properly heated, the impurity ions are also activated on the spot, damage due to an ion-beam emission is immediately removed and a defect, a distortion and the like are not also left.

Description

Make the method and apparatus of thin-film transistor

The present invention relates to make the method for thin-film transistor (TFT), each thin-film transistor all has the semiconductive thin film that is different from monocrystalline.The invention still further relates to the used equipment of this thin-film transistor of making.The present invention be more particularly directed to the method and apparatus of implanted dopant, in order to producing n type or p type conduction region, with formation source/drain region etc.Promptly can be manufactured on the dielectric substrate that glass etc. makes by the TFT of manufacturing of the present invention, for example also can be manufactured on the Semiconductor substrate that constitutes by monocrystalline silicon.

In recent years, worked out the insulated gate semiconductor device that active layer (being also referred to as active area) arranged of the form of film on dielectric substrate.Specifically, worked out film shape gated transistor (being called TFT) veritably.These devices can be divided into non-crystalline silicon tft or silicon metal TFT by used semi-conductive material and crystalline state.It should be noted, silicon metal is on-monocrystalline,, can not think the monocrystalline attitude that is.

Usually, amorphous semiconductor has little field mobility, thereby it can not be as the TFT that requires high-speed cruising.And p type amorphous silicon has very little field mobility, and it can not be as making p-channel TFT (PMOSTFT).Thereby can not make the complementary MOS circuit of forming by p channel TFT and n channel TFT (CMOS).

On the other hand, crystal semiconductor has big field mobility than amorphous semiconductor, thereby can high-speed cruising.Therefore, can obtain NMOSTFT and PMOS TFT with silicon metal, thereby can be made into cmos circuit.Pointed out to wish that setting up LDD structure (light doping section) for example is used for single crystal semiconductor MOSIC, to obtain better characteristic.

Yet,, must make the amorphous silicon thermal annealing for obtaining crystal silicon semiconductor.For this purpose, silicon is being surpassed under 600 ℃ the high temperature through long heat treatment.Thereby, require stand-by substrate to have high maximum treatment temperature.Therefore, use expensive quartz substrate usually.

We have found can promote recrystallized amorphous silicon with catalytic elements such as nickel, iron, cobalt, platinum and palladium.As a result, we carry out thermal annealing under than low in the past temperature and in the short time, successfully obtained crystal silicon film.As a result, can use the inexpensive glass substrate of low maximum treatment temperature with this method for crystallising.

And, find that thermal annealing can be realized the activation of impurity element under low than before temperature.Particularly, make n type or p type foreign ion inject the silicon fiml that contains the catalytic elements that promotes crystallization.After this method formation doped region such as source/drain region, impurity element can activate under than the low temperature of temperature commonly used.For this purpose, the concentration range of desirable catalytic elements is 1 * 10 ¹⁵To 1 * 10 ¹⁹Atom/centimetre ³In the scope.

When concentration is lower than this scope, can not promote crystallization.When concentration is higher than this scope, the Si semiconductor characteristic there is adverse effect.In this case, measure the concentration of catalytic elements with SIMS (secondary ion mass spectroscopy analytic approach).In most of the cases, catalytic elements is represented the distribution in the film.Above-mentioned value is the minimum value of catalytic elements in the silicon fiml.

In the prior art,, require to use high light such as laser irradiation (photo-annealing) for activating dopant at low temperatures.Yet there are some serious problems in photo-annealing aspect repeatability and the controllability, and is difficult to produce in batches.Use to promote that the catalytic elements of crystallization is highly significant, in this, it is feasible making the low-temp activation that can compare with photo-annealing.

Yet, quicken crystallization with catalytic elements and cause new problem.Particularly when activating the impurity that injects with thermal annealing, catalytic elements moves and accumulates in the near interface between doped region (1 drain region, source) and the raceway groove.Interface between these raceway grooves and the source/drain region is the superfine little part among the TFT.Defective in these parts is greatly damaged the TFT characteristic.

More particularly, in these parts, be unfavorable for the concentration increase of the catalytic elements of Si semiconductor.This damage the TFT characteristic (be specifically when the voltage that adds on the grid be 0 or when negative leakage current (also claiming cut-off current) between source/leakages increase) and reliability (the TFT characteristic degenerates after the use for a long time).

With reference now to Fig. 4 (A), the mechanism that promotes the motion of crystallization catalytic elements is described to 4 (D).Fig. 4 (A) illustrates until the mechanism that constitutes the grid step.Prepare a substrate 1.On substrate 1, can form suitable resilient coating.On entire substrate 1, form island shape silicon area 2 (being also referred to as active layer).Afterwards, disclosing 244104/1994 disclosed technology with Japan Patent makes catalytic elements be evenly distributed in (Fig. 4 (A)) in the island shape silicon area 2 substantially.

Afterwards, for example inject or other method introducing impurity, as phosphorus with ion.As a result, form source region 5 and drain region 6.Yet ion injection meeting is in the source 5 and leak 6 and cause many defectives and distortion (Fig. 4 (B)).

Carry out thermal annealing and if then disclose 267989/1994 and 333951/1994 disclosed technology with Japan Patent, to activate the impurity that injects, the catalytic elements that exists 5 and 6 is moved, because catalytic elements is tended to preferentially to be located to capture by defective etc. towards source/drain region.As this move (Fig. 4 (C)) that when the temperature more than 400 ℃ is carried out thermal annealing, sees catalytic elements significantly.

The catalytic elements that moves concentrates on (the arrow indication) at the interface between raceway groove 7 and source/drain region 5 and 6 especially.Make catalytic elements lowering of concentration in the raceway groove 7.Subsequently, the catalytic elements at the interface between raceway groove 7 and source/drain region 5 and 6 is highly enriched.

Fig. 4 (D) is the depth profile of catalytic elements in the shape silicon area 2 of island.Dotted line schematically illustrates the situation of Fig. 4 (A), evenly mixes with catalytic elements in the silicon island district.On the other hand, solid line schematically illustrates the situation of Fig. 4 (C).Thermal annealing result, catalytic elements accumulate in the near interface between raceway groove 7 and source/drain region 5 and 6, and the high order of magnitude of its concentration ratio initial concentration is as the arrow indication.

The objective of the invention is, the method for a kind of TFT of manufacturing is provided, when making the silicon fiml crystallization with catalytic elements, it has good characteristic and good reliability, in order to address the above problem.

Another object of the present invention is that a kind of equipment that is used to make described TFT the last period is provided.

Obviously, the above-mentioned uneven distribution of catalytic elements is to cause the result who produces defective and distortion in the shape silicon area of island in the impurity injection process.So, use and neither produce the method for implanting that defective does not produce deformation yet.Report, if in the ion implantation step, substrate is heated to 200 ℃, can save so thermal annealing or other method make its activation (Y.Mishima etal J.Appl.Phys 74 (193,7114).

The present inventor has carried out this research, and finds, after ion injected, ion injection defective there and then was not repaired and can stays defective.And, if substrate is heated to 100 ℃ to 400 ℃, preferably 200 to 350 ℃, finish ion implantation technology, can not introduce defective in the silicon fiml.

Constitute the present invention by following mode.Disclose disclosed technology in 244104/1994,267989/1994 and 333951/1994 with Japan Patent, give to add the catalytic elements that promotes crystallization in the shape silicon area of island, constitute the silicon metal island-shaped area.The degree of depth of catalytic elements preferably 1 * 10 ¹⁵To 1 * 10 ¹⁹Atom/centimetre ³Concentration is higher than 1 * 10 ¹⁹Atom/centimetre ³, metallic character appears in silicon.As a result, overslaugh characteristic of semiconductor.

Measure the concentration of catalytic elements with SIMS (secondary ion mass spectroscopy analytic approach).As a rule, above-mentioned value is the minimum value of catalytic elements in the silicon fiml.

Afterwards,, inject or other method, introduce the impurity of generation type p or n conduction with ion 100 ℃ to 400 ℃ heated substrate.If hydrogen ion or halide ion (as fluorine or chlorine) are introduced with foreign ion, then can carry out more effective activation.

But heated substrate in the middle of ion injects.Another way, also can be just before ion injects heated substrate, in ion implantation process, can not have a mind to heated substrate.In this case, underlayer temperature is passed in time and is descended.Yet, heat insulationly in normal ion implantation technology, can keep 100 ℃ to 400 ℃ temperature by providing enough.

This class ion implantation device needs at least two chambers.There is lining heat a chamber, and another chamber need not be equipped with the device of any effective heated substrate.

Schematically be shown among Fig. 5 by injection device of the present invention.This equipment is mainly by three chambers, or first preparation room (substrate load chamber) 501, one flood chambers 502 and second preparation room 503, substrate relief chamber) constitute.Each chamber all has one to make the suitable mechanism of internal pressure.

The pedestal 504 of band heater is equipped with in first preparation room 501, is used for substrate 505 is heated to suitable temperature.It is identical with the conventional ion injection device that flood chamber 502 is designed to, and dopant gas drawing-in system 510 is arranged, pumped vacuum systems 511 and substrate clamp 506, plasma chamber 508 and the control electrode 509 that is used to quicken.Another substrate 507 is placed on the anchor clamps 506.From second preparation room 503, take out the substrate 512 after handling.

If first preparation room 501 is designed to loading and unloading substrate 505, then can save second preparation room 503.In first preparation room 501, substrate is heated to proper temperature.Important is not the temperature that in first preparation room 501 substrate is heated, but the temperature of the substrate 507 in the flood chamber 502 in the ion implantation technology process.Particularly importantly make the semiconductor region of doping remain on 100 to 400 ℃, preferably remain on 200 to 350 ℃.

Among the present invention, still can not cause defective, not occur distortion yet although inject silicon fiml through ion.As a result, avoided the catalytic elements gathering.

Need to carry out thermal annealing in the temperature more than 400 ℃ because some cause, ion are injected the back, ion injection back will can not stay defective at silicon fiml and also can not stay distortion.Therefore, the catalytic elements that exists in the raceway groove will can not move, thereby prevent that catalytic elements from accumulating between raceway groove and the source/leakage at the interface.So can keep the initial concentration of catalytic elements to distribute.

By following explanation, other purpose of the present invention and feature will be clear.

Fig. 1 (A)-1 (E) is the profile of TFT of the operation of the explanation embodiment of the invention 1.

Fig. 2 (A)-2 (E) is the profile of TFT of the operation of the explanation embodiment of the invention 2.

Fig. 3 (A)-3 (E) is the cross-sectional view of TFT of the operation of the explanation embodiment of the invention 3.

Fig. 4 (A)-4 (E) is the profile of TFT of the shifting principle of explanation catalytic elements.

Fig. 4 (D) is the concentration profile of catalytic elements in the district of silicon island shown in the presentation graphs 4 (A)-4 (C);

Fig. 5 is the ion implantation device skeleton diagram that the present invention uses;

Fig. 6 (A)-6 (E) and 7 (A)-7 (C) are the profiles of the operation of explanation example 4 of the present invention.

Fig. 8 (A)-8 (E) is the profile of the operation of explanation example 5 of the present invention.

Fig. 9 (A)-9 (E) is the profile of the operation of explanation example 6 of the present invention.

Embodiment 1

Fig. 1 (A)-1 (E) has illustrated present embodiment.At first, on Corning7059 glass substrate 101, form the silica buffer film 102 of thick 2000 with sputtering method.Then, form thick 200 to 1500 , for example the Intrinsical amorphous silicon film 103 of 500A with plasma-enhanced CVD (PCVD) method.In amorphous silicon film 103, the concentration of I type impurity (promptly, trivalent or pentavalent impurity) is 1 * 10 ¹⁵To 1 * 10 ¹⁸Atom/centimetre ³, or be set in the condition that no raceway groove produces.

Make the surface oxidation of amorphous silicon film 103.Add the nickel acetate aqueous solution of 1-100ppm then from the teeth outwards.Make the coating drying that is generated, thereby form acetate nickel dam 104.Because this layer 104 as thin as a wafer, it does not always present film shape (Fig. 1 (A)).

In 550 ℃ nitrogen environment,, make membrane crystallization through 4 hours these amorphous silicon films 103 of thermal annealing.Behind the thermal annealing, available excimer laser etc. are carried out photo-annealing, behind the thermal annealing, silicon fiml are corroded into silicon island district 105.After this, use the silicon oxide film 106 of thick 1200 of PCVD deposit as gate insulating film.Also available hot CVD replaces PCVD (Fig. 1 (B)).

Subsequently, the polysilicon film that contains 0.1-2% phosphorus reaches 3000 -8000 , for example 6000 with the LPCVD deposition thickness.This polysilicon film is corroded and forms gate electrode 107 (Fig. 1 (C)).

Subsequently, make mask with gate electrode 107, with impurity, or phosphorus is introduced silicon island district 105 with ion implantation.With hydrogen phosphine is diluted to 1-10% as impurity gas.Accelerating voltage is 60 to 90kV, for example 80KV.Dosage is 1 * 10 ¹³To 8 * 10 ¹⁵Atom/centimetre ², for example, 2 * 10 ¹⁴Atom/centimetre ²Ion injects, and with heater 110 substrate is heated to 250 ℃.As a result, constitute n type doped region 108 (sources) and 109 (leakages) (Fig. 1 D).

Subsequently, form the silicon oxide film 111 of thick 6000 with PCVD, as interlevel insulator.In this oxide-film, form contact hole.

With metal multilayer film (for example; Titanium and aluminium) constitute the source of TFT and the electrode and the conductive interconnection 112 and 113 (1 Fig. 1 (E)) of leakage.

Detect the concentration of nickel with secondary ion mass spectroscopy analytic approach (SIMS).Doped region and the concentration in the raceway groove at TFT are 1 * 10 ¹⁸To 5 * 10 ¹⁸Atom/centimetre ³Do not find that the catalytic elements concentration in the channel part distinguishingly descends.

In the prior art, after activating step, must in 200-350 ℃ hydrogen environment, carry out thermal annealing, or carry out plasma treatment.Among the present invention, needn't carry out this processing.With (raceway groove length * raceway groove wide=8 μ m * 8 μ m) among the TFT that the present invention obtained, cut-off current (gate voltage is-17V, drain voltage for+1V) be approximately 0.2 to 0.5pA.Make sample TFT under the condition identical with condition of the present invention (comprising size), just underlayer temperature is a room temperature in the ion implantation step, and substrate only is heated to 500 ℃ of maintenances 1 hour in activating step.The cut-off current of sample TFT is 5 to 20pA.

Embodiment 2

Among Fig. 2 (A)-2 (E) this example has been described.At first, on Corning7059 glass substrate 201, form the silica buffer film 202 of thick 4000 with PCVD.Then, form thick 200 to 1500 , for example the Intrinsical of 500 (I type) amorphous silicon film 203 with PCVD.Make the surface oxidation of amorphous silicon film 203, form the oxide-film (not shown).Then, the nickel acetate aqueous solution that adds 1-100ppm to the surface.Make the coating drying that is generated.Therefore form acetate nickel dam 204.

Use the KrF excimer laser, its wavelength is 248nm, and irradiation amorphous silicon film 203 discloses the crystallizing amorphous film 203 of 318701/1994 disclosed technology with Japan Patent.Before the laser irradiation, can carry out pre-thermal annealing at 250 to 500 ℃.In the laser irradiation, substrate can be heated to 250 to 400 ℃.If after laser irradiation,, can effectively remove the deformation (Fig. 2 (A)) in the crystal at 400 to 550 ℃ of thermal annealings through 1 to 4 hour.

Then, corrode the silicon fiml 203 of crystallization, form the silicon island district.Silicon oxide film 205 with thick 1200 of PCVD deposit.Afterwards, the crystal silicon film that contains 0.1 to 2% phosphorus of thick 4000 of deposit on silicon oxide film 205.The corrosion polysilicon film forms gate electrode 206.

After this, make mask, use ion implantation, foreign ion (boron ion) is introduced in the district of silicon island with gate electrode 206.With hydrogen diborane is diluted to 1 to 10%, as impurity gas.Accelerating voltage is 60 to 90kV, for example 80kV.Dosage is 1 * 10 ¹²To 1 * 10 ¹⁴Atom/centimetre ², for example, 1 * 10 ¹³Atom/centimetre ²Ion injects, and with heater 209 substrate 201 is heated to 350 ℃.As a result, form p type light doping section 207 and 208 (Fig. 2 (B)).

Then, anisotropically corrode the silicon oxide film of plasma deposition, form sidewall 210.Available known LDD (lightly doped leakage) formation technology is set up these sidewalls 210.In this example, in the forming process of sidewall 210, also corroded silicon oxide film 205.Afterwards, below gate electrode 206 and sidewall 210, stay the gate insulating film 211 (Fig. 2 (C)) of silica.

Introduce p type impurity once more with the ion injection.Use and be diluted to 1 to 10% diborane by hydrogen, as impurity gas.Accelerating voltage is 10 to 30kV, for example, and 20kV.Dosage is 1 * 10 ¹⁴To 8 * 10 ¹⁶Atom/centimetre ², for example, 1 * 10 ¹⁵Atom/centimetre ²Ion injects, and with heater 214 substrate is heated to 350 ℃.As a result, form p type heavily doped region 212 (sources) and 213 (leakages).

On the other hand, the

light doping section

207 and 208 below the sidewall 210 does not inject p type foreign ion.Form lightly doped source region 215 and lightly doped drain region 216 (Fig. 2 (D)) on the contrary.

Subsequently, make interlayer dielectric with the silicon oxide film 217 of thick 4000 of PCVD deposit.In this silicon oxide film 217, form contact hole.Afterwards, form aluminium source/drain electrode and interconnection 218 and 219 (Fig. 2 (E)).

In this example, ion does not use thermal annealing to activate after injecting, thereby has shortened process time very effectively.Disclose disclosed existing method in 267989/1994 by above-mentioned Japan Patent, heavily doped region is activated.Yet, with regard to light doping section, necessary with higher temperature thermal annealing.Need not to be the thermal annealing that activates in this example.Therefore these problems can not take place.

Embodiment 3

Having illustrated among Fig. 3 (A)-3 (E) should example.At first, use the silica buffer film 302 of PCVD thick 3000 of deposit on Corning1737 glass substrate 301.Afterwards, use for example Intrinsical amorphous silicon film 303 of 500 of thick 200 to 1500 of LPCVD deposit.After this, form the silicon oxide film 304 of thick 300 with PCVD.These films are that order forms.

Selective etching silicon oxide film 304 is so that form window 305 in the part film.Afterwards, identical method forms acetate nickel dam 306 in the use-case 1 and 2.The layered structure that will comprise substrate 301 through 8 hours thermal annealings, makes amorphous silicon film 303 crystallizations at 450 to 580 ℃ for example 550 ℃.Crystallization begins with window 305, and presses the propelling of arrow direction, and is described as the above-cited day disclosure 244104/1994.After the thermal annealing, available laser etc. carry out photo-annealing step (Fig. 3 (A)).

Afterwards, the silicon fiml of corrosion crystallization forms silicon island district 308.Silicon oxide film 309 (Fig. 3 (B)) with thick 1200 of PCVD deposit.

After this, forming thickness is 6000 , and contains the gate electrode 310 that the aluminium film of 0.1 to 0.3% scandium is made.Disclose disclosed gate electrode anodizing technology in 267667/1993 with Japan Patent, make the side surface of gate electrode 310 and top surface be blocked 311 coverings of type anodized coating.In this example, the thickness of barrier type anodized coating 311 is 1500 to 2000 .Corrosion oxidation silicon fiml 309 is to form gate insulating film 312.At this moment, the gate electrode part, or the end surfaces of gate electrode 310 and barrier type anodized coating 311 on every side is from the end surfaces displacement X (Fig. 3 (C)) of gate insulating film 312.

Afterwards, make mask, use ion implantation, foreign ion (phosphonium ion) is introduced in the silicon island district 308 with gate electrode part and gate insulating film 312.Use is diluted to the phosphine of 1-10% as dopant gas with hydrogen.Ion implantation technology is made of two steps.Accelerating voltage is 60 to 90kV in the first step, for example 80kV.Dosage is 1 * 10 ¹²To 1 * 10 ¹⁴Atom/centimetre ², for example, 1 * 10 ¹³Atom/centimetre ²Accelerating voltage is 10 to 30kV in second step, for example, and 20kV.Dosage is 1 * 10 ¹⁴To 8 * 10 ¹⁵Atom/centimetre ², for example 1 * 10 ¹⁵Atom/centimetre ²

In arbitrary ion implantation step, substrate 301 is heated to 300 ℃ with heater 315.In the result of high accelerating voltage light dope (first implantation step), lightly doped source region 316 and lightly doped drain region 317 have been formed.The result of heavy doping (second implantation step) has formed source region 313 and drain region 314 (Fig. 3 (D)).

Then, make interlevel insulator with the silicon oxide film 318 of thick 5000 of PCVD deposit.In this silicon oxide film 318, form contact hole.Afterwards, form titanium source/drain electrode and interconnection 319 and 320 (Fig. 3 (E)).

In the example 2, after light dope technology, carry out the film forming step, to obtain the structure of similar LDD.Afterwards, carry out the heavy doping step again.Therefore, two doping steps are separately carried out.On the other hand, in this example, different, can carry out light dope and heavy doping step in proper order with example 2.The result has obtained very high productivity ratio.

Example 4

In the example 3, around gate electrode, form fine and close anodic oxide coating, to obtain the LDD structure.Set up in this example, do not formed the LDD structure of fine and close anode oxide film.

Fig. 6 (A)-6 (E) and 7 (A)-7 (C) are the profiles of the manufacturing process of this routine TFT of explanation.Shown in Fig. 6 (A), form the silicon oxide film of thick 2000 with sputtering method, on Corning7059 glass substrate 601, as buffer film 602.Afterwards, form the intrinsic amorphous silicon film 603 of thick 500 with PCVD.

Make the surface oxidation of amorphous silicon film 603, form oxide-film (not shown) as thin as a wafer, then, add the nickel acetate aqueous solution of 1-100ppm for the oxide-film surface, make acetate nickel dam drying, form acetate nickel dam 604 (Fig. 6)).

Afterwards, in 550 ℃ nitrogen environment through 4 hours to the lamination thermal annealing.Because heating, acetate nickel dam 604 resolves into nickel, and evenly diffuses in the amorphous silicon film 603, therefore makes its crystallization.Behind the thermal annealing, available excimer laser etc. are carried out photo-annealing.

Silicon fiml after the corrosion crystallization forms silicon island district 605.Use the silicon oxide film 606 (Fig. 6 (B)) of thick 1000 of PCVD deposit afterwards.

After this, will become the aluminium film of thick 5000 of gate electrode 607 with the sputtering method deposit.In order to suppress hillock and whisker, comprised the scandium of 0.2wt% in the aluminum.

Anodic alumina films in electrolytic solution then forms the anode oxide film 608 of fine and close thick 100 from the teeth outwards.In this case, electrolytic solution is made of the ethylene glycol solution of the tartaric acid that contains 3-10%, boric acid or nitric acid.The pH value of electrolytic solution is transferred to about 7.Control the thickness of dense anodic oxide film 608 with being added on voltage on the aluminium film.Fine and close anode oxide film 608 is used to improve the adhesive force of photoresist.

Form photoresist mask 609.With these mask 609 corrosion aluminium films, form gate electrode 607 (Fig. 6 (C).

Make anode with being in photoresist mask 609 following gate electrodes 607, carry out another anodic oxidation step.Acid solution with the citric acid that contains 3-20%, oxalic acid, chromic acid or sulfuric acid is made electrolytic solution.In this case, have photoresist mask 609 and fine and close anodized surface 608 on the surface of gate electrode 607, thereby only on the sidewall of gate electrode 607, form the anodic oxide coating 610 of porous.

Control is added on the time of the electric current on the gate electrode 607, the growth distance of this porous anode layer 610 of may command.Decide the length of doped region again by this growth distance.In this example, it is 5000 (Fig. 6 (D)) that porous anode grows into length.

Afterwards, mask 609 with photoresist, corrosion oxidation silicon fiml 606, and form gate insulating film 611 (Fig. 6 (E)).

Shown in Fig. 7 (A), order is removed photoresist mask 609, and dense anodic oxide film 608 and porous anodic oxide 610 expose gate electrode 607.

Remove photoresist mask 609 with the liquid parting of special use.Hydrofluoric acid corrosion dense anodic oxide film 608 with buffering.Because dense anodic oxide film 608 is very thin, it can selectively be eroded.Mixed acid corrosion porous anodic oxide 610 with phosphoric acid, acetic acid and nitric acid.Because porous anodic oxide 610 is removed easily, therefore do not corrode gate electrode 607.

Produce in order to suppress hillock and whisker, the exposed surface with Ozone Water cleaning gate electrode 607 forms the oxide-film (not shown).If in the processing step of back, can suppress the generation of hillock and whisker, just do not need to form oxide-film.

Afterwards, make mask, use ion implantation, foreign ion is introduced in the silicon island district 605 with gate electrode 607.Use the phosphine (PH that is diluted to 1-10% by hydrogen ₃) make impurity gas.Ion implantation technology was made of two steps.In the ion implantation technology, substrate 601 is heated to 300 ℃ with heater 612.In first step, accelerating voltage is 60 to 90kV, for example, and 80kV.Dosage is 1 * 10 ¹²To 10 * 10 ¹⁴Atom/centimetre ², for example, 1 * 10 ¹³Atom/centimetre ²

At this moment, because accelerating voltage is bigger, phosphonium ion can not permeate gate electrode 607, but can infiltrate gate insulating film 611 and be injected in the silicon island district 605, because dosage is little, has formed light doping section 613 and 614.Owing to do not have the zone under the phosphonium ion introducing gate electrode 607, formed channel formation region 615 (Fig. 7 (A)).

In second step, accelerating voltage is less than the accelerating voltage of using in the first step, and promptly 10 to 30kV, for example, and 20kV ₀Dosage is 1 * 10 ¹⁴To 8 * 10 ¹⁵Atom/centimetre ², for example 1 * 10 ¹⁵Atom/centimetre ²

Thereby phosphonium ion is impermeable to advance gate insulating film 611, but mainly injects the exposed portions serve in silicon island district 605 with high concentration, therefore, and formation source/leakage 616 and 617.The lower part of gate insulating film 611 still keeps light doping section 613 and 614, and as channel formation region 615 (Fig. 7 (B)).

In this example, ion implantation technology was made of two steps.In an ion implant operation, also may form light doping section 613 and 614 and source/drain region 616,617, as Fig. 7 (B)) shown in.In this case, can suitably stipulate accelerating voltage, dosage and other condition, therefore, gate insulating film 611 plays semi-transparent masks.

After ion injects, form the silicon nitride film 618 of thick 300 with PCVD.Owing to be heated in the step of hydrogenation that gate electrode 607 can carry out afterwards, therefore the aluminium of may growing excessively produce be full of cracks and hillock.In this example, for preventing be full of cracks and hillock, with silicon nitride film 618 covering grid electrodes 607.

Then, the silicon oxide film that forms thick 6000 with PCVD is made interlevel insulator 619.In this silicon oxide film, constitute contact hole.Formation connects 620 and 621 by the source of the TFT of metal multilayer film (as titanium and aluminium) formation and electrode and the conduction region that the drain region is used.At last, TFT (Fig. 7 (C)) is finished in laminated construction heat treatment 1 hour in 350 ℃ hydrogen environment.

Among this routine TFT, light doping section 614 is preventing to add high voltage between channel formation region 615 and the drain region 617 between channel formation region 615 and the drain region 617.And can reduce cut-off current.

In this example, behind the ion implantation step, do not carry out activation, therefore can shorten the process time with thermal annealing or laser annealing.Although under lower temperature, can activate heavily doped region with thermal annealing.The thermal annealing temperature must be set at the high temperature that light doping section activates usefulness.In this example, needn't make the thermal annealing of its activation.Therefore, help to reduce treatment temperature.

In this example, form silicon nitride film 618, be used for grill-protected electrode 607.If both do not produced be full of cracks, do not produce hillock yet, because, needn't carry out thermal annealing or laser annealing, then can save silicon nitride film 618.

Example 5

The Production Example of the CMOSTFT that this example is made up of n type TFT and P type TFT.Fig. 8 (A) has illustrated this example to 8 (E).At first, on the upper surface of Corning7059 or 1737 glass substrate 801, form buffer film (not drawing).Afterwards, form Intrinsical (I type) amorphous silicon film of thick 500A with PCVD.As an example, thickness is that the silicon oxide film of 2000  is used as buffer film.Subsequently, make the amorphous silicon film crystallization with the method described in above-mentioned each example.Silicon fiml after the corrosion crystallization forms silicon island district 802 and 803.After this, use the silicon oxide film 804 of thick 1500 of PCVD deposit.

Afterwards, use the aluminium film of thick 4000 of sputtering method deposit.This aluminium film can become gate electrode 805 and 806 later.Produce in order to suppress hillock and whisker, this aluminium film has comprised the scandium of 0.2wt%.

After this, the anodic oxidation in electrolytic solution of aluminium film forms the dense anodic oxide film (not drawing) of the thick 100 orders of magnitude from the teeth outwards.On anode oxide film, form the photoresist mask, and photoetching composition.Use this photoresist mask etch aluminium film, form gate electrode 805 and 806.

Afterwards, on gate electrode 805 and 806, keep the photoresist mask to its anodic oxidation once more.With the citric acid that contains 3-20%, oxalic acid, chromic acid or sulfuric acid (for example, 3% oxalic acid aqueous solution) acid solution constitutes electrolytic solution, in this case, have photoresist mask and dense anodic oxide thing on gate electrode 805 and 806 the surface, therefore, only on the sidewall of gate electrode 805 and 806, form porous anodic oxide 807 and 808, control the anodised processing time and can control the growth distance of porous anodic oxide 807 and 808.This growth distance can determine the length of light doping section (CDD) afterwards.In this example, porous anodic oxide 807 and 808 grows into thick 7000 .

Anodic oxidation gate electrode 805 and 806 again, the firm anode oxide film 809 and 810 to form densification.In this example, contain 3% tartaric ethylene glycol solution, make its pH value reach 6.9, re-use (Fig. 8 (A) with the ammoniacal liquor neutralization.

Afterwards, make mask with anodic oxidation district 807,808,809 and 810, corrosion oxidation silicon fiml 804.If do not corrode anodic oxidation district 807,808,809 and 810 and corrosion oxidation silicon fiml 804 only, then this etching process both can be a wet corrosion, also can be dry corrosion.In this example, use CLF ₃Gas dry corrosion silicon oxide film 804 forms gate insulating film 811 and 812 (Fig. 8 (B)).

Afterwards, order is removed dense anodic oxide thing (not shown) and porous anodic oxide 807 and 808, removes dense anodic oxide thing (not shown) with the hydrofluoric acid of buffering.Mixed acid with phosphoric acid, acetic acid and nitric acid erodes porous anodic oxide 807 and 808.Owing to can easily remove porous anodic oxide 807 and 808, thereby not corrode densification and firm anodic oxygen thing 809 and 810.

Afterwards, make mask, inject, foreign ion is drawn inject silicon island 802 and 803 with ion with gate electrode 805 and 806.In this example, use the phosphine (PH that is diluted to 1-10% with hydrogen ₃) as impurity gas.Ion implantation technology was made of two steps.In the ion implantation technology, by the present invention, substrate 801 usefulness heater heats arrive as 250 to 350 ℃.In first step, accelerating voltage is 10 to 30kV, for example 10kV.Dosage is 1 * 10 ¹⁴To 8 * 10 ¹⁵Atom/centimetre ², for example 1 * 10 ¹⁵Atom/centimetre ²

At this moment, accelerating voltage is lower, so phosphonium ion can not penetrate gate insulating film 811 and 812.They mainly infiltrate the exposed portions serve of silicon island 802 and 803, therefore form source region 813,816 and drain region 814,815.Being in mode in the zone narrower in source/drain region with the peak value of dopant profiles figure carries out ion and injects.

Be higher than the accelerating voltage of first implantation step at accelerating voltage, i.e. 60-90kV, for example 80kV carries out second implantation step, and dosage is 1 * 10 ¹²To 5 * 10 ¹³Atom/centimetre ², for example 1.5 * 10 ¹³Atom/centimetre ²

At this moment, because accelerating voltage is higher, phosphonium ion is impermeable crosses gate electrode 805 and 806, but its porous is crossed gate insulating film 811 and 812.Afterwards, ion is launched in silicon island district 802 and 803, yet the zone that is positioned under the gate insulating film is sheltered by gate insulating film, and formed light doping section (LDD district) 817 and 818, and, phosphonium ion is not injected in zone under the gate electrode 805 and 806, therefore, has formed channel formation region 819 and 820.In this case, the doping figure is to determine like this, and peak value is in the dark zone in source/drain region, because first and second implantation steps, phosphonium ion is evenly distributed in (Fig. 8 (C)) in source/drain region.

Cover laminated construction with polyimides or heat-resisting photoresist 821, only remove and to become the photoresist part (Fig. 8 (D)) of P transistor npn npn.Afterwards, introduce the boron ion, make the N type be transformed into the P type with ion implantation.In this example, with accelerating voltage 65kV and dosage 1～5 * 10 ¹⁴Atom/centimetre ²Carry out the first ion implantation step.With accelerating voltage 10kV and dosage 2 * 10 ¹⁵Atom/centimetre ²Carry out the second ion implantation step.The boron ion is not injected in zone by polyimides or 821 coverings of heat-resisting photoresist, still keeps the N type.

Afterwards, remove photoresist 821.Form the silicon oxide film of thick 1 μ m with PCVD,, and set up contact hole as interlevel insulator 822.Metal multilayer film with titanium and aluminium constitutes electrode and the interconnection of using in source/drain region 823,824 and 825.At last, laminated construction in 350 ℃ hydrogen environment through heat treatment in 2 hours.According to said method finish CMOSTFT (Fig. 8 (E)).

This routine TFT constitutes the CMOS structure that is made of N transistor npn npn and P transistor npn npn complementary combinations, thereby, when transistor is driven and during conducting, can realize lower electrical power consumed, and, because light doping section 817 and 818 is between channel formation region 819 and the drain region 814 respectively and between channel formation region 820 and the drain region 815.Thereby, can prevent from producing electric field between channel formation region 819 and the drain region 814 and between channel formation region 820 and the drain region 815 respectively, and the thermal annealing that neither is used to activate after ion injects does not carry out laser annealing yet.Therefore the process time can be shortened.

Example 6

This example is CMOS (complementary MOS) TFT of N type TFT and P type TFT.

Fig. 9 (A)-9 (E) has illustrated this example.At first, on the top surface of the glass substrate 901 that Corning7059 or 1737 glass are made, form resilient coating (show and draw).Form the intrinsic amorphous silicon film of thick 500 with PCVD.For example, the silicon oxide film by thick 2000 constitutes buffer film.Afterwards, make the amorphous silicon film crystallization by the identical mode of above-mentioned example, the silicon fiml after the corrosion crystallization forms

silicon island district

902 and 903, and after this, the silicon oxide film 904 of thick 1500 of deposit is made gate insulating film.

Afterwards, with the aluminium film of thick 4000 of sputtering method deposit, this aluminium film will become

gate electrode

905 and 906 later.For suppressing hillock and whisker, this aluminium film has comprised the scandium of 0.2wt%.

Afterwards, in electrolytic solution, make the anodic oxidation of aluminium film form the dense anodic oxide film (not shown) of thick approximately 100A from the teeth outwards.On the aluminium film, form photoresist mask and photoetching composition.Mask etch aluminium film forms

gate electrode

905 and 906 with photoresist.Stay the photoresist mask, once more anodization gate electrode 905 and 906.The acid solution (for example 3% oxalic acid aqueous solution) that contains citric acid, oxalic acid, chromic acid or the sulfuric acid of 3-20% constitutes electrolytic solution.In this case,

gate electrode

905 and 906 surface, two sides have photoresist mask and dense anodic oxide thing, therefore, only form porous

anodic oxide

909 and 910 on the sidewall of gate electrode 905 and 906.Control the anodised process time, may command porous

anodic oxide

909 and 910 growth distance, this growth distance will determine the length of light doping section (LDD) later on.In this example, porous

anodic oxide

909 and 910 length are to thick 7000 .

Anodization porous

anodic oxide

905 and 906 forms fine and close and firm anode oxide film 911 and 912 once more.In this example, contain 3% tartaric ethylene glycol, make its pH value reach 6.9 and re-use (Fig. 9 (A)) with the ammoniacal liquor neutralization.

Afterwards, with

gate electrode

905 and 906 and porous

anodic oxide

909 and 910 make mask, inject with ion foreign ion introduced silicon island 902 and 903.In this example, use is diluted to the phosphine (PH3) of 1-10% as impurity gas by hydrogen.In the injection technology, with heater substrate is heated to 250 to 350 ℃ by the present invention.Ion injects, and accelerating voltage is 60 to 90kV, 80kV for example, and dosage is 1 * 10 ¹²To 1 * 10 ¹⁵Atom/centimetre ², for example 1 * 10 ¹⁵Atom/centimetre ²

At this moment, because accelerating voltage is higher, impermeable any one that cross in gate electrode 905,906 and porous

anodic oxide

909 and 910 of phosphonium ion, but its transmission grating dielectric film 904.Then, ion deposition forms source region 913,916 and drain region 914,915 in silicon island 902 and 903.Yet phosphonium ion is not injected in the zone that is positioned under gate electrode 905 and 906.Therefore formed channel formation region 917 and 918 (Fig. 9 (B)).

Afterwards, remove dense anodic oxide thing (not shown) with the hydrofluoric acid of buffering.Afterwards, the mixed acid with phosphoric acid, acetic acid and nitric acid erodes porous anodic oxide 909 and 910.Because it is remove porous

anodic oxide

909 and 910 easily, fine and close and firm anodic oxide 911 and 912 is not corroded.

Re-inject phosphonium ion, accelerating voltage is 60 to 90kV 80kV for example, and dosage is 1 * 10 ¹²To 1 * 10 ¹⁴Atom/centimetre ², for example, 1 * 10 ¹⁴Atom/centimetre ²

This moment is because accelerating voltage is higher, and phosphonium ion is

transmission grating electrode

905 and 906 not, but transmission grating dielectric film 904.Ion is launched in

silicon island district

902 and 903, because channel formation region 917 and source/drain region 913, zone between 914, and the zone between channel formation region 918 and the source/drain region 915,916, it is light doping section with phosphorus doping, therefore, formed light dope (LDD district) 919 and 920 (Fig. 9 (C)).

Cover laminated construction and composition with polyimides or heat-resisting photoresist 921, only remove and to become the photoresist (Fig. 9 (D)) of P transistor npn npn part.Afterwards, introduce the boron ion, make the N type become the P type with ion implantation.In this example, accelerating voltage is 80kV.Boron dosage is 2 * 10 ¹⁵Atom/centimetre ²The boron ion is not injected in zone by polyimides or 921 coverings of heat-resisting photoresist, therefore is still the N type.At this moment, because a large amount of boron ion is introduced, between drain region 915 and channel region 918, do not form light doping section (LDD district).

Afterwards, remove photoresist 921.Form the silicon oxide film of thick 1 μ m with PCVD, as interlevel insulator film 922.In interlevel insulator film 922, constitute contact hole.Constitute electrode and the interconnection of using in source/drain region 923,924 and 925 with the metal multilayer film of titanium and aluminium, last, laminated construction heat treatment 2 hours in 350 ℃ hydrogen environment, method is finished CMOS TFT (Fig. 9 (E)) thus.

This routine TFT forms the CMOS structure that is made of N transistor npn npn and P transistor npn npn complementary combinations.Thereby, when transistor is driven and during conducting, can realizes low electrical power consumed, and, because light doping section 919 between channel formation region 917 and drain region 914, can prevent to produce electric field between channel formation region 917 and drain region 914.And, after ion injects, neither make the thermal annealing of its activation, do not carry out laser annealing yet, therefore can shorten the process time.

Even under the situation of using the catalytic elements that promotes crystallization, the present invention also can make the TFT of the good characteristic with low cut-off current and high reliability, the result, can develop as Japanese Patent Application Publication 244104/1994,267989/1994,318401/1994 and 333951/1994 described technology of carrying out low temperature crystallization with catalytic elements, therefore, the present invention has the industrialization advantage.

Claims

1. method of making thin-film transistor comprises following processing step:

Form non-single crystal semiconductor film on the insulating surface of substrate, it is 1 * 10 that described semiconductor film is added with concentration ¹⁵To 1 * 10 ¹⁹Atom/centimetre ³, can promote its crystallization catalytic elements and

Speeding-up ion with described dopant impurities injects to the described semiconductor layer that has the described substrate that has heated with the hydrogen or halogen ion, and dopant impurities is introduced in the described non-single crystal semiconductor layer of part, obtains p conductivity type or N conductivity type.

2. by the method for claim 1, it is characterized in that the concentration of described catalytic elements is defined as the minimum value of analyzing the value of described semiconductor layer acquisition with the secondary ion mass spectroscopy analytic approach.

By the method for claim 1, it is characterized in that in the introducing process of described dopant impurities, described underlayer temperature remains in 100 to 400 ℃ the temperature range.

4. by the method for claim 1, it is characterized in that described catalytic elements is selected from the metal set that nickel, iron, cobalt, platinum and palladium are formed.

5. by the method for claim 1, it is characterized in that in described dopant impurities introducing process, described underlayer temperature remains in 200 to 350 ℃ the temperature range.

6. by the method for claim 1, it is characterized in that, introduce described impurity by the self-aligned manner of the described semiconductor film of the residing position adjustments of gate electrode.

7. by the method for claim 2, it is characterized in that described semiconductor film comprises silicon.

8. method of making TFT comprises following process steps:

Form thin non-single crystal semiconductor film on substrate, it is 1 * 10 that described non-single crystal semiconductor film comprises concentration ¹⁵To 1 * 10 ¹⁹Atom/centimetre ³, the catalytic elements of promotion crystallization;

On described non-single crystal semiconductor film, form gate electrode;

In the first indoor heated substrate;

Preparation can produce the foreign ion of conductivity type n or p; With

Afterwards, quicken described foreign ion, collide described non-single crystal semiconductor, simultaneously with the second Room heated substrate that inoperative heater is housed with hydrogen ion or halogen ion.

9. by the method for claim 8, it is characterized in that the concentration of described catalytic elements is defined as the minimum value of analyzing the value of described semiconductor film acquisition with the secondary ion mass spectroscopy analytic approach.

10. by the method for claim 8, it is characterized in that in described dopant impurities introducing process, described underlayer temperature remains in 100 to 400 ℃ the temperature range.

11. the method by claim 8 is characterized in that, described catalytic elements is selected from the metal set of being made up of nickel, iron, cobalt, platinum and palladium.

12., it is characterized in that in described dopant impurities introducing process, described underlayer temperature remains in 200 to 350 ℃ the temperature range by the method for claim 8.

13. the method by claim 8 is characterized in that, in self aligned mode, introduces dopant impurities with respect to the gate electrode adjacent with described semiconductor film

14. the method by claim 9 is characterized in that described semiconductor film comprises silicon.

15. a method of making TFT comprises following processing step:

(1) forming on substrate is the film of amorphous silicon basically;

(2) form the coating that comprises the catalytic elements that promotes crystallization, make described coating be right after the top surface or the basal surface of described silicon fiml;

(3) described silicon fiml thermal annealing makes described catalytic elements diffuse into described silicon fiml, makes described silicon fiml crystallization;

(4) gate electrode of the described TFT of formation on the silicon fiml after the described crystallization;

(5) preparation makes described silicon fiml produce the foreign ion of conduction type n or p; With

(6) make mask with gate electrode, make described substrate be heated to 100 to 400 ℃, institute's foreign ion is injected described silicon fiml, form the low concentration impurity district.

16. the method by claim 15 is characterized in that, described catalytic elements is selected from the metal set that nickel, iron, cobalt, platinum and palladium are formed.

17. the method by claim 15 is characterized in that, in step (6), maybe will begin step (6) before, and substrate is heated to 200 ℃ to 350 ℃.

18. an equipment that is used to make TFT, this TFT has substrate, and the non-single crystal semiconductor that forms on described substrate is led film, and it is 1 * 10 that the gate electrode that forms on described non-single crystal semiconductor film, described non-single crystal semiconductor film comprise concentration ¹⁵To 1 * 10 ¹⁹Atom/centimetre ³The catalytic elements of promotion crystallization, described equipment comprises:

One first Room is used for heated substrate; With

One second Room, be used to quicken described foreign ion, collide described non-single crystal semiconductor film with hydrogen ion or halide ion, inoperative heater is equipped with in described second Room, described foreign ion produces conduction type n or p, in ion collision, described second Room makes described substrate be heated to 100-400 ℃.

19. an equipment that is used to make TFT, described TFT has substrate, is formed on the non-single crystal semiconductor film on the substrate, is formed on the gate electrode on the described non-single crystal semiconductor film, and it is 1 * 10 that described non-single crystal semiconductor film comprises concentration ¹⁵To 1 * 10 ¹⁹Atom/centimetre ³Or the catalytic elements of above promotion crystallization, described equipment comprises:

A chamber is used for foreign ion is injected described non-single crystal semiconductor film, makes described non-single crystal semiconductor film produce conduction type n or p;

Be included in a described indoor accelerator, be used to quicken described foreign ion, make it collide described substrate with hydrogen ion or halide ion; With

Be included in described indoor heater, be used for making described underlayer temperature remain on 100 to 400 ℃ in described ion collision.

20. make the transistorized method of CMOS for one kind, this CMOS transistor comprises p channel transistor and n channel transistor, described method comprises following processing step:

Form a pair of semiconductor island that comprises silicon metal, described semiconductor island is added with the catalytic elements that promotes its crystallization;

Form dielectric film on described substrate, described dielectric film covers the whole surface of described semiconductor island;

Form gate electrode on each semiconductor island;

Make mask with gate electrode, phosphonium ion is introduced in each described semiconductor island;

Only cover in the described semiconductor island one with the organic substance mask, described organic substance mask comprises the material that is selected from the material group that heat-resisting photoresist and heat-proof polyimide form; With

Make mask with described gate electrode, introduce the boron ion for another described semiconductor island, and a described semiconductor island cover with described organic substance mask,

Wherein, in described phosphonium ion and boron ion were introduced, substrate remained in 100 to 400 ℃ the temperature range.

21. the method by claim 20 is characterized in that described phosphonium ion and described boron ion are introduced with hydrogen or halogen element.

22. make the transistorized method of CMOS for one kind, this CMOS transistor comprises p channel transistor and n channel transistor, described method comprises following processing step:

Form a pair of semiconductor island that comprises silicon metal, described semiconductor island has added the catalytic elements that promotes its crystallization;

Form gate electrode on each semiconductor island, but described gate electrode comprises the anodic oxidation material;

For the described gate electrode on each described semiconductor island be to form anodic oxide coating on the side surface at least, the described gate electrode of anodic oxidation;

Make mask with described anodic oxide coating and described gate electrode, corrode the described dielectric film on each described semiconductor island;

In order to expose the upper surface that is positioned at the described dielectric film below each the above anodic oxide coating of described semiconductor island, corrode described anodic oxide coating,

Make mask with described gate electrode and described dielectric film, carry out phosphonium ion is introduced first ion introducing of each described semiconductor island;

Make mask with described gate electrode, and the exposed portions serve by described dielectric film, carry out phosphonium ion is introduced second ion of each described semiconductor island and introduce;

Only cover a described semiconductor island with the organic substance mask, described mask comprises the material of the material group that is selected from heat-resisting photoresist and heat-proof polyimide composition;

Make mask with described gate electrode and described dielectric film, and described mask covers a described semiconductor island, carry out the boron ion is introduced the 3rd ion introducing of another semiconductor island; With

Make mask with described grid, and the exposed portions serve by described dielectric film, and described mask covers a described semiconductor island, carries out the boron ion is introduced the 4th ion of another semiconductor island and introduce,

Wherein, during any in the first, second, third and the 4th ion is introduced once introduces, described substrate remains on 100-400 ℃ temperature.

23. the method by claim 22 is characterized in that, in the first, second, third and the 4th ion is introduced, introduce hydrogen or halogen element simultaneously.

24. make the transistorized method of CMOS for one kind, the CMOS transistor comprises p channel transistor and n channel transistor, described method comprises following processing step:

Form gate electrode on each described semiconductor island, described gate electrode comprises can anodised material;

For the described gate electrode on each described semiconductor island be to form anodic oxide coating on the side at least, the described gate electrode of anodic oxidation;

Make mask with described gate electrode and described anodic oxide coating,,, carry out phosphonium ion is introduced first ion introducing of each described semiconductor island by first dosage by described insulating barrier;

Described first ion corrodes described anodic oxide coating after introducing;

After corroding described anodic oxide coating, make mask with described gate electrode, by described dielectric film, by second dosage, it is less than described first dosage, and second ion that carries out phosphonium ion is introduced is introduced;

Make mask with described gate electrode, by described dielectric film, and described organic substance mask covers a described semiconductor island, carries out the boron ion is introduced the 3rd ion introducing of another described semiconductor island;

Wherein, during any primary ions in the described first, second, third and the 4th ion is introduced was introduced, described substrate remained on 100 to 400 ℃ temperature.

25. the method by claim 24 is characterized in that, introduces hydrogen or halogen element simultaneously in described first, second introduced with the 3rd ion.