CN113452362A

CN113452362A - Integrated circuit implementing NAND gate system and implementing NOR gate system

Info

Publication number: CN113452362A
Application number: CN202110419241.XA
Authority: CN
Inventors: 奥古斯丁·魏-春·张; 皮埃尔·德尔米
Original assignee: Schottky LSI Inc
Current assignee: Schottky LSI Inc
Priority date: 2017-04-10
Filing date: 2018-04-10
Publication date: 2021-09-28
Anticipated expiration: 2038-04-10
Also published as: WO2018191217A1; TW201904198A; EP3610573A1; CN110622419A; WO2018191217A4; EP3610573A4; TW202230983A; CN113452362B; TWI760477B; CN110622419B

Abstract

The invention relates to an integrated circuit implementing a NAND gate system and implementing a NOR gate system. An integrated circuit implementing a NAND gate system, comprising: a first input coupled to a cathode of the first schottky diode; x additional inputs coupled to x respective cathodes of x additional schottky diodes, wherein x is an integer; an inverter having an inverter input and an inverter output, wherein: the integrated circuit is configured for asynchronous operation; the inverter is biased between the high voltage power supply and the low voltage power supply; an inverter input coupled to an anode of the first schottky diode and x corresponding anodes of the x additional schottky diodes; and the inverter output is coupled to the output of the NAND gate system; and a source follower tree comprising one or more N-type transistors, wherein the source follower tree is biased between the high voltage power supply and the inverter input.

Description

Integrated circuit implementing NAND gate system and implementing NOR gate system

The application is a divisional application of applications with the PCT application number of PCT/US2018/026817, the international application date of 2018, 4 and 10 months, the Chinese application number of 201880031001.9 and the invention name of 'Schottky CMOS asynchronous logic unit'.

Technical Field

The present application relates to semiconductor devices and circuits, and more particularly, to the use of Super Complementary Metal Oxide Semiconductor (SCMOS)^TM) Analog, digital, and mixed-signal Integrated Circuits (ICs) that devices, and thus exhibit improved device performance due to improved power consumption, operating speed, circuit area, and device density.

Background

Since the introduction of Integrated Circuits (ICs), engineers have attempted to increase the density of circuits on ICs, which reduces the manufacturing cost of so-called ICs. One approach is to put more components/functions on the chip. The second approach is to build more chips on a larger wafer to reduce IC cost. For example, the size of silicon wafers has grown from the 3 inches average diameter in the 1960 s to the 12 inches today.

Various attempts have been made in the past to improve IC functionality, performance, and cost performance. Early IC implementations used Bipolar Junction Transistors (BJTs) with vertically stacked layers of individual diffusions and isolated transistor pockets containing three switched terminals (base, emitter and collector) and other resistive (R) and capacitive (C) circuit elements. However, in IC implementations of the last decade, there is scaling of the V-I signal and PHY parameters to accommodate more components on the chip.

CMOS technology follows and surpasses BJT technology, which is relatively bulky, provides poor transistor yield, and exhibits high DC power usage. Device complexity using complementary mos (cmos) structures has grown to billions of circuit elements. Over 30 years, cost reduction and CMOS technology performance improvements have been achieved by shrinking the physical size of CMOS transistors. These dimensions shrink to the size of only a few molecular layers thick in critical device parameters. However, further scaling of CMOS is being limited by the laws of physics. In addition to attempting to fabricate hundreds of billions of CMOS circuit elements having "molecular" dimensions, these significantly smaller circuits also operate at very low signal (voltage) levels, making their signal integrity susceptible to noise and resulting in speed droop and/or power/heat loss.

Disclosure of Invention

In various embodiments, Schottky (Schottky) -CMOS (also referred to herein as "super CMOS" and SCMOS)^TM) Techniques are used to use devices such as low threshold schottky barrier diodes (LtSBD)^TM) To construct a circuit block, thereby solving the above-mentioned drawbacks and problems associated with the increasing demand for higher semiconductor efficiency and the upcoming physical limitation of CMOS transistor size.

In some embodiments, the integrated circuit implements a NAND gate system. The integrated circuit includes a first input coupled to the cathode of the first p-type schottky diode and x additional inputs coupled to the x respective cathodes of the x additional p-type schottky diodes. The integrated circuit additionally includes a first n-type transistor including a gate node coupled to the anode of the first schottky diode and the x anodes of the x additional schottky diodes. The integrated circuit further includes a p-type transistor including a gate node coupled to the anode of the first schottky diode and the x respective anodes of the x additional schottky diodes. The integrated circuit further includes a second n-type transistor including a cathode coupled to the first p-type schottky diode and gate nodes of x additional n-type transistors including x respective gate nodes coupled to respective cathodes of x of the x additional p-type schottky diodes. The output is coupled to a non-gate node of the first n-type transistor and a non-gate node of the p-type transistor.

In some embodiments, the integrated circuit implements a NOR gate system. The integrated circuit includes a first input coupled to an anode of the first n-type schottky diode and x additional inputs coupled to x respective anodes of x additional n-type schottky diodes. The integrated circuit additionally includes a first p-type transistor including a gate node coupled to a cathode of the first n-type schottky diode and cathodes of the x additional n-type schottky diodes. The integrated circuit additionally includes an n-type transistor including a gate node coupled to a cathode of the first n-type schottky diode and to cathodes of the x additional n-type schottky diodes. The integrated circuit additionally includes a second p-type transistor including gate nodes coupled to the anode of the first n-type schottky diode and x additional p-type transistors including gate nodes coupled to the x respective anodes of the x additional n-type schottky diodes. The output is coupled to the non-gate node of the first p-type transistor and the non-gate node of the n-type transistor.

In some embodiments, the integrated circuit implements an x-input logic gate. The integrated circuit includes a plurality of schottky diodes including x schottky diodes and a plurality of source follower transistors including x source follower transistors. Each respective source follower transistor of the plurality of source follower transistors includes a respective gate node coupled to a respective schottky diode. A first source follower transistor of the plurality of source follower transistors is connected in series to a second source follower transistor of the plurality of source follower transistors.

Various advantages of the disclosed techniques will be apparent from the following description.

Drawings

The foregoing features and advantages of the present disclosure, as well as additional features and advantages thereof, will be more clearly understood hereinafter as a result of the detailed description of preferred embodiments when taken in conjunction with the accompanying drawings.

In order to more clearly illustrate the technical solution according to the embodiments of the present invention, the drawings required for the embodiments are briefly described below. The drawings, however, illustrate only the more pertinent features of the present disclosure and therefore should not be considered limiting as the description may admit to other effective features.

Fig. 1 is a circuit diagram of a two-input schottky CMOS NAND gate according to some embodiments.

Fig. 2 is a circuit diagram of an eight-input schottky CMOS NAND gate according to some embodiments.

Fig. 3 is a circuit diagram of an 8-input CMOS NAND gate.

Fig. 4 is a circuit diagram of a two-input schottky CMOS NOR gate according to some embodiments.

Fig. 5 is a circuit diagram of an eight-input schottky CMOS NOR gate according to some embodiments.

Fig. 6 is a circuit diagram of an 8-input CMOS NOR.

Fig. 7 is a circuit diagram of a schottky CMOS implementation of a 4-to-1 multiplexer circuit according to some embodiments.

Fig. 8 shows a CMOS implementation of a 4-to-1 multiplexer circuit.

Fig. 9 is a graph comparing layout area of NAND gates implemented using schottky CMOS with layout area of NAND gates implemented using CMOS, in accordance with some embodiments.

Fig. 10 is a graph comparing Root Mean Square (RMS) power consumption of NAND gates implemented using schottky CMOS with power consumption of NAND gates implemented using CMOS, in accordance with some embodiments.

Fig. 11 is a graph comparing the propagation delay of a NAND gate implemented using schottky CMOS with the propagation delay of a NAND gate implemented using CMOS, in accordance with some embodiments.

Figures 12A-12G show CMOS implementations with various numbers of inputs of NAND gates.

Like reference numerals designate corresponding parts throughout the several views of the drawings.

Detailed Description

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the subject matter presented herein. It will be apparent, however, to one skilled in the art that the subject matter may be practiced or designed without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments. The trademark designated herein by the "TM" symbol is the property of Schottky LSI, inc.

The technical solution of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is apparent that the embodiments to be described are only examples and are merely a part of the disclosure and not all embodiments of the disclosure. All other embodiments derived by one of ordinary skill in the art from the embodiments described in the present disclosure are within the scope of the present disclosure.

The schottky CMOS technology described herein implements logic using schottky barrier diodes (also referred to herein as "SBDs" and "schottky diodes"). In contrast to existing CMOS implementations, the various embodiments of schottky CMOS described herein use schottky diodes instead of p-type metal oxide semiconductor (PMOS) field effect transistors and/or n-type metal oxide semiconductor (NMOS) field effect transistors. Particularly as the number of logic inputs to the logic gate increases, replacing PMOS and NMOS transistors with schottky diodes can improve the logic efficiency achieved in a variety of ways, including reduced area consumed by circuit layout, reduced propagation delay, and reduced power consumption required for switching.

The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

Fig. 1 is a circuit diagram of a two-input schottky CMOS NAND gate according to some embodiments. The two-input schottky CMOS NAND gate includes two p-type schottky diodes 102 and 104 and a source follower tree 106 including two n-

type transistors

108 and 110. The transistors in the source follower tree 106 are connected in series as indicated by connection 112. Input a0 is coupled to the cathode of p-type Schottky Barrier Diode (SBD)102 and the gate node of n-type transistor 108. Input a1 is coupled to the cathode of p-type SBD 104 and the gate node of n-type transistor 110. The anode of SBD 102 and the anode of SBD 104 are coupled to the gates of

result transistors

114 and 116. The result transistor 114 is an n-type transistor and the result transistor 116 is a p-type transistor. Output 118 is coupled to the non-gate nodes of

result transistors

114 and 116. In particular, output 118 is coupled to the drain node of n-type transistor 114, and output 118 is coupled to the drain node of p-type transistor 116.

In some embodiments, the two-input schottky CMOS NAND gate includes feedback logic that receives an output signal as an input at the gate nodes of the n-type transistor 120 and the p-type transistor 122.

Although a CMOS implementation of a two-input NAND gate will use a p-type transistor and an n-type transistor coupled to each input of the NAND gate, in some embodiments, a schottky CMOS implementation of a two-input NAND gate uses a p-type SBD and an n-type transistor coupled to each input (with the p-type SBD in the schottky CMOS implementation replacing the p-type transistors of the CMOS implementation). As the number of inputs in the NAND gate increases, the efficiency obtained by replacing the transistors with SBDs increases, for example, as shown by the CMOS and schottky CMOS performance comparisons of fig. 9-11.

Fig. 2 is a circuit diagram of an eight-input schottky CMOS NAND gate according to some embodiments. The eight-input Schottky CMOS NAND gate includes eight p-type Schottky diodes 202-216 and a source follower tree 218 including eight n-type transistors 220-234. The transistors 220-234 in the source follower tree 218 are connected in series (e.g., the drain node of the transistor 220 is coupled to the source node of the transistor 224, the drain node of the transistor 224 is coupled to the source node of the transistor 228, etc.). Input a0 is coupled to the cathode of p-type SBD 202 and the gate node of n-type transistor 220. Input a1 is coupled to the cathode of p-type SBD 204 and the gate node of n-type transistor 222. Input a2 is coupled to the cathode of p-type SBD 206 and the gate node of n-type transistor 224. Input a3 is coupled to the cathode of p-type SBD 208 and the gate node of n-type transistor 226. Input a4 is coupled to the cathode of p-type SBD 210 and the gate node of n-type transistor 228. Input a5 is coupled to the cathode of p-type SBD 212 and the gate node of n-type transistor 230. Input a6 is coupled to the cathode of p-type SBD 214 and the gate node of n-type transistor 232. Input a7 is coupled to the cathode of p-type SBD 216 and the gate node of n-type transistor 234.

The anode of SBD 202-216 is coupled to the gates of

result transistors

236 and 238. The result transistor 236 is an n-type transistor and the result transistor 238 is a p-type transistor. Output 240 is coupled to the non-gate nodes of

result transistors

236 and 238. In particular, output 240 is coupled to the drain node of n-type transistor 236, while output 240 is coupled to the drain node of p-type transistor 238.

In some embodiments, an eight-input schottky CMOS NAND gate includes feedback logic that receives an output signal as an input at the gate nodes of n-type transistor 242 and p-type transistor 244.

It will be appreciated that the scaling illustrated with respect to fig. 1-2 may be extended to other numbers of NAND gate inputs. For each additional input, an additional SBD is coupled to the additional input, and an additional source follower transistor complementary to the SBD (e.g., an n-type transistor complementary to the p-type SBD) is added to the source follower tree (e.g., as shown by source follower tree 106 of fig. 1 or source follower tree 218 of fig. 2). The additional input is coupled to the additional SBD (e.g., to the cathode of the p-type SBD) and to the gate node of the additional source follower transistor. The additional SBD is coupled (e.g., the anode of the p-type SBD) to the gate node of the result transistor set (e.g., as shown by

result transistors

114 and 116 of fig. 1 or result

transistors

236 and 238 of fig. 2).

For example, a four-input Schottky CMOS NAND gate includes four inputs A0-A3, four p-type SBDs (e.g., configured as shown by

SBD

202 and 208 of FIG. 2) and four n-type transistors (e.g., transistors shown as 220, 222, 224, and 226 of FIG. 2 connected in series).

In some embodiments, the schottky CMOS NAND gate includes a plurality of inputs, such as twelve inputs, between two inputs and sixteen inputs.

Fig. 3 is a circuit diagram of an 8-input CMOS NAND gate. The CMOS 8 input NAND gate requires three

NAND gates

302, 304, and 306, a NOR gate 308, and

inverters

310 and 312. The stacked configuration of NAND gates 302-306 feeding NOR gates 308 as shown in fig. 3 requires increased power and increased supply current, and results in increased layout area, increased switching time, and increased propagation delay (as further described below with respect to fig. 9-12) as compared to the schottky CMOS eight-input NAND gates described with respect to fig. 2.

Fig. 4 is a circuit diagram of a two-input schottky CMOS NOR gate according to some embodiments. The two-input schottky CMOS NOR gate includes two n-

type schottky diodes

402 and 404 and a source follower tree 406 that includes two p-

type transistors

408 and 410. The transistors in the source follower tree 406 are connected in series. Input a0 is coupled to the anode of n-type Schottky Barrier Diode (SBD)402 and the gate node of p-type transistor 408. Input a1 is coupled to the anode of n-type SBD 404 and the gate node of p-type transistor 410. The cathode of SBD 402 and the cathode of SBD 404 are coupled to the gates of

result transistors

414 and 416. The resulting transistor 414 is an n-type transistor and the resulting transistor 416 is a p-type transistor. Output 418 is coupled to the non-gate nodes of

result transistors

414 and 416. Specifically, output 418 is coupled to the drain node of n-type transistor 414, while output 118 is coupled to the drain node of p-type transistor 416.

In some embodiments, a two-input schottky CMOS NOR gate includes feedback logic that receives an output signal as an input at the gate nodes of n-type transistor 420 and p-type transistor 422.

Although a CMOS implementation of a two-input NOR gate will use a p-type transistor and an n-type transistor coupled to each input of the NOR gate, in some embodiments, a schottky CMOS implementation of a two-input NOR gate uses an n-type SBD and a p-type transistor coupled to each input (replacing the n-type transistors of the existing CMOS implementation with the n-type SBD in the schottky CMOS implementation). As the number of inputs in NOR gates increases, the efficiency obtained by replacing transistors with SBDs also increases.

Fig. 5 is a circuit diagram of an eight-input schottky CMOS NOR gate according to some embodiments. The eight-input Schottky CMOS NOR gate includes eight n-type Schottky diodes 502-516 and a source follower tree 518 including eight n-type transistors 520-534. Transistors 520-534 in source follower tree 518 are connected in series (e.g., the drain node of transistor 520 is coupled to the source node of transistor 524, the drain node of transistor 524 is coupled to the source node of transistor 528, etc.). Input a0 is coupled to the anode of n-type SBD 502 and the gate node of p-type transistor 520. Input a1 is coupled to the anode of n-type SBD 504 and the gate node of p-type transistor 522. Input a2 is coupled to the anode of n-type SBD 506 and the gate node of p-type transistor 524. Input a3 is coupled to the anode of n-type SBD 508 and the gate node of p-type transistor 526. Input a4 is coupled to the anode of n-type SBD 510 and the gate node of p-type transistor 528. Input a5 is coupled to the anode of n-type SBD 512 and the gate node of p-type transistor 530. Input a6 is coupled to the anode of n-type SBD 514 and the gate node of p-type transistor 532. Input a7 is coupled to the anode of n-type SBD 516 and the gate node of p-type transistor 534.

The cathode of SBD 502-516 is coupled to the gates of

result transistors

536 and 538. The result transistor 536 is an n-type transistor and the result transistor 538 is a p-type transistor. Output 540 is coupled to the non-gate nodes of

result transistors

536 and 538. In particular, output 540 is coupled to the drain node of n-type transistor 536, while output 540 is coupled to the drain node of p-type transistor 538.

In some embodiments, an eight-input schottky CMOS NOR gate includes feedback logic that receives an output signal as an input at the gate nodes of n-type transistor 542 and p-type transistor 544.

It will be appreciated that the scale shown with respect to fig. 4-5 may be extended to other numbers of NOR gate inputs. For each additional input, an additional SBD is coupled to the additional input, and an additional source follower transistor complementary to the SBD (e.g., a p-type transistor complementary to the n-type SBD) is added to the source follower tree (e.g., as shown by source follower tree 406 of fig. 4 or source follower tree 518 of fig. 5). The additional input is coupled to the additional SBD (e.g., to the cathode of the n-type SBD) and to the gate node of the additional source follower transistor. The additional SBDs are coupled (e.g., the anode of the p-type SBD) to the gate nodes of a set of result transistors (e.g., as shown by

result transistors

414 and 416 of fig. 4 or result

transistors

536 and 538 of fig. 4).

For example, a four-input Schottky CMOS NOR gate includes four inputs A0-A3, four n-type SBDs (e.g., configured as shown by

SBD

502 and 508 of FIG. 5) and four p-type transistors (e.g., transistors shown as 520, 522, 524, and 526 of FIG. 5 connected in series).

In some embodiments, a schottky CMOS NOR gate includes multiple inputs, such as twelve inputs, between two and sixteen inputs.

Fig. 6 is a circuit diagram of an 8-input CMOS NOR gate. A CMOS 8-input NOR gate requires four two-

input NAND gates

602, 604, 606, and 608, two-

input NAND gates

610 and 612, a two-input NOR gate 614, and

inverters

616 and 618. Compared to the schottky CMOS eight-input NOR gate described with respect to fig. 5, the stacked configuration of NOR gates 602-608

feeding NAND gates

610 and 612, which in turn feed NOR gate 614, as shown in fig. 6, requires increased power and increased supply current, and results in increased layout area, increased switching time, and increased propagation delay.

Fig. 7 is a circuit diagram of a schottky CMOS implementation of a 4-to-1 multiplexer circuit (MUX) according to some embodiments. The schottky CMOS MUX couples input I1 to the gate nodes of p-type SBD 702 and n-type transistor 704. Inputs I2, I3, and I4 are similarly coupled to the gate nodes of the p-type SBD and n-type transistors, respectively. The outputs of p-type SBD 702 and transistor 704 are coupled to n-type SBD 706 and p-type transistor 708. The SBD and the output of the transistors receiving inputs from I2, I3, and I4 are similarly coupled to n-type SBD and p-type transistors, respectively. The output of the n-type SBD is coupled to the gate node of the p-type result transistor 710 and the gate node of the n-type result transistor 712. The output of the resulting transistor is received by output 714.

Fig. 8 shows a CMOS implementation of a 4-to-1 multiplexer circuit.

In some embodiments, the schottky CMOS logic described with respect to fig. 1, 2, 4, 5, and/or 7 is configured for asynchronous (e.g., static) operation. For example, the size of one or more components is selected such that the operation of the circuit is asynchronous or substantially asynchronous. In some embodiments, the size of one or more components of the schottky CMOS logic is selected to reduce and/or minimize switching noise immunity.

In some embodiments, one or more SBDs of the schottky CMOS logic described with respect to fig. 1, 2, 4, 5, and/or 7 have a threshold forward voltage that is lower than a threshold forward voltage of a transistor having a gate coupled to the SBD (e.g., where both the transistor and the SBD are coupled to inputs of the gate). For example, referring to fig. 1, in some embodiments, SBD 102 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 108 and/or SBD 104 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 110. Referring to fig. 2, in some embodiments, SBD 202 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 220, SBD 204 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 222, and/or SBD 206 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 224, and so on. Referring to fig. 4, in some embodiments SBD 402 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 408 and/or SBD 404 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 410. Referring to fig. 5, in some embodiments, SBD 502 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 520, SBD 504 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 522, and/or SBD 506 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 524, and so on. Referring to fig. 7, in some embodiments SBD 702 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 704.

Fig. 9 is a graph comparing layout area of a NAND gate implemented using schottky CMOS (e.g., as shown in fig. 1-2) to a NAND gate implemented using CMOS (e.g., as shown in fig. 3) according to some embodiments. As can be seen from fig. 9, the area of the schottky CMOS NAND gate increases at a lower rate than the area of the CMOS NAND gate increases as the number of inputs increases. FIG. 9 shows that the layout area required for a four-input Schottky CMOS NAND gate is less than 2.0 μm²This is significantly less than the area required for a four-input CMOS NAND gate. With CMOS NAN having the same number of inputsThe reduction in area required for a schottky CMOS NAND gate with three or more inputs compared to a D gate is due to, for example, a reduced number of signal lines and/or circuit nets required to implement the logic, and the relatively small size of the source follower tree (e.g., as shown in 106, 218, 406, and 518) compared to the layout of the CMOS NAND gate (e.g., as shown in fig. 3 and 6).

Fig. 10 is a graph comparing Root Mean Square (RMS) power consumption of a NAND gate implemented using schottky CMOS (e.g., as shown in fig. 1-2) to power consumption of a NAND gate implemented using CMOS (e.g., as shown in fig. 3) in accordance with some embodiments. As can be seen from fig. 10, the power required for the schottky CMOS NAND gate increases at a lower rate than the power required for the CMOS NAND gate increases as the number of inputs increases. Fig. 10 shows that the RMS power requirement of a four-input schottky CMOS NAND gate is less than 50.0 microwatts, which is significantly lower than the power required for a four-input CMOS NAND gate.

Fig. 11 is a graph comparing the propagation delay of a NAND gate implemented using schottky CMOS (e.g., as shown in fig. 1-2) to the propagation delay of a NAND gate implemented using CMOS (e.g., as shown in fig. 3) according to some embodiments. Fig. 11 shows that the four-input schottky CMOS NAND gate has a propagation delay of less than 80 picoseconds, which is significantly less than the propagation delay of the four-input CMOS NAND gate.

As can be seen from fig. 11, the propagation delay of the CMOS NAND gate shows a particularly significant increase as the number of inputs increases from three to four and from six to seven. The significant increase in required area, power consumption and propagation delay that occurs in CMOS implementations of NAND gates as the number of inputs increases can be understood with reference to fig. 12A-12G.

FIG. 12A shows a two-input NAND logic implemented using a single two-input NAND gate 1202. FIG. 12B shows a three-input NAND logic implemented using a single three-input NAND gate 1204.

FIG. 12C shows a four-input NAND logic implemented using two

NAND gates

1206 and 108 and a NOR gate 1210. The use of two NAND gates 1206 and 1208 (instead of the single NAND gate 1204 of fig. 12B) and the addition of NOR gate 1210 increases the propagation delay through the circuit when the number of NAND inputs increases from three inputs as shown in fig. 12B to four inputs as shown in fig. 12C. As shown in fig. 11, this increase is reflected in a jump in propagation delay from less than 80 picoseconds for three-input CMOS NAND to more than 120 picoseconds for four-input CMOS NAND.

12D-12E show five-input and six-input CMOS NAND gates, respectively. Similar to the four-input CMOS NAND shown in fig. 12C, five-input and six-input CMOS NAND gates feed the outputs of two NAND gates to the NOR gate. The CMOS NAND gate of figure 12D feeds the outputs of

NAND gates

1212 and 1214 to NOR gate 1216. The CMOS NAND gate of FIG. 12E feeds the outputs of

NAND gates

1218 and 1220 to NOR gate 1222.

Fig. 12F shows a seven-input NAND logic implemented using three

NAND gates

1224, 1226, and 1228 and NOR gate 1230. Using three NAND gates (1224, 1226, and 1228) instead of the two NAND gates (1218, 1220) of fig. 12E increases the propagation delay through the circuit when the number of NAND inputs increases from six inputs as shown in fig. 12E to seven inputs as shown in fig. 12F. As shown in fig. 11, this increase is reflected in a jump in propagation delay from less than 140 picoseconds for a six-input CMOS NAND to nearly 180 picoseconds for a seven-input CMOS NAND.

Fig. 12G shows an eight-input CMOS NAND gate having a similar circuit structure to the eight-input CMOS NAND gate described with respect to fig. 3. The CMOS NAND gate of FIG. 12G feeds the outputs of

NAND gates

1232, 1234 and 1236 to NOR gate 1238.

As described above with respect to the CMOS NAND gates of fig. 12A-12G, increasing the number of inputs to the CMOS NAND gates requires increasing the number of NAND gates and/or adding NOR stages. In some embodiments (e.g., as described with respect to fig. 1-2 and 4-5), increasing the number of inputs of the schottky CMOS NAND gate includes increasing the number of SBDs and increasing the number of corresponding transistors in the source follower tree. In some embodiments, the schottky CMOS approach described herein results in lower increases in power consumption, layout area, and propagation delay as the number of logic inputs increases, as compared to the CMOS approach.

While specific embodiments are described above, it will be understood that it is not intended to limit the disclosure to these specific embodiments. On the contrary, the disclosure includes alternatives, modifications and equivalents as may be within the spirit and scope of the appended claims. Numerous specific details are set forth in order to provide a thorough understanding of the subject matter presented herein. It will be apparent, however, to one of ordinary skill in the art that the present subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments.

The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in the description of the present disclosure and appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is also to be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises", "comprising", "includes" and/or "including", when used in this specification, specify the presence of stated features, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, operations, elements, components, and/or groups thereof.

As used herein, the term "if" can be interpreted to mean that the stated prerequisite is true "when" or "at … …" or "in response to a determination" or "in accordance with a determination" or "in response to a detection," depending on the context. Similarly, the phrase "if it is determined that a prerequisite of a statement is true" or "if a prerequisite of a statement is true" or "when a prerequisite of a statement is true" may be interpreted as that a prerequisite of a statement is true "when determining … …" or "in response to a determination" or "in accordance with a detection" or "in response to a detection", depending on the context.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. An integrated circuit implementing a NAND gate system, the integrated circuit comprising:

a first input coupled to a cathode of a first Schottky diode;

x additional inputs coupled to x respective cathodes of x additional schottky diodes, wherein x is an integer;

an inverter having an inverter input and an inverter output, wherein:

the integrated circuit is configured for asynchronous operation;

the inverter is biased between a high voltage power supply and a low voltage power supply;

the inverter input is coupled to an anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes; and is

The inverter output is coupled to an output of the NAND gate system; and

a source follower tree comprising one or more N-type transistors, wherein the source follower tree is biased between the high voltage power supply and the inverter input.

2. The integrated circuit of claim 1, wherein:

the inverter is a CMOS inverter including a p-type transistor and a first n-type transistor;

the first n-type transistor comprises a gate node coupled to the anode of the first Schottky diode and the x respective anodes of the x additional Schottky diodes; and is

The p-type transistor includes a gate node coupled to the anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes.

3. The integrated circuit of claim 2, wherein a threshold forward voltage of the first schottky diode is less than a threshold voltage of the first n-type transistor.

4. The integrated circuit of claim 2, wherein a threshold forward voltage of the first schottky diode is less than a threshold voltage of the p-type transistor.

5. The integrated circuit of claim 1, wherein the inverter comprises a first inverter having a first inverter input and a first inverter output, the inverter further comprising:

a second inverter having a second inverter input and a second inverter output, wherein the second inverter input is coupled to the first inverter output of the first inverter and the second inverter output is coupled to the first inverter input of the first inverter and anodes of the first Schottky diode and the x additional Schottky diodes.

6. The integrated circuit of claim 1, further comprising:

a second n-type transistor comprising a gate node coupled to the cathode of the first Schottky diode; and

x additional n-type transistors comprising x respective gate nodes coupled to the x respective cathodes of the x additional Schottky diodes.

7. The integrated circuit of claim 6, wherein a threshold forward voltage of the first schottky diode is less than a threshold voltage of the second n-type transistor.

8. The integrated circuit of claim 6, wherein:

a threshold forward voltage of a respective Schottky diode of the x additional Schottky diodes is less than a threshold forward voltage of a respective n-type transistor of the x additional n-type transistors, and

a respective additional input of the x additional inputs is coupled to the respective schottky diode and the respective n-type transistor.

9. The integrated circuit of claim 6, wherein the x additional n-type transistors further comprise a third n-type transistor connected in series with the second n-type transistor.

10. The integrated circuit of claim 1, wherein x is greater than or equal to four.

11. The integrated circuit of claim 1, wherein the integrated circuit has a propagation delay of less than 80 picoseconds and requires a Root Mean Square (RMS) power of less than 50 microwatts.

12. The integrated circuit of claim 1, wherein the first schottky diode is a p-type schottky diode.

13. An integrated circuit implementing a NOR gate system, the integrated circuit comprising:

a first input coupled to an anode of a first Schottky diode;

x additional inputs coupled to x respective anodes of x additional schottky diodes, where x is an integer;

an inverter having an inverter input and an inverter output, wherein:

the integrated circuit is configured for asynchronous operation;

the inverter input is coupled to the cathode of the first schottky diode and x respective cathodes of the x additional schottky diodes; and is

The inverter output is coupled to an output of the NOR gate system; and

a source follower tree comprising one or more P-type transistors, wherein the source follower tree is biased between the inverter input and the low voltage power supply.

14. The integrated circuit of claim 13, wherein:

the inverter is a CMOS inverter including a first p-type transistor and an n-type transistor;

the first p-type transistor comprises a gate node coupled to the cathode of the first Schottky diode and the x respective cathodes of the x additional Schottky diodes; and is

The n-type transistor includes a gate node coupled to the cathode of the first Schottky diode and the x respective cathodes of the x additional Schottky diodes.

15. The integrated circuit of claim 13, further comprising:

a second p-type transistor comprising a gate node coupled to the anode of the first Schottky diode; and

x additional p-type transistors comprising x respective gate nodes coupled to the x respective anodes of the x additional Schottky diodes.

16. The integrated circuit of claim 15, wherein a threshold forward voltage of the first schottky diode is less than a threshold voltage of the second p-type transistor.

17. The integrated circuit of claim 15, wherein:

a threshold forward voltage of a respective Schottky diode of the x additional Schottky diodes is less than a threshold forward voltage of a respective p-type transistor of the x additional p-type transistors, an

A respective additional input of the x additional inputs is coupled to the respective schottky diode and the respective p-type transistor.

18. The integrated circuit of claim 13, wherein the first schottky diode is an N-type schottky diode.