CN113451532B

CN113451532B - Light-emitting device, array substrate, display panel and pixel circuit

Info

Publication number: CN113451532B
Application number: CN202110730298.1A
Authority: CN
Inventors: 孙大卫; 王宏宇; 蔡明瀚; 张先平; 许瑾; 魏现鹤; 梁倩倩
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2022-11-29
Anticipated expiration: 2041-06-29
Also published as: CN113451532A

Abstract

The application discloses light emitting device, array substrate, display panel and pixel circuit, light emitting device include second electrode, luminescent layer and the first electrode that stacks up the setting, and light emitting device still includes: and the charge storage part is arranged on one side of the first electrode, which is far away from the light-emitting layer, is insulated from the first electrode, at least partially overlaps with the orthographic projection of the first electrode on the light-emitting layer, and is used for storing charges. The control capability of the TFT on the current in the low gray scale state can be improved.

Description

Light-emitting device, array substrate, display panel and pixel circuit

Technical Field

The application relates to the technical field of display, in particular to a light-emitting device, an array substrate, a display panel and a pixel circuit.

Background

Organic Light Emitting Diodes (OLEDs), as a novel display technology, have the advantages of high color gamut, foldability, fast response speed, and the like, so the market share of the OLED display panel increases year by year.

With the rapid development of OLED materials, the device efficiency of OLED display panels has been increasing year by year and the power consumption has been decreasing year by year in recent years. With the improvement of device efficiency, the current of the low-gray-scale screen body is also lower and lower, which leads to the difficulty of current control of a Thin Film Transistor (TFT) to be further increased. Even if a weak current is injected into the anode by the TFT, the anode potential of the current OLED device can rapidly rise and reach the turn-on voltage to emit light, which is a great challenge to the improvement of low gray scale image quality and the turn-off of the black screen.

Disclosure of Invention

The embodiment of the application provides a light-emitting device, an array substrate, a display panel and a pixel circuit.

In a first aspect, an embodiment of the present application provides a light emitting device, including a second electrode, a light emitting layer, and a first electrode, which are stacked, the light emitting device further including: and the charge storage part is arranged on one side of the first electrode, which is far away from the light-emitting layer, is insulated from the first electrode, at least partially overlaps with the orthographic projection of the first electrode on the light-emitting layer, and is used for storing charges.

According to the foregoing embodiments of the first aspect of the present application, the light emitting device further includes: and a first dielectric layer disposed between the first electrode and the charge storage portion, the first dielectric layer being capable of allowing tunneling of charges when a potential difference is formed between the first electrode and the charge storage portion, the charge storage portion being for trapping and storing charges injected to the first electrode.

According to any of the preceding embodiments of the first aspect of the present application, the charge storage section comprises one charge storage block, an orthographic projection of the charge storage block on the light emitting layer at least partially overlaps with an orthographic projection of the first electrode on the light emitting layer; or the charge storage part comprises a plurality of charge storage blocks which are arranged in a stacking mode in the thickness direction of the light-emitting device, any two adjacent charge storage blocks are arranged in an insulating mode through the second dielectric layer, and orthographic projections of the any two adjacent charge storage blocks on the light-emitting layer at least partially overlap.

According to any of the preceding embodiments of the first aspect of the present application, the orthographic projection of the charge storage blocks on the light emitting layer completely overlaps with the orthographic projection of the first electrodes on the light emitting layer.

According to any of the preceding embodiments of the first aspect of the present application, the thickness of the charge storage block is in the range of 1nm to 1000nm.

According to any of the preceding embodiments of the first aspect of the present application, the material of the charge storage block is selected to have a conductivity of more than 10 ^-8 S/cm of material.

According to any of the preceding embodiments of the first aspect of the present application, the material of the charge storage block comprises a semiconductor material.

According to any of the preceding embodiments of the first aspect of the present application, the material of the charge storage block comprises at least one of metal nanoparticles, quantum dot material and ambipolar material.

According to any one of the preceding embodiments of the first aspect of the application, the nano-metallic particles comprise at least one of gold, copper and silver; the quantum dot material comprises at least one of zinc selenide, zinc sulfide and perovskite; the bipolar material includes at least one of pentacene and tin oxide.

According to any of the preceding embodiments of the first aspect of the present application, the first dielectric layer is capable of allowing charge tunneling when a potential difference between the first electrode and the charge storage reaches a first predetermined value, the first predetermined value being less than a turn-on voltage of the light emitting device.

According to any preceding embodiment of the first aspect of the present application, the first predetermined value is 0.05V-0.5V.

According to any of the preceding embodiments of the first aspect of the present application, the dielectric constant of the first dielectric layer is between 2 and 100.

According to any of the preceding embodiments of the first aspect of the present application, the thickness of the first dielectric layer is in the range of 2nm to 100nm.

According to any one of the preceding embodiments of the first aspect of the present application, the material of the first dielectric layer comprises at least one of aluminum oxide, hafnium oxide and silicon nitride.

According to any of the preceding embodiments of the first aspect of the present application, the charge storage section comprises a first plate connected to the fixed potential line, and the first plate and the first electrode form a first storage capacitor.

According to any one of the preceding embodiments of the first aspect of the present application, the first electrode is an anode and the second electrode is a cathode.

In a second aspect, an embodiment of the present application provides a display panel, including: an array substrate; and a light emitting device layer disposed on the array substrate, wherein the light emitting device layer includes a plurality of light emitting devices arranged in an array, and at least a portion of the plurality of light emitting devices is the light emitting device according to any of the foregoing embodiments.

According to the foregoing embodiments of the second aspect of the present application, the light emitting device includes a red light emitting device, a green light emitting device and a blue light emitting device arranged in an array, and the red light emitting device and/or the green light emitting device are the light emitting devices as described in any of the foregoing embodiments.

In a third aspect, an embodiment of the present application provides an array substrate, including a substrate, a driving device layer, and a first electrode that are stacked, where the array substrate further includes: and the charge storage part is arranged on one side of the first electrode facing the substrate and is insulated from the first electrode, the orthographic projection of the charge storage part on the substrate is at least partially overlapped with the orthographic projection of the first electrode on the substrate, and the charge storage part is used for storing charges.

According to the foregoing embodiments of the third aspect of the present application, the array substrate further includes: and a first dielectric layer disposed between the first electrode and the charge storage portion, the first dielectric layer being capable of allowing tunneling of charges when a potential difference is formed between the first electrode and the charge storage portion, the charge storage portion being for trapping and storing charges injected to the first electrode.

According to any of the preceding embodiments of the third aspect of the present application, the charge storage section comprises a charge storage block, an orthographic projection of the charge storage block on the substrate at least partially overlapping an orthographic projection of the first electrode on the substrate; or the charge storage part comprises a plurality of charge storage blocks which are arranged in a stacking mode in the thickness direction of the array substrate, any two adjacent charge storage blocks are arranged in an insulating mode through the second dielectric layer, and orthographic projections of the any two adjacent charge storage blocks on the substrate at least partially overlap.

According to any one of the foregoing embodiments of the third aspect of the present application, the charge storage section includes a first plate connected to the fixed potential line such that the first plate and the first electrode form a first storage capacitance.

According to any of the preceding embodiments of the third aspect of the present application, the voltage line is a first power supply line or a reference voltage signal line or a ground line.

In a fourth aspect, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the foregoing embodiments.

In a fifth aspect, an embodiment of the present application provides a pixel circuit, including: the device comprises a light emitting module, a driving module, a data writing module, a first storage module and a second storage module; the driving module and the light emitting module are connected in series between a first power line and a second power line, and the driving module is used for generating driving current; the light emitting module comprises a first electrode and a second electrode, and the second electrode is connected with the second power line; the second storage module is connected between the control end of the driving module and the first power line; the data writing module is connected between a data signal line and the driving module, and a control end of the data writing module is electrically connected with the second scanning signal line; the first storage module is connected between the first electrode of the light emitting module and a fixed potential line, and the first storage module is capable of storing charges injected to the first electrode of the light emitting module.

According to the foregoing embodiment of the third aspect of the present application, the first storage module includes a first storage capacitor, the light emitting module includes a light emitting diode, the second plate of the first storage capacitor is multiplexed with the first electrode of the light emitting diode, and the first plate of the first storage capacitor is connected to the fixed potential line.

According to any one of the foregoing embodiments of the third aspect of the present application, the pixel circuit further includes a light emission control module, a compensation module, a first reset module, and a second reset module, the light emission control module, the driving module, and the light emission module are connected in series between the first power line and the second power line, the light emission control module is configured to control the light emission of the light emission module, and a control terminal of the light emission control module is electrically connected to a light emission control signal line; the first reset module is connected between a reference voltage signal line and the second storage module, and a control end of the first reset module is electrically connected with a first scanning signal line; the second reset module is connected between the reference voltage signal line and the first electrode of the light-emitting module, and a control end of the second reset module is connected with the first scanning signal line; the compensation module is connected between the first reset module and the light emitting control module, and the control end of the compensation module is electrically connected with the second scanning signal line.

According to any of the preceding embodiments of the third aspect of the present application, the fixed potential line is a first power supply line or a second power supply line or a reference voltage signal line or a ground line.

The light emitting device, the array substrate and the display panel provided by the embodiment of the application, the light emitting device comprises a second electrode, a light emitting layer, a first electrode and an electric charge storage part which are arranged in a stacked mode, when voltage is applied to the first electrode and the second electrode, electric charges are gradually injected into the first electrode and accumulated between the first electrode and the second electrode, so that the electric potential of the first electrode gradually rises, the electric charge storage part is arranged on one side, far away from the light emitting layer, of the first electrode, when the electric charges are injected into the first electrode, part of the electric charges are stored by the electric charge storage part, the first electrode obstructs the rapid rise of the electric potential of the first electrode, the light emitting device can emit light only by supplying high current to the TFT, and the control capacity of the TFT on the current in a low-gray-level state is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, when taken in conjunction with the accompanying drawings, in which like or similar reference characters designate like or similar features, and which are not necessarily drawn to scale.

Fig. 1 is a schematic structural diagram of a light emitting device provided in an embodiment of the first aspect of the present application;

fig. 2 is a schematic structural diagram of a light emitting device provided in an embodiment of the first aspect of the present application;

fig. 3 is a schematic structural diagram of a light-emitting device according to another embodiment of the first aspect of the present application;

fig. 4 is a schematic structural diagram of a light-emitting device according to a further embodiment of the first aspect of the present application;

fig. 5 is a schematic structural diagram of a display panel according to an embodiment of a second aspect of the present application;

fig. 6 is a schematic structural diagram of an array substrate according to an embodiment of the third aspect of the present application;

fig. 7 is a schematic structural diagram of an array substrate according to an embodiment of the third aspect of the present application;

fig. 8 is a schematic structural diagram of an array substrate according to another embodiment of the third aspect of the present application;

fig. 9 is a schematic structural diagram of an array substrate according to yet another embodiment of the third aspect of the present application;

fig. 10 is a schematic structural diagram of a pixel circuit according to an embodiment of a fifth aspect of the present application;

fig. 11 is a schematic structural diagram of a pixel circuit according to another embodiment of the fifth aspect of the present application.

Description of reference numerals:

10-a light emitting device;

20-an array substrate;

110-a second electrode;

210-a light emitting layer;

310-a first electrode;

400-a drive device layer;

510-a substrate;

600-a charge storage portion; 610-a charge storage block; 620-a first plate;

710-a first dielectric layer; 720-a second dielectric layer; 730-an insulating layer;

810-a drive module; 820-data write module; 830-a light emitting module; 840-light emitting control module; 850-a compensation module; 860-a first reset module; 870-a second reset module; 880-a first memory module; 890-second memory module;

c1-first storage capacitor; c2-a second storage capacitor; a D-light emitting diode;

vh-fixed potential line; VDD-first power line; VSS-second power line; vdata — data signal line; s1, a first scanning signal line; s2, a second scanning signal line; vref-reference voltage signal line.

Detailed Description

Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the element, it can be directly on the other layer or region or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

With the rapid development of OLED materials, the device efficiency of OLED display panels in wide use today increases year by year, and the power consumption decreases year by year. With the improvement of the device efficiency, the current of the low gray scale screen body is lower and lower, so that the difficulty of the TFT in controlling the current is further increased.

In the conventional OLED device, even if a weak current is injected into the anode from the TFT, the potential of the anode can rapidly rise and reach a starting voltage to emit light, so that the low gray level image quality of the screen body is degraded, and the black picture of the screen body is difficult to turn off.

In order to solve the above problems, embodiments of a light emitting device, an array substrate, a method for manufacturing an array substrate, and a display panel are provided in the embodiments of the present application, and embodiments of the light emitting device, the array substrate, the display panel, and the pixel circuit will be described below with reference to fig. 1 to 11.

In a first aspect, embodiments of the present application provide a light emitting device, which may be an OLED light emitting device. The light emitting device has various light emitting colors, and the light emitting device may be a red light emitting device, a green light emitting device, or a blue light emitting device, which is not particularly limited in this application.

Fig. 1 is a schematic structural diagram of a light emitting device provided in an embodiment of the present application.

As shown in fig. 1, a light emitting device 10 provided in the embodiment of the present application includes a second electrode 110, a light emitting layer 210, a first electrode 310, and a charge storage portion 600, which are stacked. The charge storage portion 600 is disposed on a side of the first electrode 310 away from the light emitting layer 210 and is insulated from the first electrode 310, an orthogonal projection of the charge storage portion 600 on the light emitting layer 210 at least partially overlaps an orthogonal projection of the first electrode 310 on the light emitting layer 210, and the charge storage portion 600 is used for storing charges.

When a voltage is applied to the first electrode 310 and the second electrode 110, charges are gradually injected into the first electrode 310 and accumulated between the first electrode 310 and the second electrode 110, so that the potential of the first electrode 310 gradually rises, and since the charge storage portion 600 is disposed on the side of the first electrode 310 away from the light emitting layer 210, while charges are injected into the first electrode 310, a part of charges are stored by the charge storage portion 600, thereby preventing the potential of the first electrode 310 from rapidly rising, so that a higher current needs to be supplied to flow through the TFT to cause the light emitting device 10 to emit light, and the control capability of the TFT for current in a low gray-scale state is improved.

In the reset phase during driving, the potential of the first electrode 310 is reset to a low potential, and the charges stored in the charge storage 600 can flow to the low potential again, thereby being discharged, and returning the light emitting device 10 to the initial state.

When the light emitting device 10 displays a high gray scale by a high current flowing through the TFT, the charge storage portion 600 has a limited function, and the charge storage portion 600 has a limited influence on the rate of increase of the potential of the first electrode 310, so that most of the charges are recombined in the light emitting layer 210, and the light emitting efficiency of the light emitting device 10 at the high gray scale is not affected.

It should be noted that, for the OLED light-emitting device 10, after the charge injection, the device does not emit light immediately but charge accumulation is performed between the second electrode 110 and the first electrode 310, so that the potential of the first electrode 310 gradually rises, and when the potential rises to a certain threshold (i.e., the lighting voltage of the OLED), electrons and holes are recombined in the light-emitting layer 210 to generate visible light.

It is understood that the first electrode 310 may be an anode and the second electrode 110 may be a cathode, and the charge storage part 600 can prevent a rapid rise of the anode potential.

Fig. 2 is a schematic structural diagram of a light emitting device according to an embodiment of the first aspect of the present application.

There are various ways to prevent the first electrode 310 from rapidly rising in potential by storing charge. In some optional embodiments, the light emitting device may further include a first dielectric layer 710, the first dielectric layer 710 disposed between the first electrode 310 and the charge storage 600, the first dielectric layer 710 being capable of allowing charge tunneling when a potential difference is formed between the first electrode 310 and the charge storage 600, the charge storage 600 for capturing and storing charges injected to the first electrode 310. The first dielectric layer 710 has a certain insulating property, and when no voltage is applied to the light-emitting device 10, the first electrode 310 and the charge storage portion 600 are insulated from each other by the first dielectric layer 710.

When a voltage is applied to the first electrode 310 and the second electrode 110, charges are gradually injected into the first electrode 310 and accumulated between the first electrode 310 and the second electrode 110, so that the potential of the first electrode 310 gradually rises, a potential difference is formed between the first electrode 310 and the charge storage portion 600, the charges on the first electrode 310 start to tunnel through the first dielectric layer 710 and are captured by the charge storage portion 600 under the action of an electric field, the rapid rise of the potential of the first electrode 310 is prevented, a higher current needs to be supplied to flow through the TFT to enable the light-emitting device 10 to emit light, and the control capability of the TFT for the current in a low gray-level state is improved.

It is understood that, in the reset phase during the driving process, the potential of the first electrode 310 is reset to a low potential, the potential of the charge storage part 600 is higher than that of the first electrode 310, and the charges trapped by the charge storage part 600 can be discharged through the first dielectric layer 710 in a reverse direction, so that the light emitting device 10 returns to the initial state.

There are various structures of the charge storage part 600 capable of trapping charges, and in some alternative embodiments, as shown in fig. 2, the charge storage part 600 may include a charge storage block 610, the charge storage block 610 is used for trapping and storing charges carried by the first electrode 310, and an orthogonal projection of the charge storage block 610 on the light emitting layer 210 at least partially overlaps with an orthogonal projection of the first electrode 310 on the light emitting layer 210.

When charges are gradually injected into the first electrode 310 and accumulated between the first electrode 310 and the second electrode 110, a potential difference is formed between the first electrode 310 and the charge storage block 610, and under the action of an electric field, the charges on the first electrode 310 start to tunnel through the first dielectric layer 710 and are captured by the charge storage block 610, thereby preventing the rapid rise of the potential of the first electrode 310.

Fig. 3 is a schematic structural diagram of a light emitting device according to another embodiment of the first aspect of the present application.

In other alternative embodiments, the charge storage part 600 may include a plurality of charge storage blocks 610 stacked in the thickness direction of the light emitting device 10, any two adjacent charge storage blocks 610 are insulated by the second dielectric layer 720, and orthographic projections of any two adjacent charge storage blocks 610 on the light emitting layer 210 at least partially overlap. The plurality of stacked charge storage blocks 610 are stacked on the first electrode 310 side away from the light emitting layer 210, so that the charge storage amount of the charge storage portion 600 can be increased, the rising speed of the potential of the first electrode 310 can be further delayed, and the current controllability of the TFT in a low gray scale state can be improved.

The charge storage unit 600 includes a plurality of charge storage blocks 610 stacked, and the plurality of charge storage blocks 610 may be two charge storage blocks 610 or three or more charge storage blocks 610, which is not particularly limited in the present application.

Alternatively, as shown in fig. 3, the charge storage part 600 may include two charge storage blocks 610 stacked in the thickness direction of the light emitting device 10, the two charge storage blocks 610 are insulated by the second dielectric layer 720, and orthographic projections of the two charge storage blocks 610 on the light emitting layer 210 at least partially overlap.

For ease of understanding and illustration, the charge storage block 610 adjacent to the first dielectric layer 710 may be referred to as a first charge storage block, and the charge storage block 610 on the side of the second dielectric layer 720 remote from the light emitting layer 210 may be referred to as a second charge storage block.

When charges are gradually injected into the first electrode 310 and accumulated between the first electrode 310 and the second electrode 110, the potential of the first electrode 301 gradually rises, a potential difference is formed between the first electrode 310 and the charge storage portion 600, the charges on the first electrode 310 start to tunnel through the first dielectric layer 710 and are captured by the first charge storage block adjacent to the first dielectric layer 710 under the action of the electric field, a potential difference is formed between the first charge storage block and the second charge storage block along with the accumulation of the charges on the first charge storage block, the charges on the first charge storage block start to tunnel through the second dielectric layer 720 and are captured by the second charge storage block under the action of the electric field, and the second charge storage block increases the total charge storage amount of the charge storage portion 600, so that the rising speed of the potential of the first electrode 310 can be further delayed, and the controllability of the TFT on the current in the low gray scale state can be improved.

It is understood that the larger the charge storage amount of each charge storage block 610 is, the larger the total charge storage amount of the charge storage section 600 is, the larger its influence on the rising speed of the potential of the first electrode 301 is. The amount of charge stored in charge storage block 610 is related to the material, size, thickness, etc. of charge storage block 610.

In some alternative embodiments, the orthographic projection of the charge storage block 610 on the light emitting layer 210 completely overlaps with the orthographic projection of the first electrode 310 on the light emitting layer 210, which can maximize space utilization and prevent too little charge storage.

Alternatively, the thickness of the charge storage block 610 may range from 1nm to 1000nm.

There are a variety of materials that can be used for charge storage block 610. In alternative embodiments, charge storage block 610 may optionally have a conductivity greater than 10 ^-8 The S/cm material is made of a material with higher conductivity without a forbidden band, and charges can freely enter and exit, so that the charges can smoothly leave the charge storage block 610 when the first electrode is reset.

Alternatively, the material of the charge storage block 610 may include a semiconductor material having good charge trapping capability.

As a preferred embodiment, the charge storage block 610 may be made of metal nanoparticles or quantum dots, which have more dangling bonds, are easier to capture charges, and can store a large amount of charges.

Optionally, the nano-metal particles may include at least one of gold, copper, and silver; the quantum dot material may include at least one of zinc selenide, zinc sulfide, and perovskite.

Optionally, when the charge storage block 610 is made of metal nanoparticles or quantum dots, a coating method may be used to fabricate the charge storage block 610.

In some alternative embodiments, the charge storage block 610 may also be made of bipolar material, which also has a certain charge trapping capability. When the charge storage block 610 is made of bipolar material, it can be fabricated by sputtering, physical vapor deposition or chemical vapor deposition.

Alternatively, the ambipolar material may include at least one of pentacene and tin oxide.

It is understood that a certain potential difference needs to be overcome for charge tunneling on the first electrode 310 through the first dielectric layer 710, and for ease of understanding and illustration, the magnitude of the potential difference that needs to be overcome for charge tunneling through the first dielectric layer 710 can be denoted as a first predetermined value, i.e., the first dielectric layer 710 is capable of allowing charge tunneling when the potential difference between the first electrode 310 and the charge storage 600 reaches the first predetermined value.

Alternatively, the first predetermined value is smaller than the turn-on voltage of the light emitting device 10, so that the charge storage portion 600 can hinder the rapid rise of the anode potential before the light emitting device 10 emits light, and can better improve the control capability of the TFT for current in the low gray scale state.

The magnitude of the first predetermined value is not particularly limited, and may be selected according to the kind of the light emitting device 10, actual control requirements, and the like. Optionally, the first predetermined value ranges from 0.05V to 0.5V.

It is understood that the smaller the first predetermined value is, the smaller the amount of charge remaining in the charge storing section 600 when the potential of the first electrode 310 is reset is. Alternatively, when the potential of the first electrode 310 is reset, the charges trapped in the charge storage portion 600 may be drained by grounding the charge storage portion 600, so that no charges remain in the charge storage portion 600, and the present application is also within the protection scope.

The magnitude of the first predetermined value is related to the material, thickness, etc. of the first dielectric layer 710. In some alternative embodiments, the thickness of the first dielectric layer 710 may be set between 2nm and 100nm.

In some alternative embodiments, the first dielectric layer 710 may be made of a material with a dielectric constant of 2 to 100, i.e., the dielectric constant of the first dielectric layer 710 is in a range of 2 to 100, so that charges can tunnel more easily.

There are many materials for the first dielectric layer 710 that satisfy the above conditions, and optionally, the first dielectric layer 710 may be made of aluminum oxide, hafnium oxide, silicon nitride, or the like.

It is understood that when the charge storage 600 includes a plurality of charge storage blocks 610, two adjacent charge storage blocks 610 are isolated from each other by the second dielectric layer 720, and charges tunnel from one charge storage block 610 to the other charge storage block 610 through the second dielectric layer 720, a certain potential difference also needs to be overcome.

Alternatively, the thickness of the second dielectric layer 720 may be set between 2nm and 100nm.

Alternatively, the second dielectric layer 720 may be made of a material with a dielectric constant of 2 to 100, i.e., the dielectric constant of the second dielectric layer 720 is in a range of 2 to 100, so that charges can tunnel more easily.

In a preferred embodiment, the thickness of the second dielectric layer 720 may be less than the thickness of the first dielectric layer 710, and the dielectric constant of the second dielectric layer 720 may be greater than the first dielectric layer 710 to reduce the potential difference that needs to be overcome when charge is tunneled through the second dielectric layer 720. Of course, the thickness and material selected for the second dielectric layer 720 may be the same as the first dielectric layer 710 and are within the scope of the present application.

Fig. 4 is a schematic structural diagram of a light emitting device according to yet another embodiment of the first aspect of the present application.

The implementation manner of blocking the rapid rise of the potential of the first electrode 310 is not limited to the above-mentioned scheme, and in other alternative embodiments, the charge storage part 600 may include the first plate 620, an orthogonal projection of the first plate 620 on the light emitting layer 210 at least partially overlaps an orthogonal projection of the first electrode 310 on the light emitting layer 210, the first plate 620 may be disposed in insulation with the first electrode 310 through the insulation layer 730, and the first plate 620 and the first electrode 310 form a first storage capacitor C1.

When a voltage is applied to the first electrode 310 and the second electrode 110, charges are gradually injected into the first electrode 310 and accumulated between the first electrode 310 and the second electrode 110, and at the same time, charges are also accumulated on the first storage capacitor C1 formed by the first electrode 310 and the first plate 620, the first storage capacitor C1 prevents the first electrode 310 from rapidly rising in potential, so that a higher current needs to be supplied to flow through the TFT to enable the light-emitting device 10 to emit light, and the control capability of the TFT for current in a low gray-scale state is improved.

Alternatively, the first plate 620 may be connected to a fixed potential line, the fixed potential line may be a first power line or a second power line, or may also be a reference voltage signal line or a ground line, and the like, the first power line may be used to transmit a positive voltage, and the reference voltage signal line is used to transmit a negative voltage, as long as a constant voltage can be provided for the first plate 620, so that the first storage capacitor C1 can be formed between the first plate 620 and the first electrode 310, which are within the protection scope of the present application.

It is understood that the larger the charge storage amount of the first storage capacitor C1, the larger its influence on the rising speed of the potential of the first electrode 301. In some alternative embodiments, the orthographic projection of the first plate 620 on the light emitting layer 210 completely overlaps with the orthographic projection of the first electrode 310 on the light emitting layer 210, so that the space utilization can be maximized, and the charge storage capacity of the first storage capacitor C1 can be maximized.

In a second aspect, embodiments of the present application further provide a display panel, which may be an OLED display panel. Fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the second aspect of the present application.

The display panel provided by the embodiment of the application comprises an array substrate and a light-emitting device layer, wherein the light-emitting device layer is arranged on the array substrate, the light-emitting device layer comprises a plurality of light-emitting devices 10 arranged in an array, and at least part of the plurality of light-emitting devices 10 are the light-emitting devices 10 described in any one of the above embodiments.

Alternatively, a plurality of light emitting devices 10 of the light emitting device layer may adopt the structure of the light emitting device 10 of any of the above embodiments.

According to the display panel provided by the embodiment of the application, the charge storage part 600 capable of storing charges is arranged on the side of the first electrode 310 of each light emitting device 10 far away from the light emitting layer 210, so that the rapid rise of the potential of the first electrode 310 can be prevented, the control capability of the TFT on the current in the low gray scale state can be improved, and the uniformity of the brightness and the chromaticity and the stability of the image quality during the low gray scale display of the display panel can be improved.

Optionally, the array substrate is an existing array substrate, and includes a substrate 510 and a driving device layer 400, where the driving device layer 400 includes a plurality of pixel circuits.

In the display panel provided by the embodiment of the present application, the light emitting device layer may include a patterned charge storage layer including a plurality of charge storage portions 600.

In some alternative embodiments, the charge storage portion 600 may include one charge storage block 610, and may also include a plurality of charge storage blocks 610 stacked in the thickness direction of the light emitting device layer, and when the charge storage portion 600 includes a plurality of charge storage blocks 610, any two adjacent charge storage blocks 610 are insulated by the second dielectric layer 720.

Optionally, the orthographic projection of the first dielectric layer 710 on the light emitting surface of the light emitting device layer may cover the plurality of light emitting devices 10, and the first dielectric layers 710 of the light emitting devices 10 are arranged on the same layer and may be integrally manufactured, so that manufacturing templates can be reduced, and the manufacturing process is simplified.

Optionally, the orthographic projection of the second dielectric layer 720 on the light emitting surface of the light emitting device layer may cover the plurality of light emitting devices 10, and the second dielectric layers 720 of the light emitting devices 10 are arranged in the same layer and may be integrally manufactured, so that manufacturing templates can be reduced, and the manufacturing process is simplified.

In other alternative embodiments, the charge storage part 600 may include a first plate 620, the first plate 620 and the first electrode 310 may be insulated from each other by an insulating layer 730, and the first plate 620 is electrically connected to a fixed potential line such that the first plate 620 and the first electrode 310 form a first storage capacitor C1.

Optionally, the first plate 620 may be electrically connected to a first power line or a second power line or a reference voltage signal line or a ground line, the first power line may be used to transmit positive voltages, the reference voltage signal line is used to transmit negative voltages, and the first power line, the second power line and the reference voltage signal line can all provide a constant potential for the first plate 620, so that the first plate 620 and the first electrode 310 form the first storage capacitor C1. Of course, it is also within the scope of the present application to connect the first plate 620 to ground, or to electrically connect the first plate 620 with a high-level signal line or a low-level signal line.

In some alternative embodiments, the light emitting device layer may include red light emitting devices, green light emitting devices, and blue light emitting devices arranged in an array. Since the turn-on voltage of the blue light-emitting device is generally high, the turn-on voltage of the red light-emitting device is lower than that of the blue light-emitting device and that of the green light-emitting device, and the turn-on voltage of the green light-emitting device is lower than that of the blue light-emitting device, the red light-emitting device and/or the green light-emitting device may adopt the structure of the light-emitting device 10 of any of the above embodiments.

Alternatively, the red light-emitting device, the green light-emitting device, and the blue light-emitting device may each adopt the structure of the light-emitting device 10 of any of the above embodiments.

When the red light emitting device, the green light emitting device, and the blue light emitting device each adopt the structure of the light emitting device 10 of the above embodiment, alternatively, the charge storage amount of the charge storage portion 600 of the red light emitting device may be larger than the charge storage amount of the charge storage portion 600 of the green light emitting device, and the charge storage amount of the charge storage portion 600 of the green light emitting device may be larger than the charge storage amount of the charge storage portion 600 of the blue light emitting device.

Fig. 6 is a schematic structural diagram of an array substrate according to an embodiment of the third aspect of the present application.

In a third aspect, the embodiment of the present application provides an array substrate 20, which includes a substrate 510, a driving device layer 400, a charge storage portion 600, and a first electrode 310, which are stacked.

The charge storage part 600 is arranged on one side of the first electrode 310 facing the substrate 510 and is insulated from the first electrode 310, an orthographic projection of the charge storage part 600 on the substrate 510 is at least partially overlapped with an orthographic projection of the first electrode 310 on the substrate 510, and the charge storage part 600 is used for storing charges injected into the first electrode 310.

When the charges are gradually injected into the first electrode 310, the potential of the first electrode 310 gradually rises, and since the charge storage portion 600 is disposed on the side of the first electrode 310 facing the substrate 510, the charges are injected into the first electrode 310, and at the same time, part of the charges are stored by the charge storage portion 600, which prevents the potential of the first electrode 310 from rapidly rising, thereby improving the current control capability of the driving device in the low gray-scale state.

Fig. 7 is a schematic structural diagram of an array substrate according to an embodiment of the third aspect of the present application; fig. 8 is a schematic structural diagram of an array substrate according to another embodiment of the third aspect of the present application.

There are various ways to prevent the first electrode 310 from rapidly rising in potential by storing charge. In some optional embodiments, the array substrate 20 may further include a first dielectric layer 710, and the first dielectric layer 710 is disposed between the first electrode 310 and the charge storage part 600. The first electrode first dielectric layer 710 is capable of allowing charge tunneling when a potential difference is formed between the first electrode 310 and the charge storage 600, the charge storage 600 serving to capture and store charge injected to the first electrode 310.

When the charges are gradually injected into the first electrode 310, the potential of the first electrode 310 gradually rises, a potential difference is formed between the first electrode 310 and the charge storage portion 600, and under the action of the electric field, the charges on the first electrode 310 start to tunnel through the first dielectric layer 710 and are captured by the charge storage portion 600, which can prevent the rapid rise of the potential of the first electrode 310, thereby improving the current control capability of the driving device in the low gray scale state.

There are various structures of the charge storage part 600 capable of capturing charges, and in some alternative embodiments, as shown in fig. 7, the charge storage part 600 may include a charge storage block 610, the charge storage block 610 is used for capturing and storing charges carried by the first electrode 310, a forward projection of the charge storage block 610 on the substrate 510 at least partially overlaps with a forward projection of the first electrode 310 on the substrate 510, and the charges on the first electrode 310 are captured by the charge storage block 610 to prevent a rapid rise of the potential of the first electrode 310.

In other alternative embodiments, the charge storage part 600 may include a plurality of charge storage blocks 610 stacked in the thickness direction of the array substrate 20, any two adjacent charge storage blocks 610 are insulated by the second dielectric layer 720, and orthographic projections of any two adjacent charge storage blocks 610 on the substrate 510 at least partially overlap. The plurality of stacked charge storage blocks 610 are stacked on the first electrode 310 side facing the substrate 510, so that the charge storage amount of the charge storage portion 600 can be increased, the rising speed of the potential of the first electrode 310 can be further delayed, and the current controllability of the TFT in the low gray scale state can be improved.

As shown in fig. 8, the charge storage part 600 may include two charge storage blocks 610 stacked in the thickness direction of the array substrate 20, the two charge storage blocks 610 are insulated by a second dielectric layer 720, and orthographic projections of the two charge storage blocks 610 on the substrate 510 at least partially overlap.

Alternatively, the material of the charge storage block may comprise a semiconductor material, which has good charge trapping capability.

In some alternative embodiments, the charge storage block 610 may also be made of bipolar material, which also has a certain charge trapping capability. When the charge storage block 610 is made of a bipolar material, it can be formed by sputtering, physical vapor deposition, or chemical vapor deposition.

Alternatively, the thickness of the first dielectric layer 710 may be set between 2nm and 100nm.

Optionally, the first dielectric layer 710 may be made of a material with a dielectric constant of 2 to 100, so that charges can tunnel more easily. The first dielectric layer 710 may be made of aluminum oxide, hafnium oxide, silicon nitride, or the like.

Optionally, the substrate 510 may be a substrate 510 made of glass, and in some embodiments, may also be a substrate 510 made of Polyimide (PI) material or a material containing PI, so that the substrate 510 may be bent.

Fig. 9 is a schematic structural diagram of an array substrate according to yet another embodiment of the third aspect of the present application.

The implementation manner of blocking the rapid rise of the potential of the first electrode 310 is not limited to the above-mentioned scheme, and in other alternative embodiments, the charge storage portion 600 may include a first plate 620, an orthogonal projection of the first plate 620 on the substrate 510 at least partially overlaps an orthogonal projection of the first electrode 310 on the substrate 510, the first plate 620 and the first electrode 310 may be disposed in an insulating manner through an insulating layer 730, and the first plate 620 and the first electrode 310 form a first storage capacitor C1.

When the charges are gradually injected into the first electrode 310 and the potential of the first electrode 310 is gradually increased, a part of the charges are also accumulated on the first storage capacitor C1 formed by the first electrode 310 and the first plate 620, and the first storage capacitor C1 prevents the rapid increase of the potential of the first electrode 310, thereby improving the current control capability of the driving device in the low gray-scale state.

It is understood that the larger the charge storage amount of the first storage capacitor C1, the larger its influence on the rising speed of the potential of the first electrode 301. In some alternative embodiments, the orthographic projection of the first plate 620 on the substrate 510 and the orthographic projection of the first electrode 310 on the substrate 510 may completely overlap, which can maximize the use of space and ensure that the charge storage capacity of the first storage capacitor C1 is maximized.

Alternatively, the first plate 620 may be electrically connected to a fixed potential line capable of supplying a constant voltage, so that the first storage capacitor C1 can be formed between the first plate 620 and the first electrode 310.

There are various fixed potential lines capable of supplying a constant voltage to the first plate 620, and the fixed potential line may be a first power line or a second power line or a reference voltage signal line, that is, the first plate 620 may be electrically connected to the first power line or the second power line or the reference voltage signal line, the first power line may be used to transmit a positive voltage, and the reference voltage signal line may be used to transmit a negative voltage. Of course, it is also possible to connect the first plate 620 to the ground line, so that the voltage on the first plate 620 is always zero, or connect the first plate 620 to the high-level signal line or the low-level signal line, which is also within the protection scope of the present application.

In a fourth aspect, embodiments of the present application further provide a display panel, which may be an OLED display panel. The display panel provided by the embodiment of the present application includes the array substrate 20 according to any one of the above embodiments.

According to the display panel provided by the embodiment of the application, the driving device has stronger control capability on current in a low-gray-scale state, and the uniformity of brightness and chromaticity and the stability of image quality are higher during low-gray-scale display.

In a fifth aspect, an embodiment of the present application further provides a pixel circuit. Fig. 10 is a schematic structural diagram of a pixel circuit according to an embodiment of the fifth aspect of the present application. As shown in fig. 10, the pixel circuit provided in this embodiment of the present invention may include a light emitting module 830, a driving module 810, a data writing module 820, and a first storage module 880.

The driving module 810 and the light emitting module 830 are connected in series between a first power line VDD and a second power line VSS, the light emitting module 830 includes a first electrode 310 and a second electrode 110, and the second electrode 110 of the light emitting module 830 is connected to the second power line VSS. The driving module 810 is used for generating a driving current to drive the light emitting module 830 to emit light.

The data writing module 820 is connected between the data signal line Vdata and the first end of the driving module 810, and is configured to write a data voltage signal into the control end of the driving module 810. The control end of the data writing module 820 is electrically connected to the second scanning signal line S2. The data signal line Vdata is used to supply a data signal. The second scanning signal line S2 is used to supply a second scanning signal.

The second storage module is connected between the control terminal of the driving module 810 and the first power line VDD, and is used for storing the charges written to the control terminal of the driving module 810. Specifically, in a data writing stage during driving of the pixel unit by the pixel circuit, the data signal on the data signal line Vdata is transferred to the driving module 810 while the second storage module is charged. In the light emitting stage during the driving process, the second memory module may maintain the potential of the control terminal of the driving module 810 using the voltage charged in the data writing stage.

The first memory module 880 is connected between the first electrode 310 of the light emitting module 830 and the fixed potential line Vh, a first end of the first memory module 880 is electrically connected to the first electrode 310 of the light emitting module 830, a second end of the first memory module 880 is connected to the fixed potential line Vh, and the first memory module 880 can store charges injected to the first electrode 310 of the light emitting module 830. The fixed potential line Vh is used to supply a constant voltage signal.

In a light emitting stage during driving, the second memory module applies the voltage charged in the data writing stage to the first electrode 310 of the light emitting module 830, charges are gradually injected into the first electrode 310 of the light emitting module 830 and accumulated between the first electrode 310 and the second electrode 110 of the light emitting module 830, so that the potential of the first electrode 310 of the light emitting module 830 gradually rises, and the charges are also accumulated at the first memory module 880, the first memory module 880 blocks rapid rise of the potential of the first electrode 310 of the light emitting module 830, and when the potential of the first electrode 310 of the light emitting module 830 rises to the turn-on voltage of the light emitting module 830, the light emitting module 830 is turned on to start light emission.

The first storage module 880 stores the charges injected into the light emitting module 830 during the light emitting period, so that the rapid increase of the potential of the first electrode 310 of the light emitting module 830 can be prevented, and the driving module 810 can supply a higher current to enable the light emitting module 830 to emit light, thereby improving the current control capability of the pixel circuit in the low gray scale state.

Optionally, the first storage module 880 may include a first storage capacitor C1, the light emitting module 830 includes a light emitting diode, the second plate of the first storage capacitor C1 is connected to the first electrode 310 of the light emitting diode, and the first plate 620 of the first storage capacitor C1 is connected to the fixed potential line Vh. As a preferred embodiment, the second plate of the first storage capacitor C1 and the first electrode 310 of the light emitting diode D may be multiplexed.

It is understood that the pixel circuit may be formed on the substrate of the array substrate and constitute a driving device layer. Optionally, the first electrode 310 of the light emitting diode and the second plate of the first storage capacitor C1 may be multiplexed, that is, when a pixel circuit is formed, the first electrode 310 of the array substrate may be used as the second plate of the first storage capacitor C1.

It should be noted that the pixel circuit provided in the embodiment of the present application may be any one of a 2T1C circuit, a 7T2C circuit, or a 9T1C circuit. Wherein "2T" in "2T1C circuit" means 2 thin film transistors, and "1C" means 1 capacitor or a whole of a plurality of capacitors connected in parallel; the other "7T1C circuits", "7T2C circuits", "9T1C circuits", etc., are analogized. The following specifically describes a pixel circuit provided in an embodiment of the present application, taking a 7T1C circuit as an example.

In some alternative embodiments, the pixel circuit may include a light emitting module 830, a driving module 810, a data writing module 820, a compensation module 850, a light emitting control module 840, a first reset module 860, a second reset module 870, a first memory module 880, and a second memory module 890.

The driving module 810, the light emitting control module 840 and the light emitting module 830 are connected in series between a first power line VDD and a second power line VSS, and the second electrode 110 of the light emitting module 830 is connected to the second power line VSS. Specifically, the number of the light emitting control modules 840 may be two, one of which is connected in series between the first terminal of the driving module 810 and the first power line VDD, and the other of which is connected in series between the second terminal of the driving module 810 and the second power line VSS. The driving module 810 is used for generating a driving current to drive the light emitting module 830 to emit light. The control end of the light emission control module 840 is electrically connected to the light emission control signal line EM. It can be understood that, in the case that the number of the light emission control modules 840 is two, the control terminals of both the light emission control modules 840 are electrically connected to the light emission control signal line EM. In a light emitting stage of the driving process, the light emitting control module 840 is turned on under the control of the light emitting control signal, and transmits the driving current generated by the driving module 810 to the light emitting module 830, so that the light emitting module 830 emits light.

The data writing module 820 is connected between the data signal line Vdata and the control terminal of the driving module 810, and is configured to write a data voltage signal into the control terminal of the driving module 810. The control terminal of the data writing module 820 is electrically connected to the second scanning signal line S2. The data signal line Vdata is used to supply a data signal. The second scanning signal line S2 is used to supply a second scanning signal. In the data writing stage of the driving process, the data writing module 820 charges the second memory module 890 through the driving module 810 by using the data signal under the control of the second scan signal line S2.

The first reset module 860 is connected between the reference voltage signal line Vref and the second memory module 890, the control terminal of the first reset module 860 is electrically connected to the first scan signal line, the first terminal of the first reset module 860 is connected to the reference voltage signal line Vref, the second terminal of the first reset module 860 is connected to the second memory module 890, and the first reset module 860 is configured to transmit a signal on the reference voltage signal line Vref to the first terminal of the second memory module 890, so as to reset the first terminal of the second memory module 890.

The second reset module 870 is connected between the reference voltage signal line Vref and the first electrode 310 of the light emitting module 830, a first terminal of the second reset module 870 is connected to the reference voltage signal line Vref, a second terminal of the second reset module 870 is connected to the first electrode 310 of the light emitting module 830, and the second reset module 870 is configured to transmit a signal on the reference voltage signal line Vref to the first electrode 310 of the light emitting module 830, so as to reset the first electrode 310 of the light emitting module 830. The control terminal of the second reset module 870 may be electrically connected to the first scan signal line S1.

The compensation module 850 is connected between the first reset module 860 and the light emitting control module 840, and a control terminal of the compensation module 850 is electrically connected to the second scan signal line S2. The compensation module 850 may be used to compensate the threshold voltage of the driving module 810, so that the driving current generated by the driving module 810 is not affected by the threshold voltage of the driving module 810 itself, thereby improving the display uniformity.

The second memory module 890 is connected between the control terminal of the driving module 810 and the first power line VDD, and stores the charges written into the control terminal of the driving module 810. Specifically, the second memory module 890 may be charged during a data writing phase in the driving process of the pixel circuit to the pixel unit. In the light emitting stage during the driving process, the second memory module 890 may maintain the potential of the control terminal of the driving module 810 using the voltage charged in the data writing stage.

The first memory module 880 is connected between the first electrode 310 of the light emitting module 830 and the fixed potential line Vh, a first end of the first memory module 880 is connected to the first electrode 310 of the light emitting module 830, a second end of the first memory module 880 is connected to the fixed potential line Vh, and the fixed potential line Vh is used to provide a constant voltage signal to the second end of the first memory module 880. The first storage module 880 is used to store the charges injected to the first electrode 310 of the light emitting module 830 during the light emitting period to prevent the rapid rise of the potential of the first electrode 310 of the light emitting module 830.

The fixed potential line Vh is various, and this is not particularly limited in the present application. In some alternative embodiments, the fixed potential line Vh may be selected as the reference voltage signal line Vref, and as shown in fig. 11, the first memory module 880 may be connected between the reference voltage signal line Vref and the first electrode 310 of the light emitting module 830. Specifically, in the light emitting stage during driving, the light emitting control module 840 is turned on, the second memory module 890 is to apply the voltage charged in the data writing stage to the first electrode 310 of the light emitting module 830, charges are gradually injected into the first electrode 310 of the light emitting module 830 and accumulated between the first electrode 310 and the second electrode 110 of the light emitting module 830, so that the potential of the first electrode 310 of the light emitting module 830 gradually rises, and charges are also accumulated at the first memory module 880, the first memory module 880 blocks the rapid rise of the potential of the first electrode 310 of the light emitting module 830, and when the potential of the first electrode 310 of the light emitting module 830 rises to the turn-on voltage of the light emitting module 830, the light emitting module 830 is turned on to start light emission. In the reset phase, the second reset module 870 transmits a signal on the reference voltage signal line Vref to the first electrode 310 of the light emitting module 830 and the first terminal of the first memory module 880 to simultaneously reset the first electrode 310 of the light emitting module 830 and the first terminal of the first memory module 880, reset the first electrode 310 of the light emitting module 830 and the first memory module 880 to a low potential, and the charge accumulated at the first memory module 880 flows to the low potential to be discharged.

In the embodiment of the present application, the pixel circuit may be implemented by a transistor, a capacitor, and the like, and the transistor may be a P-type transistor or an N-type transistor, which is not particularly limited herein. For convenience of explanation, a specific pixel circuit will be described below by taking a P-type transistor as an example. Fig. 11 also shows specific structures of the driving module 810, the data writing module 820, the light-emitting control module 840, the first reset module 860, the second reset module 870, the compensation module 850, the first memory module 880, and the second memory module 890 in the above embodiments.

As shown in fig. 11, the first storage module 880 may include a first storage capacitor C1, and the light emitting module 830 includes a light emitting diode D. The second plate of the first storage capacitor C1 is connected to the first electrode 310 of the led D, and one plate of the first storage capacitor C1 is connected to the reference voltage signal line Vref.

The driving module 810 may include a first transistor T1; the second memory module 890 includes a second storage capacitor C2; the data writing module 820 includes a second transistor T2, and the compensation module 850 includes a third transistor T3; the light emission control module 840 includes a fourth transistor T4 and a fifth transistor T5; the first reset module 860 includes a sixth transistor T6; the second reset module 870 includes a seventh transistor T7.

A first pole of the second transistor T2 is connected to the data signal line Vdata, a second pole of the second transistor T2 is connected to a first pole of the first transistor T1 and a second pole of the fourth transistor T4, and a gate of the second transistor T2 is connected to the second scan signal line S2.

A first pole of the third transistor T3 is connected to a first pole of the fifth transistor T5, a second pole of the third transistor T3 is connected to a first pole of the second storage capacitor C2, and a gate of the third transistor T3 is connected to the second scanning signal line S2.

A first electrode of the fourth transistor T4 is connected to the first power line VDD and a second electrode of the second storage capacitor C2, a second electrode of the fourth transistor T4 is connected to the first electrode of the first transistor T1, and a gate electrode of the fourth transistor T4 is connected to the emission control signal line EM.

A first pole of the fifth transistor T5 is connected to the second pole of the first transistor T1, a second pole of the fifth transistor T5 is connected to the first electrode 310 of the light emitting diode D, and a gate of the fifth transistor T5 is connected to the emission control signal line EM.

A gate of the sixth transistor T6 is connected to the first scan signal line S1, a first pole of the sixth transistor T6 is connected to the reference voltage signal line Vref, and a second pole of the sixth transistor T6 is connected to a first pole of the second storage capacitor C2 and a second pole of the third transistor T3.

A gate of the seventh transistor T7 is connected to the first scanning signal line S1, a first pole of the seventh transistor T7 is connected to the reference voltage signal line Vref, and a second pole of the seventh transistor T7 is connected to the first electrode 310 of the light emitting diode D.

A first pole of the second storage capacitor C2 is connected to the gate of the first transistor T1, and a second pole of the second storage capacitor C2 is connected to the first power line VDD.

The second electrode 110 of the light emitting diode D is connected to a second power line VSS. Illustratively, the light emitting diode D may be an organic light emitting diode. Of course, the led D may be other types of leds. The first electrode 310 of the light emitting diode D may be an anode, and the second electrode 110 of the light emitting diode D may be a cathode. The second power line VSS may be used to provide a low level signal; in some examples, the second power line VSS may be a ground terminal, which is not limited herein.

Taking fig. 11 as an example, the driving timing of the pixel circuit includes three stages, a reset stage, a data writing stage, and a light emitting stage.

In the reset phase, signals on the emission control signal line EM and the second scanning signal line S2 are at a high level, and a signal on the first scanning signal line S1 is at a low level. The signal on the emission control signal line EM controls the fourth transistor T4 and the fifth transistor T5 to be turned off; the second scanning signal line S2 controls the second transistor T2 and the third transistor T3 to be turned off; the first scanning signal S1 controls the sixth transistor T6 to be turned on, and the reference voltage signal line Vref initializes the gate of the first transistor T1, ensuring that the first transistor T1 is in a conducting state at the data writing stage; the first scanning signal line S1 controls the seventh transistor T7 to be turned on, the reference voltage signal line Vref initializes the anode of the light emitting diode D, and the reference voltage signal line Vref initializes the first plate 620 of the first storage capacitor C1, so that the potential difference between the two electrodes of the first storage capacitor C1 is zero.

In the data writing period T2, the signals on the emission control signal line EM and the first scanning signal line S1 are at a high level, and the level on the second scanning signal line S2 is at a low level. The light emission control signal line EM controls the fourth transistor T4 and the fifth transistor T5 to be turned off; the first scanning signal line S1 controls the sixth transistor T6 and the seventh transistor T7 to be turned off; the second scan signal line S2 controls the second transistor T2 and the third transistor T3 to be turned on, so that the data signal on the data signal line Vdata is written into the gate of the first transistor T1 through the source and the drain of the first transistor T1, and the third transistor T3 performs threshold compensation on the threshold voltage of the first transistor T1.

In the light emission phase, the signals on the first scanning signal line S1 and the second scanning signal line S2 are at a high level, and the signal on the light emission control signal line EM is at a low level. The first scanning signal line S1 controls the sixth transistor T6 and the seventh transistor T7 to be turned off; the second scanning signal line S2 controls the second transistor T2 and the third transistor T3 to be turned off; the light emission control signal line EM controls the fourth transistor T4 and the fifth transistor T5 to be turned on, the driving current generated by the first transistor T1 is transmitted to the light emitting diode D, and the light emitting diode D is turned on to start light emission.

It can be understood that when the fourth transistor T4 and the fifth transistor T5 are turned on, the voltage applied by the first power line VDD is applied to the anode of the light emitting diode D and the second plate of the first storage capacitor C1, charges are gradually injected into the anode of the light emitting diode D and gradually increase the potential of the first electrode 310 of the light emitting module 830, and the charges are also accumulated at the second plate of the first storage capacitor C1, the first storage capacitor C1 prevents the anode of the light emitting diode D from rapidly increasing, and when the potential difference between the anode and the cathode of the light emitting diode D increases to the turn-on voltage of the light emitting diode D, the light emitting diode D is turned on to start emitting light.

The specific structure of the pixel circuit is not limited thereto, and in other alternative embodiments, the first memory module 880 may also be connected between the first electrode 310 of the light emitting module 830 and the first power line VDD; when the first storage module 880 includes the first storage capacitor C1 and the light emitting module 830 includes the light emitting diode D, the second plate of the first storage capacitor C1 is connected to the first electrode 310 of the light emitting diode D, and the first plate 620 of the first storage capacitor C1 is connected to the first power line VDD. As a preferred embodiment, the second plate of the first storage capacitor C1 and the first electrode 310 of the light emitting diode D may be multiplexed. Of course, it is also within the scope of the present application to ground the first plate 620 of the first storage capacitor C1.

It is understood that the pixel circuit may be formed on the substrate of the array substrate and constitute a driving device layer, and optionally, the first electrode 310 of the light emitting diode D and the second plate of the first storage capacitor C1 may be multiplexed, that is, the first electrode 310 of the array substrate may be used as the second plate of the first storage capacitor C1 when the pixel circuit is formed.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A light-emitting device comprising a second electrode, a light-emitting layer, and a first electrode which are provided in a stacked manner, the light-emitting device further comprising:

a charge storage unit which is provided in a stacked manner on a side of the first electrode away from the light-emitting layer and is insulated from the first electrode, an orthogonal projection of the charge storage unit on the light-emitting layer at least partially overlaps an orthogonal projection of the first electrode on the light-emitting layer, and the charge storage unit is used for storing charges; the charge storage section includes at least one charge storage block, a material of the charge storage block including at least one of a metal nanoparticle, a quantum dot material, and a bipolar material.

2. The light-emitting device according to claim 1, further comprising:

a first dielectric layer disposed between the first electrode and the charge storage portion, the first dielectric layer capable of allowing tunneling of charges when a potential difference is formed between the first electrode and the charge storage portion, the charge storage portion for capturing and storing charges injected to the first electrode.

3. The light-emitting device according to claim 2, wherein the charge storage portion comprises a charge storage block, and an orthogonal projection of the charge storage block on the light-emitting layer at least partially overlaps with an orthogonal projection of the first electrode on the light-emitting layer; or

The charge storage part comprises a plurality of charge storage blocks which are arranged in a stacked mode in the thickness direction of the light-emitting device, any two adjacent charge storage blocks are arranged in an insulated mode through a second dielectric layer, and orthographic projections of any two adjacent charge storage blocks on the light-emitting layer at least partially overlap.

4. The light-emitting device according to claim 3, wherein the thickness of the charge storage block is 1nm to 1000nm.

5. The light-emitting device according to claim 1, wherein the metal nanoparticles comprise at least one of gold, copper, and silver; the quantum dot material comprises at least one of zinc selenide, zinc sulfide, and perovskite; the bipolar material includes at least one of pentacene and tin oxide.

6. The light-emitting device according to claim 3, wherein the first dielectric layer is capable of allowing charge tunneling when a potential difference between the first electrode and the charge storage portion reaches a first predetermined value, the first predetermined value being less than a lighting voltage of the light-emitting device.

7. The light-emitting device according to claim 6, wherein the first predetermined value is 0.05V to 0.5V.

8. The light-emitting device according to claim 3, wherein the dielectric constant of the first dielectric layer is 2 to 100.

9. The light-emitting device according to claim 3, wherein the first dielectric layer has a thickness of 2nm to 100nm.

10. The light-emitting device according to claim 3, wherein a material of the first dielectric layer comprises at least one of aluminum oxide, hafnium oxide, and silicon nitride.

11. The light-emitting device according to claim 1, wherein the charge storage portion comprises a first plate connected to a fixed potential line, and the first plate and the first electrode form a first storage capacitor.

12. The light-emitting device according to claim 1, wherein the first electrode is an anode and the second electrode is a cathode.

13. A display panel, comprising:

an array substrate; and

a light emitting device layer disposed on the array substrate, the light emitting device layer comprising a plurality of light emitting devices arranged in an array, at least some of the plurality of light emitting devices being as claimed in any one of claims 1 to 12.

14. The display panel according to claim 13, wherein the light emitting device comprises a red light emitting device, a green light emitting device and a blue light emitting device arranged in an array, and the red light emitting device and/or the green light emitting device is the light emitting device according to any one of claims 1 to 12.

15. An array substrate, comprising a substrate, a driving device layer and a first electrode, wherein the substrate, the driving device layer and the first electrode are arranged in a stacked manner, the array substrate further comprising:

a charge storage unit, which is arranged on one side of the first electrode facing the substrate in a stacked manner and is insulated from the first electrode, wherein the orthographic projection of the charge storage unit on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate, and the charge storage unit is used for storing charges; the charge storage section includes at least one charge storage block, a material of the charge storage block including at least one of a metal nanoparticle, a quantum dot material, and a bipolar material.

16. The array substrate of claim 15, wherein the array substrate further comprises:

17. The array substrate of claim 15, wherein the charge storage portion comprises a charge storage block, and an orthogonal projection of the charge storage block on the substrate at least partially overlaps an orthogonal projection of the first electrode on the substrate; or

The charge storage part comprises a plurality of charge storage blocks which are stacked in the thickness direction of the array substrate, any two adjacent charge storage blocks are arranged in an insulating mode through a second dielectric layer, and orthographic projections of the any two adjacent charge storage blocks on the substrate are at least partially overlapped.

18. The array substrate of claim 15, wherein the charge storage part comprises a first plate connected to a fixed potential line such that the first plate and the first electrode form a first storage capacitor.

19. The array substrate of claim 18, wherein the fixed potential line is a first power line or a second power line or a reference voltage signal line or a ground line.

20. A pixel circuit, comprising: the device comprises a light emitting module, a driving module, a data writing module, a first storage module and a second storage module; wherein,

the driving module and the light-emitting module are connected in series between a first power line and a second power line, and the driving module is used for generating driving current;

the light emitting module comprises a first electrode and a second electrode, and the second electrode is connected with the second power line;

the second storage module is connected between the control end of the driving module and the first power line;

the data writing module is connected between a data signal line and the driving module, and a control end of the data writing module is electrically connected with the second scanning signal line;

the first storage module is connected between the first electrode of the light emitting module and a fixed potential line, the first storage module is capable of storing charges injected to the first electrode of the light emitting module, the first storage module comprises a first storage capacitor, and a first plate of the first storage capacitor is made of at least one of metal nanoparticles, quantum dot materials and bipolar materials.

21. The pixel circuit according to claim 20, wherein the light emitting module comprises a light emitting diode, the second plate of the first storage capacitor is multiplexed with the first electrode of the light emitting diode, and the first plate of the first storage capacitor is connected to the fixed potential line.

22. The pixel circuit according to claim 20, wherein the fixed potential line is the first power supply line or the second power supply line or a reference voltage signal line or a ground line.