CN113451469A - Light-emitting chip and preparation method thereof - Google Patents
Light-emitting chip and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 7
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- 238000009792 diffusion process Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 295
- 229910003437 indium oxide Inorganic materials 0.000 claims description 21
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- 238000005530 etching Methods 0.000 claims description 3
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000002096 quantum dot Substances 0.000 description 6
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides a light-emitting chip and a preparation method thereof, wherein the light-emitting chip comprises a substrate; the current diffusion layer, the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer are sequentially arranged on the substrate; the N-type semiconductor layer, the light emitting layer and the P-type semiconductor layer are partially arranged on the current diffusion layer in a manner of covering the current diffusion layer, and a step surface is formed on the current diffusion layer; a P electrode is arranged on the step surface; at least one ITO barrier layer is arranged on the N-type semiconductor layer; and an N electrode is arranged on the at least one ITO barrier layer. The light-emitting chip utilizes the characteristic that free metal simple substances in the tin paste have weak permeability in the ITO barrier layer, and at least one ITO barrier layer is arranged between the N electrode and the N-type semiconductor layer to prevent the free metal simple substances from permeating into the N-type semiconductor layer, so that the voltage of the light-emitting chip is more stable, the performance of the light-emitting chip is improved, and the service life of the light-emitting chip is prolonged.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a light-emitting chip and a preparation method thereof.
Background
At present, the package of a Light Emitting Diode (LED) chip is usually soldered by using a solder paste, and the solder paste has a strong penetrating action. The flip LED chip is characterized in that the P electrode and the N electrode are arranged on the same side, so that the thicknesses of the P electrode and the N electrode are different, wherein the N electrode is thinner, and solder paste is easy to permeate the N electrode to enter the N-type semiconductor layer when packaged, so that the forward voltage of the chip is higher, and even short circuit is caused.
Accordingly, the prior art is yet to be developed and improved.
Disclosure of Invention
In view of the above defects in the prior art, an object of the present invention is to provide a light emitting chip and a method for manufacturing the same, which are used to solve the technical problem that the current flip-chip LED chip is prone to penetrate into the N electrode, which results in a higher forward voltage of the chip and damages the chip.
In one aspect, the present invention provides a light emitting chip, including:
a substrate;
a current spreading layer disposed over the substrate;
a P-type semiconductor layer disposed over the current diffusion layer;
a light emitting layer disposed on the P-type semiconductor layer;
an N-type semiconductor layer disposed over the light emitting layer; the N-type semiconductor layer, the light emitting layer and the P-type semiconductor layer are arranged to partially cover the current diffusion layer so as to form a step surface on the current diffusion layer;
a P electrode disposed on the step surface of the current diffusion layer;
at least one ITO barrier layer arranged on the N-type semiconductor layer;
and the N electrode is arranged on the at least one ITO barrier layer.
In the above embodiment, the light emitting chip of the present invention utilizes the characteristic that the free metal simple substance in the solder paste has weak penetration ability in the ITO barrier layer, and at least one ITO barrier layer is disposed between the N electrode and the N-type semiconductor layer, so that the metal simple substance can be well prevented from penetrating into the N-type semiconductor layer, and on the other hand, because the ITO has good conductivity, the circuit communication between the N electrode and the N-type semiconductor layer is not affected.
Optionally, the ITO barrier layer includes indium oxide and tin oxide, and the mass percentage of indium oxide in the ITO barrier layer is 90% to 99%.
In the above embodiment, since the free metal in the solder paste permeates through the grain boundary in the ITO barrier layer, the grain boundary of the ITO barrier layer can be changed by changing the mass ratio of indium oxide and tin oxide in the ITO barrier layer, so as to adjust the blocking capability of the ITO barrier layer to the free metal in the solder paste.
Optionally, when at least two ITO barrier layers are disposed, the mass ratio of indium oxide to tin oxide in two adjacent ITO barrier layers is different.
In the above embodiment, because the ITO barrier layer is provided with the multilayer, the effect of blocking free metal simple substance in the tin cream can superpose by the multilayer ITO barrier layer, simultaneously because the quality proportion of indium oxide and tin oxide is different in two adjacent ITO barrier layers, the crystal orientation between two adjacent ITO barrier layers is different like this, the degree of difficulty that free metal simple substance in the tin cream diffuses another layer of ITO barrier layer from one layer of ITO barrier layer is bigger, the effect of blocking free metal simple substance in the tin cream by the ITO barrier layer that can be further.
Optionally, the thickness of the at least one ITO barrier layer is 60-100 nm.
In the above embodiment, since the thickness of the ITO blocking layer may affect both the blocking effect of the ITO blocking layer and the circuit conduction between the N electrode and the N-type semiconductor layer, the thickness of at least one ITO blocking layer may be selected to be 60 to 100nm by comprehensively considering the blocking effect of the ITO blocking layer and the circuit conduction between the N electrode and the N-type semiconductor layer.
Optionally, an area of an end face of the N electrode is larger than an area of an end face of the P electrode.
In the above embodiment, since the conductivity of ITO is weaker than that of the N electrode, in the case where an ITO barrier layer is provided between the N electrode and the N-type semiconductor layer, it is also necessary to compensate for the conductivity between the N electrode and the N-type semiconductor layer, and setting the area of the end face of the N electrode to be larger than the area of the end face of the P electrode makes it possible to more equalize the voltage and current between the N-type semiconductor layer and the P-type semiconductor layer of the light emitting chip.
Optionally, the light emitting layer comprises a quantum well layer.
In the above embodiments, the quantum well layer has excellent light emitting characteristics, and the light emitting chip can have better light emitting effect by using the quantum well layer as the light emitting layer.
Optionally, the light emitting chip further includes:
and an insulating layer covering the surfaces of the N-type semiconductor layer and the current diffusion layer and exposing the N electrode and the P electrode.
In the embodiment, the insulating layer covers the surfaces of the N-type semiconductor layer and the current diffusion layer, so that each layer of the light-emitting chip can be well isolated from the external environment, each layer is prevented from being oxidized and failed, and the service life of the device is prolonged.
Optionally, the light emitting chip further includes:
an adhesive layer disposed between the substrate and the current spreading layer.
In the above embodiment, since the surface of the substrate is relatively smooth, the bonding layer can improve the connection strength between the substrate and the current diffusion layer, so that the light-emitting chip is firmer.
On the other hand, the invention also provides a preparation method of the light-emitting chip, which comprises the following steps:
providing a substrate;
depositing a current diffusion layer, a P-type semiconductor layer, a light emitting layer and an N-type semiconductor layer on the substrate in sequence;
partially etching the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer to form a step surface on the current diffusion layer;
arranging a P electrode on the step surface of the current diffusion layer;
at least one ITO barrier layer is arranged on the N-type semiconductor layer;
and arranging an N electrode on the at least one ITO barrier layer.
In the embodiment, the light-emitting chip prepared by the method is simple in manufacturing process and convenient to operate, and the manufactured light-emitting chip has more stable voltage, good performance and long service life because the ITO barrier layer can prevent free metal simple substances in the solder paste from permeating into the N-type semiconductor layer.
Optionally, when at least two ITO barrier layers are disposed, the mass ratio of indium oxide to tin oxide in two adjacent ITO barrier layers is different.
In the above embodiment, the multilayer ITO barrier layers are stacked to more effectively prevent the free metal simple substance in the solder paste from permeating into the N-type semiconductor layer, and because the mass ratio of indium oxide to tin oxide in the two adjacent ITO barrier layers is different, the crystal orientation between the two adjacent ITO barrier layers is different, the difficulty of diffusing the free metal simple substance in the solder paste from one ITO barrier layer to the other ITO barrier layer is higher, and the effect of blocking the free metal simple substance in the solder paste by the ITO barrier layers can be further improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a light emitting chip according to an embodiment of the invention;
fig. 2 is a schematic cross-sectional view of a light emitting chip according to another embodiment of the invention;
fig. 3 is a flowchart of a method for manufacturing a light emitting chip according to an embodiment of the invention.
The reference numerals in the figures are as follows:
10-a substrate; 20-a current spreading layer; a 30-P type semiconductor layer; 40-a light emitting layer; a 50-N type semiconductor layer; 60-step surface; 70-P electrode; 80-ITO barrier layer; a 90-N electrode; 100-an insulating layer; 110-adhesive layer.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Referring to fig. 1, the present invention provides a light emitting chip including:
a substrate 10;
a current diffusion layer 20 disposed over the substrate 10;
a P-type semiconductor layer 30 disposed over the current diffusion layer 20;
a light emitting layer 40 disposed on the P-type semiconductor layer 20;
an N-type semiconductor layer 50 disposed over the light emitting layer 40; the N-type semiconductor layer 50, the light emitting layer 40 and the P-type semiconductor layer 30 are all arranged to partially cover the current diffusion layer 20 so as to form a step surface 60 on the current diffusion layer 20;
a P-electrode 70 provided on the step surface 60 of the current diffusion layer 20;
at least one ITO barrier layer 80 disposed on the N-type semiconductor layer 50;
an N electrode 90 disposed over the at least one ITO barrier layer 50.
In the above embodiment, the light emitting chip of the present invention utilizes the characteristic that the free metal in the solder paste has a weak penetration ability in the ITO blocking layer 80, and at least one ITO blocking layer 80 is disposed between the N electrode 90 and the N-type semiconductor layer 50, so that the metal can be well blocked from penetrating into the N-type semiconductor layer 50, and on the other hand, because the ITO has a good conductivity, the circuit communication between the N electrode 90 and the N-type semiconductor layer 50 is not affected.
In some embodiments, the substrate 10 includes a sapphire substrate, a glass substrate or a flexible substrate, but the invention is not limited thereto, and when the substrate 10 is a flexible substrate, the light emitting device is a flexible light emitting device, and can be used for manufacturing a flexible display.
In some embodiments, the current spreading layer 20 material may be a conductive material including, but not limited to, indium tin oxide, aluminum zinc oxide, zinc tin oxide, gallium zinc oxide, indium yttrium oxide, aluminum gallium arsenide, gallium phosphide nitride, gallium arsenide phosphide, indium zinc oxide, or diamond-like carbon thin films.
In some embodiments, the P-type semiconductor layer 30 includes, but is not limited to, a P-type nitride material layer, a P-type oxide material layer, a P-type phosphide material layer, and a doped P-type semiconductor material layer, and in one embodiment, the P-type semiconductor layer 30 includes a P-type gallium phosphide layer.
In some embodiments, the light emitting layer 40 includes a quantum dot layer or a quantum well layer. The quantum dot is a semiconductor material of nanometer level, and can emit light with specific frequency by applying a certain electric field or light pressure to the quantum dot, the frequency of the emitted light can change along with the change of the size, the color of the emitted light can be controlled by adjusting the size, the quantum well is a quantum dot with a special structure, the quantum well material has a quantum confinement effect, the quantum confinement effect can enable the semiconductor quantum well to present various unique electronic and photonic characteristics with wide application prospect, the light conversion unit manufactured by the quantum well can have a better light emitting effect, quantum dot particles or quantum well particles with different shapes, structures and sizes can convert light into light with different colors of other wavelengths under the irradiation of the light with specific wavelengths, and the light conversion effect of the light conversion layer can be improved by manufacturing the light conversion layer by adopting the quantum dot or the quantum well.
In some embodiments, the N-type semiconductor layer 50 includes, but is not limited to, an N-type organic semiconductor material layer or an N-type inorganic semiconductor material layer, and in one embodiment, the P-type semiconductor layer 30 includes an N-type silver phosphoiodide layer.
In certain embodiments, the N electrode 90 and the P electrode include, but are not limited to, metal electrodes including, but not limited to, nickel, copper, aluminum, gold, platinum, and zinc, and semiconductor material electrodes including, but not limited to, silicon, germanium, selenium, gallium arsenide, and indium antimonide, and in one embodiment, the N electrode 90 and the P electrode may be selected to be nickel electrodes because nickel has a strong barrier effect against free metal elements in a tin paste.
In some embodiments, when the ITO barrier layer 80 is provided with at least two layers, the mass ratio of indium oxide to tin oxide in two adjacent layers of the ITO barrier layer 80 is different. Because ITO barrier layer 80 is provided with the multilayer, the effect of blockking free metal simple substance in the multilayer ITO barrier layer 80 to the tin cream can superpose, simultaneously because the quality proportion of indium oxide and tin oxide is different in two adjacent ITO barrier layers 80, the crystal orientation between two adjacent ITO barrier layers 80 is different like this, the degree of difficulty that free metal simple substance in the tin cream spreads another layer ITO barrier layer 80 from one layer ITO barrier layer is bigger, the effect of blockking free metal simple substance in the tin cream of ITO barrier layer 80 that can be further is to the tin cream.
In some embodiments, the ITO barrier layer 80 includes indium oxide and tin oxide, and the indium oxide accounts for 90% to 99% of the ITO barrier layer 80 by mass. For example, the mass percentage of indium oxide may be 90%, 95%, and 97%, and the present invention is not limited thereto. Because the free metal simple substance in the tin paste permeates through the grain boundary in the ITO barrier layer 80, the grain boundary of the ITO barrier layer 80 can be changed by changing the mass ratio of indium oxide to tin oxide in the ITO barrier layer 80, and the blocking capability of the ITO barrier layer 80 on the free metal simple substance in the tin paste is adjusted.
Referring to fig. 1 and 2, in some embodiments, the ITO barrier layer 80 partially or completely covers the surface of the N-type semiconductor layer, and in embodiments where the ITO barrier layer 80 completely covers the N-type semiconductor layer, the ITO barrier layer 80 may be fitted to the end face of the N-electrode; in embodiments where the ITO barrier layer 80 completely covers the N-type semiconductor layer, the ITO barrier layer 80 can also function as a current spreading layer.
In some embodiments, the at least one ITO barrier layer 80 has a thickness of 60 to 100 nm. Such as 60nm, 70nm, 80nm, 90nm and 100 nm. Since the thickness of the ITO barrier layer 80 affects both the blocking effect of the ITO barrier layer 80 and the circuit conduction between the N electrode 90 and the N-type semiconductor layer 50, the thickness of at least one ITO barrier layer 80 can be selected to be 80nm by comprehensively considering the blocking effect of the ITO barrier layer 80 and the circuit conduction between the N electrode 90 and the N-type semiconductor layer 50.
In some embodiments, the present invention is illustrated by the preparation of two ITO barrier layers 80, wherein the preparation of the two ITO barrier layers 80 comprises: before the N electrode 90 is arranged, sputtering (sputter) equipment is used for sputtering a first ITO barrier layer 80 on the surface of the N-type semiconductor layer 50, wherein the thickness of the first ITO barrier layer 80 is 30-50nm, and the mass ratio of indium oxide to tin oxide in the first ITO barrier layer 80 is 90: 10; then sputtering a second ITO barrier layer 80 on the first ITO barrier layer 80, wherein the thickness of the second ITO barrier layer 80 is 30-50nm, the mass ratio of indium oxide to tin oxide in the second ITO barrier layer 80 is 97:3, and then annealing by using Rapid Thermal Anneal (RTA) equipment to enable the first ITO barrier layer 80 and the second ITO barrier layer 80 to form an ITO crystal structure with a certain included angle; the two ITO barrier layers 80 can block the diffusion of free metal simple substances such as tin (Sn), gold (Au) and copper (Cu) in tin paste, can effectively protect the N-type semiconductor layer from being damaged, and can improve the performance of devices and the yield.
In some embodiments, the thickness of each ITO barrier layer 80 may be the same or different, the thickness of each ITO barrier layer 80 may be 30-50nm, such as 30nm, 40nm and 50nm, and the ITO barrier layer 80 may include 1-5 layers, such as 2 layers, 3 layers and 5 layers, which are not limited herein.
In some embodiments, the area of the end face of the N-electrode 90 is greater than the area of the end face of the P-electrode 70. Since the conductivity of ITO is weaker than that of the N-electrode 90, in the case where the ITO barrier layer 80 is provided between the N-electrode 90 and the N-type semiconductor layer 50, it is also necessary to compensate for the conductivity between the N-electrode 90 and the N-type semiconductor layer 50, and setting the area of the end surface of the N-electrode 90 to be larger than the area of the end surface of the P-electrode 70 makes it possible to more equalize the voltage and current between the N-type semiconductor layer 50 and the P-type semiconductor layer 30 of the light emitting chip.
Referring to fig. 1, in some embodiments, the light emitting chip further includes:
and an insulating layer 100 covering the surfaces of the N-type semiconductor layer 50 and the current diffusion layer 20 and exposing the N-electrode 90 and the P-electrode 70. The insulating layer 100 covers the surfaces of the N-type semiconductor layer 50 and the current diffusion layer 20, so that each layer of the light-emitting chip can be well isolated from the external environment, and each layer is prevented from being oxidized and failed, thereby prolonging the service life of the device.
Referring to fig. 1, in some embodiments, the light emitting chip further includes:
and an adhesive layer 110 disposed between the substrate 10 and the current diffusion layer 20. Since the surface of the substrate 10 is smooth, the adhesive layer 110 may improve the connection strength between the substrate 10 and the current diffusion layer 20, thereby making the light emitting chip more robust.
Referring to fig. 2, in another aspect, the present invention further provides a method for manufacturing a light emitting chip, including:
s100, providing a substrate 10;
s200, sequentially depositing a current diffusion layer 20, a P-type semiconductor layer 30, a light emitting layer and an N-type semiconductor layer 50 on the substrate 10;
s300, partially etching the P-type semiconductor layer 30, the light emitting layer and the N-type semiconductor layer 50 to form a step surface 60 on the current diffusion layer 20;
s400, providing a P-electrode 70 on the step surface 60 of the current diffusion layer 20;
s500, arranging at least one ITO barrier layer 80 on the N-type semiconductor layer 50;
s600, arranging an N electrode 90 on the at least one ITO barrier layer 80.
The light-emitting chip prepared by the method has the advantages of simple manufacturing process and convenience in operation, and the manufactured light-emitting chip has more stable voltage, good performance and long service life because the ITO barrier layer 80 can prevent free metal simple substances in the solder paste from permeating into the N-type semiconductor layer 50.
In some embodiments, the methods of sequentially depositing the current diffusion layer 20, the P-type semiconductor layer 30, the light emitting layer and the N-type semiconductor layer 50 on the substrate 10 and disposing at least one ITO barrier layer 80 on the N-type semiconductor layer 50 include sputtering and spin coating, and the invention is not limited thereto.
In some embodiments, when the ITO barrier layer 80 is provided with at least two layers, the mass ratio of indium oxide to tin oxide in two adjacent layers of the ITO barrier layer 80 is different.
The multilayer ITO barrier layers 80 can more effectively prevent free metal simple substances in the tin paste from permeating into the N-type semiconductor layer 50 due to the fact that the mass proportion of indium oxide and tin oxide in the two adjacent ITO barrier layers 80 is different, crystal orientation between the two adjacent ITO barrier layers 80 is different, difficulty in diffusing the free metal simple substances in the tin paste from one ITO barrier layer 80 to the other ITO barrier layer 80 is higher, and the effect of blocking the free metal simple substances in the tin paste by the ITO barrier layers 80 can be further achieved.
In summary, the present invention provides a light emitting chip and a method for manufacturing the same, wherein the light emitting chip includes a substrate; the current diffusion layer, the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer are sequentially arranged on the substrate; the N-type semiconductor layer, the light emitting layer and the P-type semiconductor layer are partially arranged on the current diffusion layer in a manner of covering the current diffusion layer, and a step surface is formed on the current diffusion layer; a P electrode is arranged on the step surface; at least one ITO barrier layer is arranged on the N-type semiconductor layer; and an N electrode is arranged on the at least one ITO barrier layer. The light-emitting chip utilizes the characteristic that free metal simple substances in the tin paste have weak permeability in the ITO barrier layer, and at least one ITO barrier layer is arranged between the N electrode and the N type semiconductor layer to prevent the metal simple substances from permeating into the N type semiconductor layer, so that the voltage of the light-emitting chip is more stable, the performance of the light-emitting chip is improved, and the service life of the light-emitting chip is prolonged.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A light emitting chip, comprising:
a substrate;
a current spreading layer disposed over the substrate;
a P-type semiconductor layer disposed over the current diffusion layer;
a light emitting layer disposed on the P-type semiconductor layer;
an N-type semiconductor layer disposed over the light emitting layer; the N-type semiconductor layer, the light emitting layer and the P-type semiconductor layer are arranged to partially cover the current diffusion layer so as to form a step surface on the current diffusion layer;
a P electrode disposed on the step surface of the current diffusion layer;
at least one ITO barrier layer arranged on the N-type semiconductor layer;
and the N electrode is arranged on the at least one ITO barrier layer.
2. The light-emitting chip according to claim 1, wherein when at least two ITO barrier layers are provided, the mass ratio of indium oxide to tin oxide in two adjacent ITO barrier layers is different.
3. The light emitting chip of claim 1, wherein the light emitting layer comprises a quantum well layer.
4. The light-emitting chip of claim 1, wherein the ITO barrier layer comprises indium oxide and tin oxide, and the mass percentage of the indium oxide in the ITO barrier layer is 90-99%.
5. The light-emitting chip of claim 1, wherein the at least one ITO barrier layer has a thickness of 60-100 nm.
6. The light-emitting chip according to claim 1, wherein an area of an end surface of the N-electrode is larger than an area of an end surface of the P-electrode.
7. The light-emitting chip according to claim 1, further comprising:
and an insulating layer covering the surfaces of the N-type semiconductor layer and the current diffusion layer and exposing the N electrode and the P electrode.
8. The light-emitting chip according to claim 1, further comprising:
an adhesive layer disposed between the substrate and the current spreading layer.
9. A method for preparing a light-emitting chip is characterized by comprising the following steps:
providing a substrate;
depositing a current diffusion layer, a P-type semiconductor layer, a light emitting layer and an N-type semiconductor layer on the substrate in sequence;
partially etching the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer to form a step surface on the current diffusion layer;
arranging a P electrode on the step surface of the current diffusion layer;
at least one ITO barrier layer is arranged on the N-type semiconductor layer;
and arranging an N electrode on the at least one ITO barrier layer.
10. The method for manufacturing a light-emitting chip according to claim 9, wherein when at least two ITO barrier layers are provided, the mass ratio of indium oxide to tin oxide in the two adjacent ITO barrier layers is different.
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