CN113451417B - Power device and preparation method thereof - Google Patents
Power device and preparation method thereof Download PDFInfo
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- CN113451417B CN113451417B CN202110725060.XA CN202110725060A CN113451417B CN 113451417 B CN113451417 B CN 113451417B CN 202110725060 A CN202110725060 A CN 202110725060A CN 113451417 B CN113451417 B CN 113451417B
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- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 275
- 229910052751 metal Inorganic materials 0.000 claims abstract description 225
- 239000002184 metal Substances 0.000 claims abstract description 225
- 238000002161 passivation Methods 0.000 claims abstract description 199
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims description 16
- 239000004642 Polyimide Substances 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 604
- 238000010586 diagram Methods 0.000 description 23
- 239000011241 protective layer Substances 0.000 description 15
- 238000012360 testing method Methods 0.000 description 13
- 238000005336 cracking Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000001125 extrusion Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 238000005382 thermal cycling Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
Abstract
A power device and a preparation method thereof relate to the technical field of semiconductor devices. The power device includes: a wide band gap substrate; a wide bandgap drift layer disposed on the wide bandgap substrate; a termination region and an active region disposed in the wide bandgap drift layer, the active region being located between the termination regions; the metal electrode layer is arranged on the active region, and schottky contact is formed between the metal electrode layer and the active region; a first material layer disposed on the metal electrode layer; and a passivation layer entirely or partially covering the first material layer and extending toward the termination region, the first material layer entirely or partially separating the passivation layer from the metal electrode layer; the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the passivation layer is c, wherein a > b > c. The power device can improve the reliability of the device.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a power device and a preparation method thereof.
Background
The semiconductor power device is used as a core device in a power electronic circuit to realize efficient transmission and conversion of electric energy and effective and accurate control in the process of the electric energy, and high-quality and efficient utilization of the electric energy is realized. Due to research and development of power semiconductor devices, power electronics technology is developed toward miniaturization, large capacity, high frequency, high efficiency, energy saving, high reliability and low cost.
Conventional semiconductor power devices are typically covered with a passivation layer extending all the way to the front electrode surface in the termination area of the power device in order to prevent external moisture and mobile ions (such as sodium) from affecting the internal structure of the device. However, when the TCT (Temperature Cycle Test ) is performed on the power device, since the thermal expansion coefficients of the plastic package body, the front electrode and the passivation layer in the packaged device are different, stress is generated between the plastic package body and the front electrode due to mutual extrusion, so that the front electrode surface and the passivation layer are cracked, and water vapor and mobile ions in the air can enter the device along the cracks, thereby degrading the device performance and even causing the device to fail.
Disclosure of Invention
In order to improve the reliability of the device, the invention provides a power device and a power preparation method.
In one aspect of the present disclosure, there is provided a power device including: a wide band gap substrate; a wide bandgap drift layer disposed on the wide bandgap substrate; a termination region and an active region disposed in the wide bandgap drift layer, the active region being located between the termination regions; the metal electrode layer is arranged on the active region, and schottky contact is formed between the metal electrode layer and the active region; a first material layer disposed on the metal electrode layer; and a passivation layer entirely or partially covering the first material layer and extending toward the termination region, the first material layer entirely or partially separating the passivation layer from the metal electrode layer; the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the passivation layer is c, wherein a > b > c.
In another aspect of the present disclosure, there is provided a power device including: a wide band gap substrate; a wide bandgap drift layer disposed on the wide bandgap substrate; an active region provided in the wide band gap drift layer, and a termination region provided in the wide band gap drift layer and located on one side of the active region; a first passivation layer disposed on the wide bandgap drift layer, the first passivation layer configured to cover the termination region surface from the active region edge; the metal electrode layer is arranged on the active region, schottky contact is arranged between the metal electrode layer and the active region, the metal electrode layer is provided with a step higher than the first passivation layer, the step is provided with a first side wall facing the first passivation layer, and the first side wall is connected with the first passivation layer; a first material layer disposed on the metal electrode layer, a second passivation layer entirely or partially covering the first material layer and extending toward the terminal region, the first material layer entirely or partially separating the second passivation layer from the metal electrode layer; the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the second passivation layer is c, wherein a > b > c.
In still another aspect of the present disclosure, a method for manufacturing a power device is provided, the method comprising: providing a first power device structure, wherein the first power device structure comprises a wide band gap substrate, a wide band gap drift layer arranged on the wide band gap substrate, an active region arranged in the wide band gap drift layer, a terminal region arranged in the wide band gap drift layer and positioned at one side of the active region, a first passivation layer arranged on the wide band gap drift layer and configured to cover the surface of the terminal region from the edge of the active region, a metal electrode layer arranged on the active region, schottky contact is arranged between the metal electrode layer and the active region, the metal electrode layer is provided with a step higher than the first passivation layer, the step is provided with a first side wall facing the first passivation layer and a top surface deviating from the wide band gap drift layer, and the first side wall is connected with the first passivation layer; forming a first material layer on the metal electrode layer; and forming a second passivation layer which completely or partially covers the first material layer and extends towards the terminal area, wherein the first material layer completely or partially separates the second passivation layer from the metal electrode layer, the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the second passivation layer is c, and a > b > c.
By adopting the power device disclosed by the invention, the reliability of the device is improved after TCT test.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present disclosure and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a power device according to some embodiments of the present disclosure;
FIG. 2 is a second schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 3 is a third schematic structural diagram of a power device according to some embodiments of the present disclosure;
fig. 4 is a schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 5 is a schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 6 is a schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 7 is a schematic diagram of a power device according to some embodiments of the present disclosure;
Fig. 8 is a schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 9 is a diagram illustrating a power device according to some embodiments of the present disclosure;
fig. 10 is a schematic structural diagram of a power device according to other embodiments of the present disclosure;
FIG. 11 is a schematic diagram of a second embodiment of a power device according to the present disclosure;
FIG. 12 is a third schematic diagram of a power device according to other embodiments of the present disclosure;
fig. 13 is a schematic diagram of a power device according to other embodiments of the present disclosure;
fig. 14 is a schematic diagram of a power device according to other embodiments of the present disclosure;
fig. 15 is a schematic diagram of a power device according to another embodiment of the disclosure;
fig. 16 is a schematic diagram of a power device according to other embodiments of the present disclosure;
fig. 17 is a schematic diagram of a power device according to another embodiment of the disclosure;
fig. 18 is a diagram illustrating a power device according to another embodiment of the present disclosure;
fig. 19 is a schematic flow chart of a method for manufacturing a power device according to some embodiments of the present disclosure;
fig. 20 is one of schematic diagrams of states of a power device provided in some embodiments of the present disclosure;
FIG. 21 is a second schematic diagram of a power device according to some embodiments of the present disclosure;
FIG. 22 is a third schematic diagram illustrating a state of a power device according to some embodiments of the present disclosure;
fig. 23 is a second flow chart of a method for manufacturing a power device according to some embodiments of the present disclosure;
FIG. 24 is a fourth schematic diagram of a state of a power device provided by some embodiments of the present disclosure;
fig. 25 is a third flow chart of a method for manufacturing a power device according to some embodiments of the present disclosure;
fig. 26 is a schematic diagram showing a state of a power device according to some embodiments of the present disclosure.
Icon: 10-a wide bandgap substrate; a 20-wide bandgap drift layer; 21-an active region; a 22-terminal region; 31-schottky contact metal; 311-sub-metal layer; 32-a metal electrode layer; 321-top surface; 322-a first sidewall; 323 steps; 33-metal electrode contact areas; 41-a first material layer; a 50A-passivation layer; 50B-a second passivation layer; 60-a first passivation layer; 70-a protective layer; an 80-ohm metal layer; 90-a back electrode layer; 100-first power device structure.
Detailed Description
The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Related terms such as "below" or "above" … "or" upper "or" lower "or" horizontal "or" vertical "may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It should be understood that these terms, and those terms discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present disclosure provides a power device including: a wide bandgap substrate 10; a wide bandgap drift layer 20 disposed on the wide bandgap substrate 10; a termination region 22 and an active region 21 disposed in the wide bandgap drift layer 20, the active region 21 being located within the termination region 22; the metal electrode layer 32 is arranged on the active region 21, and schottky contact is formed between the metal electrode layer 32 and the active region 21; a first material layer 41 disposed on the metal electrode layer 32; and a passivation layer 50A covering the first material layer 41 entirely or partially and extending toward the termination region 22, the first material layer 41 separating the passivation layer 50A from the metal electrode layer 32 entirely or partially, the material of the first material layer 41 having a coefficient of expansion of a, the material of the metal electrode layer 32 having a coefficient of expansion of b, and the material of the passivation layer 50A having a coefficient of expansion of c, wherein a > b > c.
According to the method, the passivation layer 50A is separated from the metal electrode layer 32 through the first material layer 41, the expansion coefficient of the material of the first material layer 41 is a, the expansion coefficient of the material of the metal electrode layer 32 is b, and the expansion coefficient of the material of the passivation layer 50A is c, wherein a > b > c can enable the passivation layer 50A to not crack due to the existence of the first material layer 41 when the passivation layer 50A is subjected to stress generated by thermal cycling during TCT reliability test, so that the problem that the reliability of a device is reduced due to the fact that the passivation layer 50A cracks after the TCT test of the device can be effectively solved.
In some embodimentsIn this embodiment, as shown in fig. 1, the wide bandgap substrate 10 is an N-type silicon carbide wide bandgap substrate 10. In some embodiments, the wide bandgap substrate 10 is in the form of 4H-SiC. In some embodiments, the wide bandgap substrate 10 has a thickness of 350 μm. In some embodiments, the wide bandgap substrate 10 has a doping concentration of 1×10 19 cm 3 Up to 1X 10 20 /cm 3 Between them. It should be understood that the above-described crystal form, thickness, and doping concentration of the wide bandgap substrate 10 are merely examples provided by some embodiments of the present disclosure and are not the only limitations of the present disclosure.
In some embodiments, as shown in fig. 1, the thickness of the wide bandgap drift layer 20 may be between 5 μm and 80 μm, for example, may be 5 μm, 10 μm, 30 μm, 50 μm, 70 μm, 80 μm, etc., which are not further listed in this disclosure. In some embodiments, the doping concentration of the wide bandgap drift layer 20 may be 1×10 14 /cm 3 Up to 5X 10 16 /cm 3 Between them.
In some embodiments, as shown in fig. 1, the active region 21 disposed in the wide band gap drift layer 20 may be stripe-shaped, hexagonal, or a combination of stripe-shaped and hexagonal.
In some embodiments, as shown in fig. 1, the metal electrode layer 32 is in schottky contact with the active region 21. In some embodiments, the metal electrode layer 32 includes a schottky contact metal 31 disposed on a side of the active region 21 facing away from the wide bandgap substrate 10 and a sub-metal layer 311 disposed on a side of the schottky contact metal 31 facing away from the wide bandgap substrate 10. In some embodiments, the schottky contact metal 31 may have a thickness between 100nm and 500 nm. In some embodiments, the material of the schottky metal layer 31 may be any one of Ti, W, ta, ni, mo, and Pt or a combination of at least two of the foregoing metals. The thickness of the schottky metal layer 31 may be between 100nm and 500 nm. For example, the thickness of the schottky metal layer 31 may be 100nm, 200nm, 300nm, 400nm, 500nm, or the like.
In some embodiments, as shown in fig. 1, the thickness of the metal electrode layer 32 may be between 2 μm and 5 μm. Illustratively, the thickness of the metal electrode layer 32 may be 2 μm, 3 μm, 4 μm, 5 μm, or the like. The material of the metal electrode layer 32 may be any one of Al, ag, cu, and Au or a combination of at least two metals.
In some embodiments, as shown in fig. 1, a first material layer 41 is provided on the metal electrode layer 32. The first material layer 41 is provided to completely or partially separate the passivation layer 50A and the metal electrode layer 32. In some embodiments, first material layer 41 may be polyimide. The polyimide material has a certain elasticity, so that when the passivation layer 50A is subjected to stress generated by thermal cycle during TCT test, the problem of reduced device reliability caused by cracking of the passivation layer 50A can be effectively avoided.
In some embodiments, as shown in fig. 1, the passivation layer 50A has a thickness between 1 μm and 3 μm. For example, the passivation layer 50A may have a thickness of 1 μm, 2 μm, 3 μm, or the like. In some embodiments, the material of passivation layer 50A is silicon oxide (e.g., siO 2 ) Or silicon nitride (for example, si 3 N 4 ). In some embodiments, the material of the first material layer 41 has a coefficient of expansion a, the material of the metal electrode layer 32 has a coefficient of expansion b, and the material of the passivation layer 50A has a coefficient of expansion c, where a>b>c. In this way, the present disclosure can effectively improve the problem of stress generated by mutual extrusion between the passivation layer 50A and the metal electrode layer 32 when TCT test is performed, so as to reduce the risk of cracking the passivation layer 50A and improve the reliability of the device.
In some embodiments, as shown in fig. 7, the power device provided by the present disclosure further includes a protective layer 70 overlying passivation layer 50A and metal electrode layer 32. In some embodiments, in actual use, protective layer 70 may be etched to expose portions of metal electrode layer 32, thereby forming metal electrode contact regions 33 (see fig. 7). The material of the protective layer 70 is polyimide. In some embodiments, the protective layer 70 may have a thickness between 3 μm and 5 μm, for example, 3 μm, 4 μm, or 5 μm.
In some embodiments, as shown in fig. 7, the power device provided by the present disclosure may further include an ohmic metal layer 80 on a side of the wide bandgap substrate 10 facing away from the wide bandgap drift layer 20, and a back electrode layer 90 on a side of the ohmic metal layer 80 facing away from the wide bandgap substrate 10. Wherein the thickness of the back electrode layer 90 may be between 2 μm and 5 μm. The material of the ohmic metal layer 80 may be any one metal of Ni, ti, nb, and Mo, and the thickness of the ohmic metal layer 80 may be between 100nm and 500 nm.
In some embodiments, the power devices provided by the present disclosure may be ordinary schottky diodes, junction barrier schottky diodes, or hybrid PIN schottky diodes.
In some embodiments, first material layer 41 is used to completely separate passivation layer 50A from metal electrode layer 32. In some embodiments, first material layer 41 is used to partially separate passivation layer 50A from metal electrode layer 32. Hereinafter, the case of full separation and partial separation will be respectively exemplified.
In some embodiments, as shown in fig. 1, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the passivation layer 50A is configured to extend along the first material layer 41 from the position of the first material layer 41 at the top surface 321 toward the termination region 22. At this time, the passivation layer 50A is completely separated from the metal electrode layer 32 by the first material layer 41.
In some embodiments, as shown in fig. 2, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; passivation layer 50A is configured to be flush with the top surface of first material layer 41 and extends toward termination region 22. At this time, the passivation layer 50A is also completely separated from the metal electrode layer 32 by the first material layer 41.
In some embodiments, as shown in fig. 3, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the passivation layer 50A is configured to extend toward the termination region 22 from a position where the sidewall of the first material layer 41 facing the termination region 22 is higher than 1/2h (the height of the sidewall of the first material layer 41 facing the termination region 22 is h). At this time, the first material layer 41 may also completely separate the passivation layer 50A and the metal electrode layer 32.
In some embodiments, as shown in fig. 4, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the passivation layer 50A is configured to cover a portion of the top surface 321 of the metal electrode layer 32 and extend toward the termination region 22 along the first material layer 41 at the location of the top surface 321 and the side wall of the first material layer 41 facing the termination region 22. At this time, the first material layer 41 may partially separate the passivation layer 50A and the metal electrode layer 32, and the passivation layer 50A may be in contact with the metal electrode layer 32 at a partial region of the top surface 321 of the metal electrode layer 32.
In some embodiments, as shown in fig. 5, the metal electrode layer 32 includes a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to be flush with a top surface 321 of the metal electrode layer 32 and extending in a direction toward the wide bandgap drift layer 20; passivation layer 50A is configured to entirely cover first material layer 41 and extend toward termination region 22. At this time, the first material layer 41 may completely separate the passivation layer 50A and the metal electrode layer 32.
In some embodiments, as shown in fig. 6, the metal electrode layer 32 includes a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to be flush with a top surface 321 of the metal electrode layer 32 and extending in a direction toward the wide bandgap drift layer 20; the passivation layer 50A is arranged flush with the top surface of the first material layer 41 and extends toward the termination region 22. At this time, the passivation layer 50A is also completely separated from the metal electrode layer 32 by the first material layer 41.
In some embodiments, as shown in fig. 7, the metal electrode layer 32 includes a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to be flush with a top surface 321 of the metal electrode layer 32 and extending in a direction toward the wide bandgap drift layer 20; the passivation layer 50A is configured to extend toward the termination region 22 from a position where the sidewall of the first material layer 41 facing the termination region 22 is higher than 1/2h (the height of the sidewall of the first material layer 41 facing the termination region 22 is h). At this time, the first material layer 41 may also completely separate the passivation layer 50A and the metal electrode layer 32.
In some embodiments, as shown in fig. 8, the metal electrode layer 32 includes a first sidewall 322 facing the termination region 22, the first material layer 41 is disposed on the first sidewall 322, the first sidewall 322 has a height h, and the first material layer 41 is configured to extend from the first sidewall 322 higher than 1/2h toward the wide bandgap drift layer 20; the passivation layer 50A is configured to be flush with the top surface of the first material layer 41 and extend toward the termination region 22. At this time, the first material layer 41 may also completely separate the passivation layer 50A from the metal electrode layer 32.
In some embodiments, as shown in fig. 9, the metal electrode layer 32 includes a first sidewall 322 facing the termination region 22, the first material layer 41 is disposed on the first sidewall 322, the first sidewall 322 has a height h, and the first material layer 41 is configured to extend from the first sidewall 322 higher than 1/2h toward the wide bandgap drift layer 20; the passivation layer 50A is configured to extend from the first sidewall 322 higher than the first material layer 41 along the first material layer 41 toward the termination region 22. At this time, the first material layer 41 may partially separate the passivation layer 50A and the metal electrode layer 32, and the passivation layer 50A may be in contact with the metal electrode layer 32 at a partial region at the first sidewall 322 of the metal electrode layer 32.
It should be noted that, in some embodiments, when the terminal regions 22 are distributed on opposite sides of the active region 21, the related designs related to the first material layer 41 and the passivation layer 50A mentioned in the disclosure may be disposed on one side of the active region 21, or may be disposed on opposite sides of the active region, respectively, which is not particularly limited in the disclosure.
The present disclosure also provides another power device including: a wide bandgap substrate 10; a wide bandgap drift layer 20 disposed on the wide bandgap substrate 10; an active region 21 provided in the wide bandgap drift layer 20, and a termination region 22 provided in the wide bandgap drift layer 20 and located on the active region 21 side; a first passivation layer 60 disposed on the wide band gap drift layer 20, the first passivation layer 60 being configured to cover a surface of the termination region 22 from an edge of the active region 21; the metal electrode layer 32 is arranged on the active region 21, schottky contact is formed between the metal electrode layer 32 and the active region 21, the metal electrode layer 32 is provided with a step 323 higher than the first passivation layer 60, the step 323 is provided with a first side wall 322 facing the first passivation layer 60, and the first side wall 322 is connected with the first passivation layer 60; a first material layer 41 disposed on the metal electrode layer 32, a second passivation layer 50B entirely or partially covering the first material layer 41 and extending toward the termination region 22, the first material layer 41 completely or partially separating the second passivation layer 50B from the metal electrode layer 32; the expansion coefficient of the material of the first material layer 41 is a, the expansion coefficient of the material of the metal electrode layer 32 is B, and the expansion coefficient of the material of the second passivation layer 50B is c, where a > B > c.
The second passivation layer 50B is separated from the metal electrode layer 32 by the first material layer 41, the expansion coefficient of the material of the first material layer 41 is a, the expansion coefficient of the material of the metal electrode layer 32 is B, and the expansion coefficient of the material of the second passivation layer 50B is c, wherein a > B > c can enable the second passivation layer 50B to not crack due to the first material layer 41 when the second passivation layer 50B is subjected to stress generated by thermal cycling during a TCT reliability test, so that the problem that the reliability of a device is reduced due to the cracking of the second passivation layer 50B after the TCT test of the device can be effectively solved.
In some embodiments, the wide bandgap substrate 10 is an N-type silicon carbide wide bandgap substrate 10, as shown in fig. 10. In some embodiments, the wide bandgap substrate 10 is in the form of 4H-SiC. In some embodiments, the wide bandgap substrate 10 has a thickness of 350 μm. In some embodiments, the wide bandgap substrate 10 has a doping concentration of 1×10 19 cm 3 Up to 1X 10 20 /cm 3 Between them. It should be understood that the above-described crystal form, thickness, and doping concentration of the wide bandgap substrate 10 are merely examples provided by some embodiments of the present disclosure and are not the only limitations of the present disclosure.
In some embodiments, as shown in FIG. 10, the wide bandgap drift layer 20 may have a thickness of between 5 μm and 80 μmFor example, it may be 5 μm, 10 μm, 30 μm, 50 μm, 70 μm, 80 μm, or the like, and the disclosure is not limited thereto. In some embodiments, the doping concentration of the wide bandgap drift layer 20 may be 1×10 14 /cm 3 Up to 5X 10 16 /cm 3 Between them.
In some embodiments, as shown in fig. 10, the active region 21 disposed in the wide band gap drift layer 20 may be stripe-shaped, hexagonal, or a combination of stripe-shaped and hexagonal.
In some embodiments, as shown in fig. 10, the thickness of the first passivation layer 60 may be set as desired by those skilled in the art, and the present application is not limited. In some embodiments, the material of the first passivation layer 60 may be silicon oxide. The first passivation layer 60 is configured to cover the surface of the terminal region 22 from the edge of the active region 21, i.e., the first passivation layer 60 covers the edge of the active region 21 and covers the surface of the terminal region 22.
In some embodiments, as shown in fig. 10, the metal electrode layer 32 and the active region 21 are in schottky contact, and a schottky contact metal 31 may be disposed between the metal electrode layer 32 and the active region 21. In some embodiments, the schottky contact metal 31 may have a thickness between 100nm and 500 nm. In some embodiments, the material of the schottky metal layer 31 may be any one of Ti, W, ta, ni, mo, and Pt or a combination of at least two of the foregoing metals. The thickness of the schottky metal layer 31 may be between 100nm and 500 nm. For example, the thickness of the schottky metal layer 31 may be 100nm, 200nm, 300nm, 400nm, 500nm, or the like. The metal electrode layer 32 is higher than the step 323 of the first passivation layer 60, as shown in fig. 10, that is, the metal electrode layer 32 is covered on the first passivation layer 60. The step 323 has a first sidewall 322 facing the first passivation layer 60, and the first sidewall 322 is the same as the first sidewall 322 described above, and is the outer peripheral wall of the metal electrode layer.
In some embodiments, as shown in fig. 10, the thickness of the metal electrode layer 32 may be between 2 μm and 5 μm. Illustratively, the thickness of the metal electrode layer 32 may be 2 μm, 3 μm, 4 μm, 5 μm, or the like. In some embodiments, the material of the metal electrode layer 32 may be any one of Al, ag, cu, and Au or a combination of at least two metals.
In some embodiments, as shown in fig. 10, first material layer 41 is disposed on first sidewall 322, as shown in fig. 10. I.e. the first material layer 41 is provided on the outer peripheral wall of the metal electrode layer 32. It should be noted that the area of the first material layer 41 covering the first sidewall 322 is not limited in the present disclosure, as long as the second passivation layer 50B and the metal electrode layer 32 can be completely or partially separated by the first material layer 41. Wherein in some embodiments, the first material layer 41 may be polyimide. The polyimide material has a certain elasticity, so that when the second passivation layer 50B is subjected to stress generated by thermal cycle during TCT test, the problem of reduced device reliability caused by cracking of the second passivation layer 50B can be effectively avoided.
In some embodiments, the present disclosure does not limit the area and region of the second passivation layer 50B covering the first material layer 41, as long as the first material layer 41 can completely or partially separate the second passivation layer 50B from the metal electrode layer 32. In some embodiments, as shown in fig. 10, the thickness of the second passivation layer 50B is between 1 μm and 3 μm. For example, the thickness of the second passivation layer 50B may be 1 μm, 2 μm, 3 μm, or the like. Also, the material of the second passivation layer 50B is silicon oxide (e.g., siO 2 ) Or silicon nitride (for example, si 3 N 4 ). In some embodiments, the material of the first material layer 41 has a coefficient of expansion a, the material of the metal electrode layer 32 has a coefficient of expansion B, and the material of the second passivation layer 50B has a coefficient of expansion c, where a>b>c. In this way, the present disclosure can effectively improve the problem of stress generated by mutual extrusion between the second passivation layer 50B and the metal electrode layer 32 when TCT test is performed, so as to reduce the risk of cracking of the second passivation layer 50B and improve the reliability of the device.
In some embodiments, as shown in fig. 10, the power device further includes a protective layer 70 overlying the second passivation layer 50B and the metal electrode layer 32. In some embodiments, in actual use, protective layer 70 may be etched to expose portions of metal electrode layer 32, thereby forming metal electrode contact regions 33 (see fig. 10). The material of the protective layer 70 is polyimide. In some embodiments, the protective layer 70 may have a thickness between 3 μm and 5 μm, for example, 3 μm, 4 μm, or 5 μm.
In some embodiments, as shown in fig. 10, the power device provided by the present disclosure may further include an ohmic metal layer 80 on a side of the wide bandgap substrate 10 facing away from the wide bandgap drift layer 20, and a back electrode layer 90 on a side of the ohmic metal layer 80 facing away from the wide bandgap substrate 10. Wherein the thickness of the back electrode layer 90 may be between 2 μm and 5 μm. The material of the ohmic metal layer 80 may be any one metal of Ni, ti, nb, and Mo, and the thickness of the ohmic metal layer 80 may be between 100nm and 500 nm.
In some embodiments, the power devices provided by the present disclosure may be ordinary schottky diodes, junction barrier schottky diodes, or hybrid PIN schottky diodes.
In some embodiments, first material layer 41 is used to completely separate second passivation layer 50B from metal electrode layer 32. In some embodiments, first material layer 41 is used to partially separate second passivation layer 50B from metal electrode layer 32. Hereinafter, the case of full separation and partial separation will be respectively exemplified.
In some embodiments, as shown in fig. 10, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the second passivation layer 50B is configured to extend from the first material layer 41 at the position of the top surface 321 along the first material layer 41 toward the termination region 22. At this time, the first material layer 41 completely separates the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 11, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the second passivation layer 50B is configured to be flush with the top surface of the first material layer 41 and extends toward the termination region 22. At this time, the first material layer 41 also completely separates the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 12, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the second passivation layer 50B is configured to extend toward the termination region 22 from a position where the sidewall of the first material layer 41 facing the termination region 22 is higher than 1/2h (the height of the sidewall of the first material layer 41 facing the termination region 22 is h). At this time, the first material layer 41 may also completely separate the second passivation layer 50B and the metal electrode layer 32.
In some embodiments, as shown in fig. 13, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and to cover the first sidewall 322; the second passivation layer 50B is configured to cover a portion of the top surface 321 of the metal electrode layer 32 and extends toward the terminal region 22 along the first material layer 41 at the location of the top surface 321 and the side wall of the first material layer 41 facing the terminal region 22. At this time, the first material layer 41 may partially separate the second passivation layer 50B and the metal electrode layer 32, and the second passivation layer 50B may be in contact with the metal electrode layer 32 at a partial region of the top surface 321 of the metal electrode layer 32.
In some embodiments, as shown in fig. 14, the first material layer 41 is configured to be flush with the top surface 321 of the metal electrode layer 32 and extends in a direction toward the wide bandgap drift layer 20; the second passivation layer 50B is configured to entirely cover the first material layer 41 and extend toward the termination region 22. At this time, the first material layer 41 may completely separate the second passivation layer 50B and the metal electrode layer 32.
In some embodiments, as shown in fig. 15, the first material layer 41 is configured to be flush with the top surface 321 of the metal electrode layer 32 and extend in a direction toward the wide bandgap drift layer 20; the second passivation layer 50B is arranged flush with the top surface of the first material layer 41 and extends toward the termination region 22. At this time, the first material layer 41 also completely separates the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 16, the first material layer 41 is configured to be flush with the top surface 321 of the metal electrode layer 32 and extends in a direction toward the wide bandgap drift layer 20; the second passivation layer 50B is configured to extend toward the termination region 22 from a position where the sidewall of the first material layer 41 facing the termination region 22 is higher than 1/2h (the height of the sidewall of the first material layer 41 facing the termination region 22 is h). At this time, the first material layer 41 may also completely separate the second passivation layer 50B and the metal electrode layer 32.
In some embodiments, as shown in fig. 17, the first material layer 41 is disposed on the first sidewall 322, the first sidewall 322 has a height h, and the first material layer 41 is configured to extend from the first sidewall 322 higher than 1/2h toward the wide bandgap drift layer 20; the second passivation layer 50B is configured to be flush with the top surface of the first material layer 41 and extend toward the termination region 22. At this time, the first material layer 41 may also completely separate the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 18, the first material layer 41 is disposed on the first sidewall 322, the first sidewall 322 has a height h, and the first material layer 41 is configured to extend from the first sidewall 322 higher than 1/2h toward the wide bandgap drift layer 20; the second passivation layer 50B is configured to extend from the first sidewall 322 higher than the first material layer 41 along the first material layer 41 toward the termination region 22. At this time, the first material layer 41 may partially separate the second passivation layer 50B and the metal electrode layer 32, and the second passivation layer 50B may be in contact with the metal electrode layer 32 at a partial region of the first sidewall 322 of the metal electrode layer 32.
It should be noted that, in some embodiments, when the termination region 22 is distributed on opposite sides of the active region 21, the related designs related to the first material layer 41 and the second passivation layer 50B mentioned in the disclosure may be disposed on one side of the active region 21, or may be disposed on opposite sides of the active region, respectively, and the disclosure is not limited in particular.
Referring to fig. 19, the present disclosure further provides a method for manufacturing a power device, including the following steps:
s100, providing a first power device structure 100, where the first power device structure 100 includes a wide bandgap substrate 10, a wide bandgap drift layer 20 disposed on the wide bandgap substrate 10, an active region 21 disposed in the wide bandgap drift layer 20, a termination region 22 disposed in the wide bandgap drift layer 20 and located at one side of the active region 21, a first passivation layer 60 disposed on the wide bandgap drift layer 20, the first passivation layer 60 being configured to cover a surface of the termination region 22 from an edge of the active region 21, a metal electrode layer 32 disposed on the active region 21, the metal electrode layer 32 being in schottky contact with the active region 21, the metal electrode layer 32 having a step 323 higher than the first passivation layer, the step 323 having a first sidewall 322 facing the first passivation layer 60 and a top surface 321 facing away from the wide bandgap drift layer 20, the first sidewall 322 being in contact with the first passivation layer 60, as shown in fig. 20.
S200, a first material layer 41 is formed on the metal electrode layer, as shown in fig. 17.
S300, forming a second passivation layer 50B, where the second passivation layer 50B covers the first material layer 41 and extends toward the termination region 22; the expansion coefficient of the material of the first material layer 41 is a, the expansion coefficient of the material of the metal electrode layer 32 is B, and the expansion coefficient of the material of the second passivation layer 50B is c, where a > B > c, as shown in fig. 18.
The preparation method provided by the disclosure separates the second passivation layer 50B from the metal electrode layer 32 completely or partially through the first material layer 41, and the expansion coefficient of the material of the first material layer 41 is a, the expansion coefficient of the material of the metal electrode layer 32 is B, and the expansion coefficient of the material of the second passivation layer 50B is c, wherein a > B > c, so that when the TCT reliability test is performed, the second passivation layer 50B is subjected to stress generated by thermal cycling, the second passivation layer 50B is not cracked due to the existence of the first material layer 41, and the problem that the reliability of the device is reduced due to the cracking of the second passivation layer 50B after the TCT test is performed can be effectively solved.
In some embodiments, as shown in fig. 20, the wide bandgap substrate 10 is an N-type silicon carbide wide bandgap substrate 10. In some embodimentsThe wide bandgap substrate 10 has a crystal form of 4H-SiC. In some embodiments, the wide bandgap substrate 10 has a thickness of 350 μm. In some embodiments, the wide bandgap substrate 10 has a doping concentration of 1×10 19 cm 3 Up to 1X 10 20 /cm 3 Between them. It should be understood that the above-described crystal form, thickness, and doping concentration of the wide bandgap substrate 10 are merely examples provided by some embodiments of the present disclosure and are not the only limitations of the present disclosure.
In some embodiments, as shown in fig. 20, the thickness of the wide bandgap drift layer 20 may be between 5 μm and 80 μm, for example, may be 5 μm, 10 μm, 30 μm, 50 μm, 70 μm, 80 μm, etc., which are not further listed in this disclosure. In some embodiments, the doping concentration of the wide bandgap drift layer 20 may be 1×10 14 /cm 3 Up to 5X 10 16 /cm 3 Between them.
In some embodiments, as shown in fig. 20, the active region 21 disposed in the wide band gap drift layer 20 may be stripe-shaped, hexagonal, or a combination of stripe-shaped and hexagonal.
In some embodiments, as shown in fig. 20, the material of the first passivation layer 60 may be silicon oxide. The first passivation layer 60 is configured to cover the surface of the terminal region 22 from the edge of the active region 21, i.e., the first passivation layer 60 covers the edge of the active region 21 and covers the surface of the terminal region 22.
In some embodiments, as shown in fig. 20, the metal electrode layer 32 and the active region 21 are in schottky contact, and a schottky contact metal 31 may be disposed between the metal electrode layer 32 and the active region 21. In some embodiments, the schottky contact metal 31 may have a thickness between 100nm and 500 nm. In some embodiments, the material of the schottky metal layer 31 may be any one of Ti, W, ta, ni, mo, and Pt or a combination of at least two of the foregoing metals. The thickness of the schottky metal layer 31 may be between 100nm and 500 nm. For example, the thickness of the schottky metal layer 31 may be 100nm, 200nm, 300nm, 400nm, 500nm, or the like. The metal electrode layer 32 is higher than the step 323 of the first passivation layer 60, as shown in fig. 20, that is, the metal electrode layer 32 covering the first passivation layer 60. The step 323 has a first sidewall 322 facing the first passivation layer 60, and the first sidewall 322 is the same as the first sidewall 322 described above, and is the outer peripheral wall of the metal electrode layer.
In some embodiments, as shown in fig. 20, the thickness of the metal electrode layer 32 may be between 2 μm and 5 μm. Illustratively, the thickness of the metal electrode layer 32 may be 2 μm, 3 μm, 4 μm, 5 μm, or the like. The material of the metal electrode layer 32 may be any one of Al, ag, cu, and Au or a combination of at least two metals.
In some embodiments, as shown in fig. 21, in step S200, the first material layer 41 is formed on the metal electrode layer 32. In some embodiments, first material layer 41 may be polyimide. The polyimide material has a certain elasticity, so that when the second passivation layer 50B is subjected to stress generated by thermal cycle during TCT test, the problem of reduced device reliability caused by cracking of the second passivation layer 50B can be effectively avoided. The second sidewall of the first material layer 41 is the outer peripheral wall of the first material layer 41.
In some embodiments, as shown in fig. 22, the thickness of the second passivation layer 50B is between 1 μm and 3 μm. For example, the thickness of the second passivation layer 50B may be 1 μm, 2 μm, 3 μm, or the like. Also, the material of the second passivation layer 50B is silicon oxide (e.g., siO 2 ) Or silicon nitride (for example, si 3 N 4 ). In some embodiments, the material of the first material layer 41 has a coefficient of expansion a, the material of the metal electrode layer 32 has a coefficient of expansion B, and the material of the second passivation layer 50B has a coefficient of expansion c, where a>b>c。
In some embodiments, as shown in fig. 18, the preparation method provided in this example may further continue to prepare the protective layer 70, the ohmic metal layer 80, and the back electrode layer 90 on the basis of step S300. The sequence of preparation of the protective layer 70, the ohmic metal layer 80 and the back electrode layer 90 can be selected by one skilled in the art according to common general knowledge in the art, and the present disclosure is not limited thereto.
In some embodiments, as shown in fig. 18, a protective layer 70 overlies the second passivation layer 50B and the metal electrode layer 32. In some embodiments, in actual use, protective layer 70 may be etched to expose portions of metal electrode layer 32, thereby forming metal electrode contact regions 33 (see fig. 18). The material of the protective layer 70 is polyimide. In some embodiments, the protective layer 70 may have a thickness between 3 μm and 5 μm, for example, 3 μm, 4 μm, or 5 μm.
In some embodiments, as shown in fig. 22, the back electrode layer 90 is located on a side of the ohmic metal layer 80 remote from the wide bandgap substrate 10. Wherein the thickness of the back electrode layer 90 may be between 2 μm and 5 μm. The material of the ohmic metal layer 80 may be any one metal of Ni, ti, nb, and Mo, and the thickness of the ohmic metal layer 80 may be between 100nm and 500 nm.
In some embodiments, as shown in fig. 23, when the first material layer 41 is formed on the first sidewall 322 in step S200, it may be achieved by:
s211, a first material layer 41 is formed on the entire surface of the first power device structure 100 facing away from the wide bandgap substrate 10, as shown in fig. 24.
S212, removing the first material layer 41 on the top surface 321 of the metal electrode layer 32 and the first material layer 41 on the surface of the first passivation layer 60 by using a photolithography process, and retaining the first material layer 41 on the first sidewall 322, as shown in fig. 20.
In some embodiments, in step S211, the manner of forming the entire surface of the first material layer 41 is not limited, and a deposition process or any other achievable process may be used.
In some embodiments, in step S212, as shown in fig. 21, performing a photolithography process on the first material layer 41 may result in a structure as shown in fig. 21, where the first material layer 41 of the structure shown in fig. 21 covers the entire first sidewall 322.
Referring to fig. 25, in step S200, when the first material layer 41 is formed on the first sidewall 322, the following steps may be further performed:
s221, a first material layer 41 is formed on the entire surface of the first power device structure 100 facing away from the wide bandgap substrate 10, as shown in fig. 24.
S222, removing the first material layer 41 in the middle area of the top surface 321 of the metal electrode layer 32 and the first material layer 41 on the surface of the first passivation layer 60 by using a photolithography process, and retaining the first material layer 41 on the first sidewall 322 and at the edge of the top surface 321, as shown in fig. 26.
In some embodiments, in step S221, the manner of forming the entire surface of the first material layer 41 is not limited, and a deposition process or any other achievable process may be used.
In some embodiments, in step S222, the first material layer 41 is subjected to a photolithography process to obtain a structure as shown in fig. 26, where the first material layer 41 of the structure shown in fig. 26 covers the entire first sidewall 322 and the edge of the top surface 321 of the metal electrode layer 32.
In some embodiments, the power device manufactured by the manufacturing method of the power device provided by the disclosure may be a general schottky diode, a junction barrier schottky diode or a hybrid PIN schottky diode.
In some embodiments, in step S300, the first material layer 41 serves to completely separate the second passivation layer 50B from the metal electrode layer 32. In some embodiments, first material layer 41 is used to partially separate second passivation layer 50B from metal electrode layer 32. Can be obtained by performing the following processing on the formation positions of the first material layer 41 in step S200 and the second passivation layer 50B in step S300.
In some embodiments, as shown in fig. 10, where the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 in step S200 may be configured to extend from an edge of the top surface 321 toward the first sidewall 322 and cover the first sidewall 322; the second passivation layer 50B in step S300 is configured to extend from the first material layer 41 at the position of the top surface 321 along the first material layer 41 toward the termination region 22. At this time, the first material layer 41 completely separates the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 11, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 in step S200 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and cover the first sidewall 322; the second passivation layer 50B in step S300 is disposed flush with the top surface of the first material layer 41 and extends toward the termination region 22. At this time, the first material layer 41 also completely separates the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 12, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 in step S200 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and cover the first sidewall 322; the second passivation layer 50B in step S300 is configured to extend toward the termination region 22 from a position where the sidewall of the first material layer 41 facing the termination region 22 is higher than 1/2h (the height of the sidewall of the first material layer 41 facing the termination region 22 is h). At this time, the first material layer 41 may also completely separate the second passivation layer 50B and the metal electrode layer 32.
In some embodiments, as shown in fig. 13, the metal electrode layer 32 has a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22, the first material layer 41 in step S200 being configured to extend from an edge of the top surface 321 toward the first sidewall 322 and cover the first sidewall 322; the second passivation layer 50B in step S300 is configured to cover a portion of the top surface 321 of the metal electrode layer 32 and extend toward the termination region 22 along the first material layer 41 at the location of the top surface 321 and the side wall of the first material layer 41 facing the termination region 22. At this time, the first material layer 41 may partially separate the second passivation layer 50B and the metal electrode layer 32, and the second passivation layer 50B may be in contact with the metal electrode layer 32 at a partial region of the top surface 321 of the metal electrode layer 32.
In some embodiments, as shown in fig. 14, the first material layer 41 in step S200 is configured to be flush with the top surface 321 of the metal electrode layer 32 and extend in a direction toward the wide bandgap drift layer 20; the second passivation layer 50B in step S300 is configured to entirely cover the first material layer 41 and extend toward the terminal region 22. At this time, the first material layer 41 may completely separate the second passivation layer 50B and the metal electrode layer 32.
In some embodiments, as shown in fig. 15, the first material layer 41 in step S200 is configured to be flush with the top surface 321 of the metal electrode layer 32 and extend in a direction toward the wide bandgap drift layer 20; the second passivation layer 50B in step S200 is disposed flush with the top surface of the first material layer 41 and extends toward the termination region 22. At this time, the first material layer 41 also completely separates the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 16, the first material layer 41 in step S200 is configured to be flush with the top surface 321 of the metal electrode layer 32 and extend in a direction toward the wide bandgap drift layer 20; the second passivation layer 50B in step S200 is configured to extend toward the termination region 22 from a position where the sidewall of the first material layer 41 facing the termination region 22 is higher than 1/2h (the height of the sidewall of the first material layer 41 facing the termination region 22 is h). At this time, the first material layer 41 may also completely separate the second passivation layer 50B and the metal electrode layer 32.
In some embodiments, as shown in fig. 17, the first material layer 41 in step S200 is disposed on the first sidewall 322, the first sidewall 322 has a height h, and the first material layer 41 is configured to extend from the first sidewall 322 higher than 1/2h toward the wide bandgap drift layer 20; the second passivation layer 50B in step S300 is disposed flush with the top surface of the first material layer 41 and extends toward the termination region 22. At this time, the first material layer 41 may also completely separate the second passivation layer 50B from the metal electrode layer 32.
In some embodiments, as shown in fig. 18, the first material layer 41 in step S200 is disposed on the first sidewall 322, the first sidewall 322 has a height h, and the first material layer 41 is configured to extend from the first sidewall 322 higher than 1/2h toward the wide bandgap drift layer 20; the second passivation layer 50B in step S300 is configured to extend from the first sidewall 322 higher than the first material layer 41 along the first material layer 41 toward the termination region 22. At this time, the first material layer 41 may partially separate the second passivation layer 50B and the metal electrode layer 32, and the second passivation layer 50B may be in contact with the metal electrode layer 32 at a partial region of the first sidewall 322 of the metal electrode layer 32.
It should be noted that, in some embodiments, when the termination region 22 is distributed on opposite sides of the active region 21, the related preparation methods related to the first material layer 41 and the second passivation layer 50B mentioned in the present disclosure may be formed only on one side of the active region 21, or may be formed on opposite sides of the active region 21, respectively, and the present disclosure is not limited in particular.
The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
In addition, the specific features described in the foregoing embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present disclosure does not further describe various possible combinations.
Claims (4)
1. A power device that is a normal schottky diode, a junction barrier schottky diode, or a hybrid PIN schottky diode, comprising:
A wide band gap substrate;
a wide bandgap drift layer disposed on the wide bandgap substrate;
a termination region and an active region disposed in the wide bandgap drift layer, the active region being located between the termination regions;
the metal electrode layer is arranged on the active region, schottky contact is formed between the metal electrode layer and the active region, and the metal electrode layer is provided with a top surface facing away from the wide-bandgap drift layer and a first side wall facing the terminal region;
a first material layer disposed on a first sidewall of the metal electrode layer;
and a passivation layer entirely or partially covering the first material layer and extending toward the termination region;
the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the passivation layer is c, wherein a > b > c;
the first material layer is configured to be flush with the top surface of the metal electrode layer, extends along the first sidewall in a direction toward the wide bandgap drift layer, and the passivation layer is configured to entirely cover the first material layer and extend toward the termination region, the first material layer entirely separating the metal electrode layer from the passivation layer.
2. A power device that is a normal schottky diode, a junction barrier schottky diode, or a hybrid PIN schottky diode, comprising:
a wide band gap substrate;
a wide bandgap drift layer disposed on the wide bandgap substrate;
an active region disposed in the wide bandgap drift layer, and a termination region disposed in the wide bandgap drift layer and located on one side of the active region;
a first passivation layer disposed on the wide bandgap drift layer, the first passivation layer configured to cover the termination region surface from the active region edge;
the metal electrode layer is arranged on the active region, schottky contact is formed between the metal electrode layer and the active region, the metal electrode layer is provided with a step higher than the first passivation layer, the step is provided with a first side wall facing the first passivation layer, and the first side wall is connected with the first passivation layer;
a first material layer disposed on the first sidewall, a second passivation layer entirely or partially covering the first material layer and extending toward the termination region;
the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the second passivation layer is c, wherein a > b > c;
The first material layer is arranged to be flush with the top surface of the metal electrode layer and extends towards the wide bandgap drift layer, and the passivation layer is arranged to entirely cover the first material layer and extends towards the termination region, the first material layer entirely separating the metal electrode layer from the passivation layer.
3. The power device of claim 2, wherein the material of the first material layer is polyimide;
and/or the material of the first passivation layer is silicon oxide;
and/or the material of the second passivation layer is silicon oxide or silicon nitride.
4. A method for preparing a power device, wherein the power device is a common Schottky diode, a junction barrier Schottky diode or a hybrid PIN Schottky diode,
characterized by comprising the following steps:
providing a first power device structure, wherein the first power device structure comprises a wide-bandgap substrate, a wide-bandgap drift layer arranged on the wide-bandgap substrate, an active region arranged in the wide-bandgap drift layer, a terminal region arranged in the wide-bandgap drift layer and positioned at one side of the active region, a first passivation layer arranged on the wide-bandgap drift layer, the first passivation layer is configured to cover the surface of the terminal region from the edge of the active region, a metal electrode layer arranged on the active region, schottky contact is arranged between the metal electrode layer and the active region, the metal electrode layer is provided with a step higher than the first passivation layer, the step is provided with a first side wall facing towards the first passivation layer and a top surface deviating from the wide-bandgap drift layer, and the first side wall is connected with the first passivation layer;
Forming a first material layer on the first sidewall;
forming a second passivation layer which covers the first material layer completely or partially and extends towards the terminal region, wherein the first material layer completely separates the second passivation layer from the metal electrode layer, the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the second passivation layer is c, and a > b > c;
the step of forming a first material layer on the first sidewall includes:
forming a first material layer on the whole surface of the first power device structure, which is away from the wide-gap substrate;
and removing the first material layer on the top surface of the metal electrode layer and the first material layer on the surface of the first passivation layer by adopting a photoetching process, and reserving the first material layer on the first side wall.
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| CN202310823581.8A CN116722047A (en) | 2021-06-29 | 2021-06-29 | Power device |
| CN202110725060.XA CN113451417B (en) | 2021-06-29 | 2021-06-29 | Power device and preparation method thereof |
| US17/705,906 US20220310822A1 (en) | 2021-03-29 | 2022-03-28 | Power device and method for making the same |
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