CN113451393A - High electron mobility transistor and manufacturing method thereof - Google Patents
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The invention provides a high electron mobility transistor and a manufacturing method thereof, comprising the following steps: the device comprises an epitaxial wafer, a stress ring, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial wafer internally comprises a channel layer; the edge area of the epitaxial wafer is provided with an annular isolation area with a first designated depth, a middle epitaxial wafer is positioned in the middle of the annular isolation area, and the edge area of the middle epitaxial wafer is provided with an annular etching groove with a second designated depth; the stress ring is positioned in the annular etching groove and communicated with the channel layer; the source electrode and the drain electrode are respectively positioned in the first groove and the second groove in the central area of the epitaxial wafer and are communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer. In the mode, the designated position of epitaxial wafer is provided with the stress ring, can produce stress effect to the channel through the stress ring, and corresponding deformation can take place for the crystal lattice, can make electron when passing through the channel, receives the scattering reduction of crystal lattice, and then has improved the electron mobility in the channel.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-electron-mobility transistor and a manufacturing method thereof.
Background
High Electron Mobility Transistors (HEMTs) are commonly used in the design and manufacture of power amplifiers and low noise amplifier circuits; the higher the electron mobility in the channel of the HEMT, the higher the drive current of the HEMT, and the higher the gain, output power, and maximum oscillation frequency of the HEMT. In the related art, the problem of degradation of electron mobility due to scattering of impurities and defects in a crystal is generally solved by reducing the concentrations of impurities and defects in a HEMT crystal; alternatively, the problem of mobility degradation due to surface or interface scattering is solved by optimizing the surface or interface in the vicinity of the channel to improve electron mobility. However, as metal materials and manufacturing processes become mature, the difficulty is high and the realization is not easy by improving or optimizing the crystal quality to improve the electron mobility.
Disclosure of Invention
In view of the above, the present invention provides a high electron mobility transistor and a method for fabricating the same, so that electrons in a channel are less scattered by a crystal lattice, thereby improving electron mobility in the channel.
In a first aspect, an embodiment of the present invention provides a high electron mobility transistor, including: the device comprises an epitaxial wafer, a stress ring, a gate electrode, and a source electrode and a drain electrode which are positioned on two sides of the gate electrode; the inside of the epitaxial wafer comprises a channel layer; the edge area of the epitaxial wafer is provided with an annular isolation area with a first designated depth, and the annular isolation area is used for blocking two-dimensional electron gas in the channel layer; the middle epitaxial wafer is positioned in the middle of the annular isolation region, and an annular etching groove with a second specified depth is formed in the edge region of the middle epitaxial wafer; the stress ring is positioned in the annular etching groove and communicated with the channel layer; the stress ring is used for generating stress action on the channel layer; the source electrode is positioned in the first groove in the central area of the epitaxial wafer and is communicated with the channel layer; the drain electrode is positioned in the second groove in the central area of the epitaxial wafer and is communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer.
Furthermore, the stress ring is arranged in the annular etching groove in a deposition or generation mode; the stress ring is used for generating tensile or compressive stress on the channel layer.
Further, the second designated depth is 50nm to 500 nm; the stress ring is parallel to the upper surface of the epitaxial wafer;
further, the height of the source electrode and the drain electrode is 50nm-300 nm; the height of the gate electrode is 50nm-500 nm; the depth of the first groove and the depth of the second groove are smaller than the height of the source electrode and the height of the drain electrode, respectively.
Further, the high electron mobility transistor further includes an insulating layer; the thickness of the insulating layer is 50nm-1000 nm; the insulating layer is positioned on the upper layer of the epitaxial wafer and is in contact with the annular isolation region, the stress ring, the gate electrode, the source electrode and the drain electrode.
Further, the surface of the insulating layer comprises three through holes; the first through hole is communicated with the surface of the source electrode, the second through hole is communicated with the surface of the gate electrode, and the third through hole is communicated with the surface of the drain electrode.
Furthermore, the high electron mobility transistor also comprises three metal layers which are not in contact with each other; the first metal layer is in contact with the first through hole region of the insulating layer and is positioned on the upper layer of the first through hole region; the second metal layer is in contact with the second through hole area of the insulating layer and is positioned on the upper layer of the second through hole area; the third metal layer is in contact with the third through hole region of the insulating layer and is located on the upper layer of the third through hole region.
Further, the first metal layer is used for leading out a source electrode; the second metal layer is used for leading out a gate electrode; the third metal layer is used for leading out the drain electrode.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a high electron mobility transistor, including: obtaining an epitaxial wafer, wherein the interior of the epitaxial wafer comprises a channel layer; setting an annular isolation area with a first specified depth in the edge area of the epitaxial wafer in a preset setting mode; the annular isolation region is used for blocking two-dimensional electron gas in the channel layer; etching an annular etching groove with a second specified depth in the edge area of the middle epitaxial wafer by a reactive ion etching technology on the middle epitaxial wafer positioned in the middle part of the annular isolation area; generating a stress ring in the annular etching groove by controlling the conditions of deposition or generation of a preset material; the stress ring is used for generating stress action on the channel layer; generating a source electrode in a first groove in the central area of the epitaxial wafer in a metal deposition, stripping and annealing mode; generating a drain electrode in the second groove in the central area of the epitaxial wafer; generating a gate electrode in an intermediate region between the source electrode and the drain electrode; the source electrode and the drain electrode are respectively communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer.
Further, generating a source electrode in the first groove of the central area of the epitaxial wafer in a metal deposition, stripping and annealing mode; generating a drain electrode in the second groove in the central area of the epitaxial wafer; after the step of generating a gate electrode in an intermediate region of the source electrode and the drain electrode, the method further includes: generating an insulating layer on the upper layer of the epitaxial wafer in a deposition mode; generating three through holes in the designated area of the insulating layer by an etching technology; the first through hole is communicated with the surface of the source electrode, the second through hole is communicated with the surface of the gate electrode, and the third through hole is communicated with the surface of the drain electrode; respectively generating three metal layers which are not in contact with each other on the upper layer of the through hole region in a metal deposition mode; the first metal layer is in contact with the first through hole region of the insulating layer, is positioned on the upper layer of the first through hole region and is used for leading out a source electrode; the second metal layer is in contact with the second through hole area of the insulating layer, is positioned on the upper layer of the second through hole area and is used for leading out the gate electrode; the third metal layer is in contact with the third through hole region of the insulating layer, is positioned on the upper layer of the third through hole region and is used for leading out the drain electrode.
The embodiment of the invention has the following beneficial effects:
the invention provides a high electron mobility transistor and a manufacturing method thereof, comprising the following steps: the device comprises an epitaxial wafer, a stress ring, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial wafer internally comprises a channel layer; the edge area of the epitaxial wafer is provided with an annular isolation area with a first designated depth, a middle epitaxial wafer is positioned in the middle of the annular isolation area, and the edge area of the middle epitaxial wafer is provided with an annular etching groove with a second designated depth; the stress ring is positioned in the annular etching groove and communicated with the channel layer; the source electrode and the drain electrode are respectively positioned in the first groove and the second groove in the central area of the epitaxial wafer and are communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer. In the mode, the designated position of epitaxial wafer is provided with the stress ring, can produce stress effect to the channel through the stress ring, and corresponding deformation can take place for the crystal lattice, can make electron when passing through the channel, receives the scattering reduction of crystal lattice, and then has improved the electron mobility in the channel.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another hemt according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another hemt according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another high electron mobility transistor according to an embodiment of the present invention.
Icon:
1-an epitaxial wafer; 2-stress ring; 3-a gate electrode; 4-a source electrode; 5-a drain electrode; 6-a channel layer; 7-an annular isolation region; 8-an insulating layer; 91-first metal layer; 92-a second metal layer; 93-third metal layer.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
High Electron Mobility Transistors (HEMTs) are commonly used in the design and manufacture of power amplifiers and low noise amplifier circuits; the higher the electron mobility in the channel of the HEMT, the higher the drive current of the HEMT, and the higher the gain, output power, and maximum oscillation frequency of the HEMT. In the related art, the method for improving the electron mobility in the HEMT channel mainly includes two methods: first, by reducing the concentration of impurities and defects in the HEMT crystal, the problem of electron mobility degradation due to scattering of impurities and defects in the crystal is solved, thereby improving electron mobility. Second, by optimizing the surface or interface near the channel, mobility degradation caused by surface or interface scattering is reduced, thereby improving electron mobility. However, as metal materials and manufacturing processes become mature, the difficulty is high and the realization is not easy by improving or optimizing the crystal quality to improve the electron mobility. Based on this, the high electron mobility transistor and the manufacturing method thereof provided by the embodiments of the present invention may be applied to microelectronic fabrication, and in particular, may be applied to a semiconductor device requiring high electron mobility.
To facilitate understanding of the present embodiment, a detailed description will be first given of a high electron mobility transistor disclosed in an embodiment of the present invention, as shown in fig. 1, the high electron mobility transistor includes: the device comprises an epitaxial wafer 1, a stress ring 2, a gate electrode 3, and a source electrode 4 and a drain electrode 5 which are positioned on two sides of the gate electrode 3; the inside of the epitaxial wafer 1 includes a channel layer 6;
referring to fig. 1 (a), a top view of a transistor is shown without showing a channel layer inside an epitaxial wafer; fig. 1 (b) is a cross-sectional view of the transistor along the dotted line, the bottom layer of the transistor is an epitaxial wafer (e.g., the square region in fig. 1), and the material of the epitaxial wafer may be GaN, GaAs, or the like; different materials of the epitaxial layer will typically produce different high electron mobility transistors. For example, if the material of the epitaxial wafer is gallium nitride GaN, the high electron mobility transistor is a gallium nitride high electron mobility transistor (GaN HEMT).
The epitaxial wafer includes a channel layer, the channel layer includes two-dimensional electron gas, wherein the two-dimensional electron gas is a system which uses physical methods such as quantum confinement to limit the movement of electron group in one direction to a small range, and can move freely in the other two directions, namely a two-dimensional electron system, and the channel layer is on the upper half layer of the epitaxial wafer, such as the position of the channel layer 6 shown in fig. 1.
In order to enable the two-dimensional electron gas in the channel layer to move in the channel layer without moving out of the channel layer, an annular isolation region 7 with a first designated depth may be provided in an edge region of the epitaxial wafer 1, the annular isolation region being used to block the two-dimensional electron gas in the channel layer 6; the lower angle alignment area shown in fig. 1 is the annular isolation area; the first specified depth is typically greater than the depth of the channel layer in the epitaxial wafer so that the annular isolation region can block the two-dimensional electron gas in the channel layer. The annular isolation region can be generated by ion implantation or shallow trench isolation.
In order to improve the electron mobility in the channel layer, the middle epitaxial wafer is positioned in the middle of the annular isolation region 7, and an annular etching groove with a second specified depth is arranged in the edge region of the middle epitaxial wafer; the stress ring 2 is positioned in the annular etching groove and communicated with the channel layer 6; the stress ring 2 is used for generating stress action on the channel layer 6;
referring to fig. 1, the horizontal line region and the middle region of other shapes in the figure are the middle part of the annular isolation region, and an annular etching groove with a second designated depth can be arranged in the edge region of the middle epitaxial wafer, i.e. the horizontal line region in the figure, by an ion etching technology, and the distribution and the size of the annular etching groove can be preset according to actual needs and applications. The annular etching groove is provided with the stress ring, and the stress ring can be generated in a deposition or growth mode; the stress ring may be a dielectric material such as Si3N4、SiO2Etc.; the GaAs HEMT may be an AlGaAs or GaAs crystal, and the GaN HEMT may be an AlGaN, GaN or AlN crystal. In the working process of the high electron mobility transistor, the stress ring can generate tensile or extrusion stress on the channel layer, the crystal lattice can generate corresponding deformation, electrons can be reduced by scattering of the crystal lattice when passing through the channel, and then the electron mobility in the channel is improved.
The source electrode 4 is positioned in a first groove in the central region of the epitaxial wafer and is communicated with the channel layer 6; the drain electrode 5 is positioned in the second groove in the central area of the epitaxial wafer and is communicated with the channel layer 6; the gate electrode 3 is in contact with the upper surface of the epitaxial wafer 1.
The central epitaxial wafer is positioned in the central area of the stress ring, and a first groove and a second groove are formed in the designated position of the central epitaxial wafer; the source electrode 4 is positioned in the first groove, and the drain electrode 5 is positioned in the second groove; the gate electrode 3 is generally located in the intermediate region between the source electrode and the drain electrode, and directly contacts the upper surface of the epitaxial wafer without communicating with the channel layer. The depth of the first recess and the second recess is generally greater than the depth of the channel layer in the epitaxial wafer, so that the source electrode and the drain electrode located in the recesses communicate with the channel layer. The source electrode and the drain electrode may be made of an ohmic contact metal, and the gate electrode may be made of an ohmic contact metal or another metal. In addition, the source electrode and the drain electrode are usually connected with two-dimensional electron gas by metal deposition, stripping and annealing.
The high electron mobility transistor includes: the device comprises an epitaxial wafer, a stress ring, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial wafer internally comprises a channel layer; the edge area of the epitaxial wafer is provided with an annular isolation area with a first designated depth, a middle epitaxial wafer is positioned in the middle of the annular isolation area, and the edge area of the middle epitaxial wafer is provided with an annular etching groove with a second designated depth; the stress ring is positioned in the annular etching groove and communicated with the channel layer; the source electrode and the drain electrode are respectively positioned in the first groove and the second groove in the central area of the epitaxial wafer and are communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer. In the mode, the designated position of epitaxial wafer is provided with the stress ring, can produce stress effect to the channel through the stress ring, and corresponding deformation can take place for the crystal lattice, can make electron when passing through the channel, receives the scattering reduction of crystal lattice, and then has improved the electron mobility in the channel.
The embodiment provides another high electron mobility transistor, which is implemented on the basis of the above embodiment, wherein the stress ring 2 is disposed in the annular etching groove by deposition or generation; the stress ring is used for generating tensile or compressive stress on the channel layer. Specifically, stress rings with preset distribution and size are generated in the annular etching grooves by controlling the deposition or growth conditions of materials, such as the temperature, the temperature change process, the gas pressure change process and the like of the deposition or growth of the materials. Generally, after the stress ring generates tensile or compressive stress on the channel layer, the crystal lattice generates corresponding deformation, so that electrons are subjected to the scattering reduction of the crystal lattice when passing through the channel, and the electron mobility in the channel is further improved.
The second specified depth is 50nm to 500 nm; the stress ring is parallel to the upper surface of the epitaxial wafer;
in order to enable the stress ring to be parallel to the upper surface of the epitaxial wafer, a second designated depth of the annular etching groove can be set to be 50nm-500nm, the specific depth can be set according to the depth of the channel layer on the epitaxial wafer, and the finally set second designated depth is generally larger than the depth of the channel layer on the epitaxial wafer, so that the stress ring can generate stress action on the channel layer. Because electrodes and other material layers need to be arranged on the upper layer of the central area of the epitaxial wafer, the stress ring is usually arranged to be parallel to the upper edge face of the epitaxial wafer, so that the arrangement of other material layers on the upper layer of the epitaxial wafer is facilitated, and the stress ring can be prevented from generating stress on other materials.
The height of the source electrode and the drain electrode is 50nm-300 nm; the height of the gate electrode is 50nm-500 nm; the depth of the first groove and the depth of the second groove are smaller than the height of the source electrode and the height of the drain electrode, respectively.
In order to make the upper surfaces of the source electrode and the drain electrode higher than the upper surface of the epitaxial wafer, the heights of the source electrode and the drain electrode can be set to be 50nm-300nm, and meanwhile, the depth of the first groove and the depth of the second groove are set to be smaller than the height of the source electrode and the height of the drain electrode respectively, so that the electrodes can be led out. The specific heights of the source electrode, the drain electrode, and the gate electrode may be set within a height range according to actual needs. The source electrode and the drain electrode can be generated through metal deposition, stripping and annealing, so that the source electrode and the drain electrode are communicated with two-dimensional electron gas.
In the above manner, the stress ring is disposed in the annular etching groove by deposition or generation, and is used for generating tensile or compressive stress on the channel layer, thereby improving electron mobility in the channel. In addition, the generated size distribution of the electrode and the size distribution of the stress ring are also arranged, so that the stability of the high electron mobility transistor is improved, and the stress of the stress ring on other parts of the transistor is avoided. And further, the gain, the output power and the maximum oscillation frequency of the HEMT are improved.
The present invention also provides another high electron mobility transistor, as shown in fig. 2, further including an insulating layer 8; the thickness of the insulating layer 8 is 50nm-1000 nm; the insulating layer is positioned on the upper layer of the epitaxial wafer and is in contact with the annular isolation region, the stress ring, the gate electrode, the source electrode and the drain electrode.
In order to stably lead out the electrodes and ensure the stability of each electrode, an insulating layer is generally disposed on the upper layers of the gate electrode, the source electrode and the drain electrode; the insulating layer, which is typically a dielectric material such as Si, contacts the upper surface of the epitaxial wafer, the annular isolation region, the stress ring, the gate electrode, the source electrode, and the drain electrode3N4，SiO2(ii) a Alternatively, the insulating layer may be grown as an upper layer on the epitaxial wafer, typically by deposition of a dielectric. The thickness of the insulating layer is usually 50nm-1000nm, and the specific thickness can be set according to actual needs, but must be higher than the electrode protruding from the surface of the epitaxial wafer.
With continued reference to fig. 2, in order to extract the source electrode, the drain electrode, and the gate electrode, the surface of the insulating layer includes three through holes; wherein the first via hole communicates with the surface of the source electrode, the second via hole (shown in fig. 2 (a)) communicates with the surface of the gate electrode, and the third via hole communicates with the surface of the drain electrode.
The position of the second through hole can be seen in fig. 2 (a), which is a top view. The first through hole is communicated with the surface of the source electrode and used for leading out the source electrode; the same second through hole is communicated with the surface of the gate electrode and is used for leading out the gate electrode; the same third through hole is communicated with the surface of the drain electrode and is used for leading out the drain electrode; the electrodes can be specifically led out through a power-on lead, a connecting wire or metal deposition.
In addition, the through hole can be formed at a designated position of the insulating layer by reactive ion etching or other etching means, and reaches the surface of the ohmic contact metal (drain electrode and source electrode) and the surface of the gate metal (gate electrode).
In order to extract the source electrode, the gate electrode and the drain electrode, the present embodiment further provides a high electron mobility transistor, which further includes three metal layers that are not in contact with each other, as shown in fig. 3; wherein the first metal layer 91 is in contact with the first via region of the insulating layer, and is located on the upper layer of the first via region; the second metal layer 92 (shown in fig. 3 (a)) is in contact with the second via region of the insulating layer, on top of the second via region; the third metal layer 93 is in contact with the third via region of the insulating layer, and is located on an upper layer of the third via region. The first metal layer is used for leading out a source electrode; the second metal layer is used for leading out a gate electrode; the third metal layer is used for leading out the drain electrode.
Specifically, the metal layer can realize the extraction of the source electrode, the drain electrode and the gate electrode in a metal deposition mode. The first metal layer, the second metal layer and the third metal layer are not contacted with each other, namely are insulated from each other, the heights of the upper surfaces of the three metal layers can be consistent, and the specific heights can be set according to actual requirements; the metal layers may have other dimensions according to actual needs, and the sizes of the first metal layer, the second metal layer, and the third metal layer shown in fig. 3, for example, may not be flush with the outer edges of the epitaxial wafer and the insulating layer, or may be flush with the outer edges of the epitaxial wafer and the insulating layer.
In the above manner, in order to extract the source electrode, the gate electrode and the drain electrode, different metal layers are arranged on the upper layer of the through hole, so that the electrode can be stably extracted, the working stability of the high electron mobility transistor is improved, and the working effect of the high electron mobility transistor is further improved.
An embodiment of the present invention provides a method for manufacturing a high electron mobility transistor, as shown in fig. 4, the method includes the following steps:
step S402, obtaining an epitaxial wafer, wherein the interior of the epitaxial wafer comprises a channel layer;
an epitaxial wafer as shown in fig. 5, the epitaxial wafer includes a channel layer inside, the channel layer includes two-dimensional electron gas, wherein the position of the channel layer can be set according to actual needs, and is usually set at the upper position of the epitaxial wafer; the bottom layer of the epitaxial layer also typically includes a substrate, buffer layer, etc., where the dielectric material of each layer is typically different. Specifically, an epitaxial wafer material may be prepared as needed.
Step S404, setting an annular isolation area with a first specified depth in the edge area of the epitaxial wafer in a preset setting mode; the annular isolation region is used for blocking two-dimensional electron gas in the channel layer;
the preset setting mode can be an ion implantation mode or a shallow groove isolation mode. Referring to the epitaxial wafer shown in fig. 6, the annular isolation region is generally referred to as an isolation region for blocking two-dimensional electron gas in the channel layer. The first designated depth is larger than the depth of the channel layer on the epitaxial wafer.
Specifically, ion beams can be irradiated onto the surface of the epitaxial wafer and penetrate into the channel layer on the surface, so that the surface composition and the performance of the material are improved. Typically the ion beam is formed by: the method comprises the steps of bombarding atoms of chemical elements with free electrons or other particles to enable the atoms to lose electrons to form ions, accelerating the ions through an electric field, and forming an ion beam with energy of 103-106 electron volts. When the ion beam irradiates the surface of the epitaxial wafer, the penetration depth is generally within the range of 100-1000 atomic layers from the surface. The material surface may have different properties depending on the kind of ions and materials. In this embodiment, ions are implanted into the edge region of the epitaxial wafer, and a ring-shaped isolation region is formed in the edge region of the epitaxial wafer, so that the two-dimensional electron gas of the channel layer is isolated by the ring-shaped isolation region.
And a shallow groove isolation mode can be adopted, a groove is formed in the edge area of the epitaxial wafer through a silicon nitride mask after deposition, patterning and etching, deposited oxide is filled in the groove for isolation, and an annular isolation area is generated to isolate the two-dimensional electron gas of the channel layer.
Step S406, etching an annular etching groove with a second specified depth in the edge area of the middle epitaxial wafer of the middle part of the annular isolation area by a reactive ion etching technology;
referring to the epitaxial wafer shown in fig. 7, at the position of the middle epitaxial wafer shown in (a), i.e. the middle part of the ring-shaped isolation region, etching is performed in a vacuum system by using molecular gas plasma through a reactive ion etching technique, and anisotropic etching is achieved by using ion-induced chemical reaction, i.e. ion energy is used to form an easily-etched damage layer on the surface of the layer to be etched and promote chemical reaction, and ions can also remove surface products to expose the clean etching surface, so as to finally obtain the ring-shaped etching groove with the second specified depth. The second specified depth is typically greater than the first specified depth.
Step S408, generating a stress ring in the annular etching groove by controlling the conditions of deposition or generation of the preset material; the stress ring is used for generating stress action on the channel layer;
referring to the epitaxial wafer shown in fig. 8, a stress ring is disposed in the annular etched groove of the epitaxial wafer. Specifically, the stress ring may be generated in the annular etching groove by controlling the conditions of deposition or generation of the predetermined material, for example, controlling the temperature, temperature variation process, air pressure variation process, etc. of deposition or growth of the material; the stress ring may be a dielectric material such as Si3N4，SiO2For example, a GaAs HEMT may be a crystal of AlGaAs, GaAs or the like, and a GaN HEMT may be a crystal of AlGaN, GaN, AlN or the like. The stress ring can realize tensile or compressive stress on the channel layer of the epitaxial wafer.
Step S410, generating a source electrode in a first groove in the central area of an epitaxial wafer in a metal deposition, stripping and annealing mode; generating a drain electrode in the second groove in the central area of the epitaxial wafer; generating a gate electrode in an intermediate region between the source electrode and the drain electrode; the source electrode and the drain electrode are respectively communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer.
Referring to the epitaxial wafer shown in fig. 9, a central epitaxial wafer located in the central region of the stress ring is provided with a first groove and a second groove at specified positions of the central epitaxial wafer; the source electrode is positioned in the first groove, and the drain electrode is positioned in the second groove; the depth of the first recess and the second recess is generally greater than the depth of the channel layer in the epitaxial wafer, so that the source electrode and the drain electrode located in the recesses communicate with the channel layer. The material of the source and drain electrodes may be an ohmic contact metal. Specifically, the source electrode and the drain electrode are usually communicated with the two-dimensional electron gas at the designated position of the central epitaxial wafer by means of metal deposition, stripping and annealing. Typical values for the thickness of the ohmic contact metal are 50-300 nm.
Further, with continued reference to the transistor shown in fig. 1, the gate electrode is typically located in an intermediate region between the source and drain electrodes, directly contacting the upper surface of the epitaxial wafer, and not communicating with the channel layer. The gate electrode may be made of an ohmic contact metal or another metal. Specifically, the gate electrode may also be referred to as a gate metal, and is typically formed in a different manner than the source and drain electrodes, and the gate electrode may be formed directly on the surface of the epitaxial wafer without communicating with the channel layer. Typical values for the gate metal thickness are 50-500 nm.
In the mode, the stress ring is arranged at the designated position of the epitaxial wafer, the stress effect can be generated on the channel through the stress ring, the crystal lattice can deform correspondingly, electrons can be reduced by scattering of the crystal lattice when passing through the channel, the electron mobility in the channel is further improved, and the gain, the output power and the maximum oscillation frequency of the HEMT are improved.
In order to further improve the working effect of the electron mobility transistor, the method further comprises:
step 501, generating an insulating layer on the upper layer of the epitaxial wafer in a deposition mode;
the insulating layer is typically a dielectric material, such as Si3N4，SiO2Etc., the thickness of the insulating layer is generally 50 to 1000 nm. Specifically, an insulating layer, see the hemt shown in fig. 10, may be formed on the upper layer of the epitaxial wafer in a conventional deposition manner, and the insulating layer is in contact with the lower electrode, the epitaxial wafer, the stress ring, and the annular isolation region.
502, generating three through holes in a designated area of an insulating layer by an etching technology; the first through hole is communicated with the surface of the source electrode, the second through hole is communicated with the surface of the gate electrode, and the third through hole is communicated with the surface of the drain electrode;
the etching technique may be reactive ion etching or other etching means, and through holes are formed in the designated regions of the insulating layer, i.e., above the source electrode, the drain electrode, and the gate electrode, so that the first through hole is communicated with the surface of the source electrode, the second through hole is communicated with the surface of the gate electrode, and the third through hole is communicated with the surface of the drain electrode. Specific transistor structure reference is made to the high electron mobility transistor shown in fig. 2.
Step 503, respectively generating three metal layers which are not in contact with each other on the upper layer of the through hole region in a metal deposition mode; the first metal layer is in contact with the first through hole region of the insulating layer, is positioned on the upper layer of the first through hole region and is used for leading out a source electrode; the second metal layer is in contact with the second through hole area of the insulating layer, is positioned on the upper layer of the second through hole area and is used for leading out the gate electrode; the third metal layer is in contact with the third through hole region of the insulating layer, is positioned on the upper layer of the third through hole region and is used for leading out the drain electrode.
In order to enable the electrodes to be led out, referring to the high electron mobility transistor shown in fig. 3, three metal layers which are not in contact with each other are respectively generated on the upper layer of the through hole region, and the metal layers can be in contact with the upper surfaces of the corresponding electrodes by means of metal deposition. Specifically, the first metal layer is in contact with a first through hole region of the insulating layer, is positioned on the upper layer of the first through hole region, and is used for leading out a source electrode; the second metal layer is in contact with the second through hole area of the insulating layer, is positioned on the upper layer of the second through hole area and is used for leading out the gate electrode; the third metal layer is in contact with the third through hole region of the insulating layer, is positioned on the upper layer of the third through hole region and is used for leading out the drain electrode. The mode can safely and stably lead out the electrode, and further improves the working effect of the high electron mobility transistor.
In the mode, the stress environment of the HEMT channel is adjusted by manufacturing a circle of stress ring on the periphery of the HEMT device, and the electron mobility in the HEMT channel is improved, so that the gain, the output power and the maximum oscillation frequency of the HEMT are improved. The method has the advantages of simple process, strong practicability, compatibility with the existing process and large-scale application.
The method for manufacturing the high electron mobility transistor provided by the embodiment of the invention has the same technical characteristics as the high electron mobility transistor provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases for those skilled in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that the following embodiments are merely illustrative of the present invention, and not restrictive, and the scope of the present invention is not limited thereto: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A high electron mobility transistor, comprising: the device comprises an epitaxial wafer, a stress ring, a gate electrode, and a source electrode and a drain electrode which are positioned on two sides of the gate electrode;
the epitaxial wafer comprises a channel layer inside; an annular isolation region with a first designated depth is arranged in the edge region of the epitaxial wafer and is used for blocking two-dimensional electron gas in the channel layer;
the middle epitaxial wafer is positioned in the middle of the annular isolation region, and an annular etching groove with a second specified depth is formed in the edge region of the middle epitaxial wafer; the stress ring is positioned in the annular etching groove and communicated with the channel layer; the stress ring is used for generating stress action on the channel layer;
the source electrode is positioned in a first groove in the central region of the epitaxial wafer and is communicated with the channel layer; the drain electrode is positioned in a second groove in the central area of the epitaxial wafer and is communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer.
2. The hemt of claim 1, wherein said stress ring is deposited or grown in said annular etched recess; the stress ring is used for generating tensile or compressive stress on the channel layer.
3. The hemt of claim 1, wherein said second specified depth is between 50nm and 500 nm; the stress ring is parallel to the upper surface of the epitaxial wafer.
4. The hemt of claim 1, wherein said source and drain electrodes have a height of 50nm-300 nm; the height of the gate electrode is 50nm-500 nm; the depth of the first groove and the depth of the second groove are smaller than the height of the source electrode and the height of the drain electrode, respectively.
5. The hemt of claim 1, further comprising an insulating layer; the thickness of the insulating layer is 50nm-1000 nm;
the insulating layer is located on the upper layer of the epitaxial wafer and is in contact with the annular isolation region, the stress ring, the gate electrode, the source electrode and the drain electrode.
6. The hemt of claim 5, wherein the surface of said insulating layer comprises three through holes; wherein the first via is in communication with the source electrode surface, the second via is in communication with the gate electrode surface, and the third via is in communication with the drain electrode surface.
7. The hemt of claim 6, further comprising three metal layers not in contact with each other; wherein the first metal layer is in contact with the first through hole region of the insulating layer and is positioned on the upper layer of the first through hole region; the second metal layer is in contact with the second through hole area of the insulating layer and is positioned on the upper layer of the second through hole area; the third metal layer is in contact with the third through hole region of the insulating layer and is located on the upper layer of the third through hole region.
8. The hemt of claim 7, wherein said first metal layer is used to extract said source electrode; the second metal layer is used for leading out the gate electrode; the third metal layer is used for leading out the drain electrode.
9. A method for fabricating a high electron mobility transistor, comprising:
obtaining an epitaxial wafer, wherein the interior of the epitaxial wafer comprises a channel layer;
setting an annular isolation region with a first specified depth in an edge region of the epitaxial wafer in a preset setting mode; the annular isolation region is used for blocking two-dimensional electron gas in the channel layer;
etching an annular etching groove with a second specified depth in the edge area of the middle epitaxial wafer positioned in the middle part of the annular isolation area by a reactive ion etching technology;
generating a stress ring in the annular etching groove by controlling the conditions of deposition or generation of a preset material; wherein the stress ring is used for generating stress action on the channel layer;
generating a source electrode in the first groove of the central area of the epitaxial wafer in a metal deposition, stripping and annealing mode; generating a drain electrode in the second groove in the central area of the epitaxial wafer; generating a gate electrode in an intermediate region between the source electrode and the drain electrode; the source electrode and the drain electrode are respectively communicated with the channel layer; the gate electrode is in contact with an upper surface of the epitaxial wafer.
10. The method of claim 9, wherein a source electrode is formed in the first recess in the central region of the epitaxial wafer by metal deposition, lift-off and annealing; generating a drain electrode in the second groove in the central area of the epitaxial wafer; after the step of generating a gate electrode in an intermediate region between the source electrode and the drain electrode, the method further includes:
generating an insulating layer on the upper layer of the epitaxial wafer in a deposition mode;
generating three through holes in the designated area of the insulating layer by an etching technology; wherein a first via is in communication with the source electrode surface, a second via is in communication with the gate electrode surface, and a third via is in communication with the drain electrode surface;
respectively generating three metal layers which are not in contact with each other on the upper layer of the through hole region in a metal deposition mode; the first metal layer is in contact with the first through hole region of the insulating layer, is positioned on the upper layer of the first through hole region and is used for leading out the source electrode; the second metal layer is in contact with the second through hole area of the insulating layer, is positioned on the upper layer of the second through hole area and is used for leading out the gate electrode; and the third metal layer is in contact with the third through hole region of the insulating layer, is positioned on the upper layer of the third through hole region and is used for leading out the drain electrode.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257686A (en) * | 2016-04-07 | 2016-12-28 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacture method thereof |
| JP2018186142A (en) * | 2017-04-25 | 2018-11-22 | 株式会社村田製作所 | Semiconductor device |
| US20190198384A1 (en) * | 2017-12-22 | 2019-06-27 | Vanguard International Semiconductor Corporation | Semiconductor device with two-part insulation structure within non-active region |
| CN112216736A (en) * | 2019-07-10 | 2021-01-12 | 联华电子股份有限公司 | High electron mobility transistor and method of fabricating the same |
-
2021
- 2021-06-30 CN CN202110733990.XA patent/CN113451393A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257686A (en) * | 2016-04-07 | 2016-12-28 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacture method thereof |
| JP2018186142A (en) * | 2017-04-25 | 2018-11-22 | 株式会社村田製作所 | Semiconductor device |
| US20190198384A1 (en) * | 2017-12-22 | 2019-06-27 | Vanguard International Semiconductor Corporation | Semiconductor device with two-part insulation structure within non-active region |
| CN112216736A (en) * | 2019-07-10 | 2021-01-12 | 联华电子股份有限公司 | High electron mobility transistor and method of fabricating the same |
Non-Patent Citations (1)
| Title |
|---|
| 赵正平: "《宽禁带半导体高频及微波功率器件与电路》", 31 December 2017 * |
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