CN113448129A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN113448129A CN113448129A CN202110732330.XA CN202110732330A CN113448129A CN 113448129 A CN113448129 A CN 113448129A CN 202110732330 A CN202110732330 A CN 202110732330A CN 113448129 A CN113448129 A CN 113448129A
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Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
Abstract
The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a display area, a first terminal area and a second terminal area, the first terminal area and the second terminal area are arranged on two sides of the display area, a plurality of first terminals are arranged in the first terminal area, a plurality of second terminals are arranged in the second terminal area, a plurality of first signal lines are arranged in the display area, first ends of the first signal lines are electrically connected with the first terminals, and second ends of the first signal lines are electrically connected with the second terminals; the first-class signal lines are used for outputting common electrode signals located on the side of a color film substrate in the display panel, so that the common electrode signals located on two sides of the display area are arranged in the display area in a wiring mode, the width of frames on two sides of the display panel is reduced, meanwhile, the delay degree of the common electrode signals transmitted from the side of the array substrate to the side of the color film substrate is reduced, and real extremely narrow-frame display of the periphery of the display device is achieved under the condition that the display effect of the display device is not affected.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
With the gradual development of liquid crystal displays, the existing products are continuously developed in the directions of high resolution, narrow frame, light weight and thinning, and the technology of ultra-narrow frame is developed, and in the technology of ultra-narrow frame of "three narrow and one wide", a scanning line data line driving same-side design display product (GCOF) is used.
However, in the GCOF products produced by mass production in the industry at present, since a part of the common electrode signal routing lines are disposed on the two side frames outside the display area, the frame width of the display panel cannot be less than 0.9mm, and thus the display device is difficult to meet the requirement of an ultra-narrow frame.
Therefore, a display panel and a display device are needed to solve the above technical problems.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which are used for improving the technical problem that the width of a frame of the display device is increased due to the fact that a part of common electrode signal routing is arranged on frames on two sides of a display area in the display device in the prior art.
The embodiment of the application provides a display panel, which comprises a display area, a first terminal area and a second terminal area, wherein the first terminal area and the second terminal area are arranged on two sides of the display area; wherein the display panel includes:
a plurality of first terminals disposed within the first terminal region;
a plurality of second terminals disposed within the second terminal area; and
and the first ends of the first signal lines are electrically connected with the first terminals, and the second ends of the first signal lines are electrically connected with the second terminals.
Optionally, in some embodiments of the present application, each of the first type signal traces is connected in parallel with another of the first type signal traces.
Optionally, in some embodiments of the present application, the display panel further includes an array substrate, the array substrate is further provided with a first common electrode layer and a transparent conductive layer located on the first common electrode layer, the first terminal is disposed on the transparent conductive layer, and the first end of the first type signal line is electrically connected to the first common electrode layer through the transparent conductive layer.
Optionally, in some embodiments of the present application, the display panel further includes a plurality of sub-pixels arranged in an array, and each of the first type signal traces is disposed between two adjacent sub-pixels arranged along the first direction.
Optionally, in some embodiments of the present application, the display panel further includes a scan line and a power supply cathode trace, where the scan line includes a first sub-scan line extending along the first direction and a second sub-scan line extending along the second direction, and each of the first sub-scan lines is electrically connected to its corresponding second sub-scan line through an input point;
the second sub-scanning line and the power source cathode wiring respectively extend from the first terminal area to the second terminal area and are arranged in parallel with the first type of signal wiring.
Optionally, in some embodiments of the present application, the display panel further includes a plurality of second-type signal traces, the second-type signal traces are parallel to the first-type signal traces, and each second-type signal trace extends from the first terminal area to the second terminal area;
each second-type signal routing is arranged between two adjacent sub-pixels arranged along the first direction, and each second-type signal routing is used for transmitting a first common electrode signal on the side of the array substrate.
Optionally, in some embodiments of the present application, the number of the first type signal traces and the second type signal traces in the display area are equal.
Optionally, in some embodiments of the present application, at least two subpixels with different colors are spaced between each second-type signal trace and the adjacent first-type signal trace.
Optionally, in some embodiments of the present application, the display panel further includes a color film substrate, and an electrical connection member disposed between the array substrate and the color film substrate;
the color film substrate comprises a second common electrode layer, and the second common electrode layer is electrically connected with the second terminal through the electric connecting piece.
The application also provides a display device, which comprises a plurality of chip on films and the display panel, wherein the chip on films are arranged on one side, close to the first terminal area, of the display panel;
the chip on film is internally provided with a grid driving circuit, and the grid driving circuit comprises cascaded multi-stage grid driving units and scanning lines connected with the multi-stage grid driving units.
The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a display area, a first terminal area and a second terminal area, the first terminal area and the second terminal area are arranged on two sides of the display area, a plurality of first terminals are arranged in the first terminal area, a plurality of second terminals are arranged in the second terminal area, a plurality of first signal lines are arranged in the display area, first ends of the first signal lines are electrically connected with the first terminals, and second ends of the first signal lines are electrically connected with the second terminals; the first-class signal lines are used for outputting common electrode signals located on the side of a color film substrate in the display panel, so that the common electrode signals located on two sides of the display area are arranged in the display area in a wiring mode, the width of frames on two sides of the display panel is reduced, meanwhile, the delay degree of the common electrode signals transmitted from the side of the array substrate to the side of the color film substrate is reduced, and real extremely narrow-frame display of the periphery of the display device is achieved under the condition that the display effect of the display device is not affected.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a top view of a display panel provided in an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a display panel provided in an embodiment of the present application;
fig. 3 is a schematic distribution diagram of a portion of signal traces in a display panel according to a first embodiment of the present disclosure;
fig. 4 is a schematic distribution diagram of a portion of signal traces in a display panel according to a second embodiment of the present disclosure;
fig. 5 is a schematic trace diagram of a display device located on a color film substrate side according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 to 5, an embodiment of the present application provides a display panel 100, including a display area 11 and a non-display area 12 surrounding the display area 11, wherein a first terminal area 121 and a second terminal area 122 are further disposed outside two sides of the display area 11; wherein the display panel 100 includes:
a plurality of first terminals 1211 disposed in the first terminal area 121;
a plurality of second terminals 1221 disposed in the second terminal area 122; and
a plurality of first-type signal lines 111 disposed in the display region 11, wherein a first end of the first-type signal lines 111 is electrically connected to the first terminal 1211, and a second end of the first-type signal lines 111 is electrically connected to the second terminal 1221.
The technical solution of the present application will now be described with reference to specific embodiments.
As shown in fig. 1, a top view of a display panel 100 according to an embodiment of the present disclosure is provided. The display panel 100 includes a display area 11 and a non-display area 12 surrounding the display area 11, a first terminal area 121 and a second terminal area 122 are further disposed outside two sides of the display area 11, and both the first terminal area 121 and the second terminal area 122 are located in the non-display area 12.
In the embodiment of the present application, the display panel 100 further includes:
a plurality of first terminals 1211 disposed in the first terminal area 121;
a plurality of second terminals 1221 disposed in the second terminal area 122; and
a plurality of first-type signal lines 111 disposed in the display region 11, wherein a first end of the first-type signal lines 111 is electrically connected to the first terminal 1211, and a second end of the first-type signal lines 111 is electrically connected to the second terminal 1221.
Further, the first-type signal line 111 is used for transmitting a common electrode signal of the display panel 100 on the color filter substrate 21 side.
It is understood that the display panel 100 shown in fig. 1 has a rectangular shape. Of course, in other possible embodiments, the display panel 100 is not limited to a rectangular shape, but may be a regular or irregular shape such as a circle.
Fig. 2 is a schematic cross-sectional view of a display panel 100 according to an embodiment of the present disclosure. The display panel 100 includes an array substrate 10, a color film substrate 21 arranged in a box-to-box manner with the array substrate 10, a sealant 40, and an electrical connection member 23 arranged between the array substrate 10 and the color film substrate 21.
The array substrate 10 includes a first common electrode layer 113, and a second common electrode layer 22 corresponding to the first common electrode layer 113 is disposed on the color filter substrate 21. The sealant 40, the array substrate 10 and the color filter substrate 21 enclose a liquid crystal accommodating space 30, and the electrical connection member 23 is used for conducting the first common electrode layer 113 on the array substrate 10 and the second common electrode layer 22 on the color filter substrate 21.
It can be understood that the liquid crystal is disposed in the liquid crystal accommodating space 30 by a conventional method in the art, and the detailed description is omitted here.
Specifically, referring to fig. 2, in the present embodiment, a portion of the array substrate 10 corresponding to the first terminal area 121 includes a substrate 112, the first common electrode layer 113 disposed on the substrate 112, a first inorganic film layer 114 disposed on the first common electrode layer 113, and a transparent conductive layer 115 disposed on the first inorganic film layer 114.
Wherein the transparent conductive layer 115 is electrically connected to the first common electrode layer 113. As shown in fig. 2, in this embodiment, the manner of electrically connecting the transparent conductive layer 115 and the first common electrode layer 113 is as follows: a via hole is formed on the first inorganic film layer 114, and the transparent conductive layer 115 is deposited or attached in the via hole.
It should be noted that, a plurality of via holes are disposed on the first terminal area 121 of each array substrate 10, so as to better realize the electrical connection between the first common electrode layer 113 and the transparent conductive layer 115. While only 1 via is schematically indicated in fig. 2.
Specifically, the first terminal 1211 is disposed on the transparent conductive layer 115, and the first end of the first-type signal line 111 is electrically connected to the first common electrode layer 113 through the transparent conductive layer 115. The second common electrode layer 22 is electrically connected to the second terminal 1221 through the electrical connector 23, and the second end of the first signal trace 111 is electrically connected to the second common electrode layer 22 through the electrical connector 23.
In the embodiment of the present application, the substrate 112 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate. The substrate 12 may also be a flexible substrate. Examples thereof include a PET (Polyethylene terephthalate) substrate and a PI (Polyimide) substrate.
In the embodiment of the present application, the array substrate 10 further includes a thin film transistor, the thin film transistor is disposed on the substrate 112 in an array, the thin film transistor includes a drain, and the drain is connected to the first common electrode layer 113. Illustratively, the thin film transistor generally includes three poles: the grid electrode is arranged in the first metal layer, the source electrode and the drain electrode are arranged in the second metal layer, and the source electrode and the drain electrode in the thin film transistor can be interchanged in function according to needs.
In the embodiment of the present application, the first common electrode layer 113 is used for a storage capacitor.
In the embodiment of the present application, the electrical connection element 23 is a conductive gold ball, and the conductive glue ball may be a silver glue ball or a gold glue ball, etc. It can be understood that the conductive rubber ball is formed by mixing the rubber material with elasticity and the metal capable of conducting electricity, such as gold or silver, and the conductive rubber ball has certain elasticity.
More specifically, in the present embodiment, the materials of the first common electrode layer 113, the second common electrode layer 22 and the transparent conductive layer 115 are all indium tin oxide.
In this embodiment, the first inorganic film layer 114 includes a first gate insulating layer disposed on the first common electrode layer 113 and a passivation layer disposed on the first gate insulating layer.
It is understood that the gate insulating layer corresponds to an inorganic film layer between the gate and the source/drain layers in the display region 11 of the display panel 100; the passivation layer corresponds to the inorganic film layer of the source/drain layer far from the gate layer in the display region 11 of the display panel 100.
Fig. 3 is a schematic distribution diagram of a portion of signal traces in the display panel 100 according to the first embodiment of the present application. The display panel 100 further includes a plurality of sub-pixels 116 arranged in an array, and each of the first signal traces 111 is disposed between two adjacent sub-pixels 116 arranged along the first direction D1.
Specifically, the plurality of sub-pixels 116 constitute one pixel unit. Illustratively, each of the pixel units may include 3 sub-pixels 116, such as a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, each of the pixel units may include 4 sub-pixels 116, such as a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. This embodiment is not particularly limited thereto.
It is understood that the arrangement of the sub-pixels 116 in the display panel 100 may not be an array arrangement, but may also be a diamond arrangement or other arrangements.
In this embodiment, the display panel 100 further includes a plurality of second-type signal traces 119, the second-type signal traces 119 are parallel to the first-type signal traces 111, and each of the second-type signal traces 119 extends from the first terminal area 121 to the second terminal area 122;
each of the second signal traces 119 is disposed between two adjacent sub-pixels 116 arranged along the first direction D1, and each of the second signal traces 119 is used for transmitting a first common electrode signal on the side of the array substrate 10.
In the embodiment of the present application, the second signal trace 119 is directly electrically connected to the first common electrode layer 113.
In this embodiment, the display panel 100 further includes a scan line and a power source cathode trace 117, where the scan line includes a first sub-scan line extending along the first direction D1 and a second sub-scan line 118 extending along the second direction D2, and each of the first sub-scan lines is electrically connected to its corresponding second sub-scan line 118 through an input point;
the first direction D1 is perpendicular to the second direction D2, and the second sub-scan line 118 and the power source cathode trace 117 extend from the first terminal area 121 to the second terminal area 122 respectively and are parallel to the first type signal trace 111.
In this embodiment, the number of the first type signal traces 111 and the second type signal traces 119 in the display area 11 is equal. Since the first signal traces 111 are used to output the common electrode signal on the color filter substrate 21 side, and the second signal traces 119 are used to output the common electrode signal on the array substrate 10 side, the number of the first signal traces 111 is equal to that of the second signal traces 119, so that the delay phenomenon of the common electrode signal can be reduced.
In the embodiment of the present application, at least two subpixels 116 with different colors are spaced between each second-type signal trace 119 and the adjacent first-type signal trace 111. The power source cathode trace 117 or the second sub-scan line 118 is spaced between each second-type signal trace 119 and the adjacent first-type signal trace 111.
In the embodiment of the present application, one first-type signal trace 111 is distributed every 6 sub-pixels 116 (different-sized panels, the number of sub-pixels may be changed), and 3 sub-pixels 116 with different colors are spaced between each second-type signal trace 119 and the adjacent first-type signal trace 111. The first type signal trace 111, the power source cathode trace 117, the second sub-scan line 118, the second type signal trace 119, another power source cathode trace 117, and another second sub-scan line 118 form a circulation unit, and the circulation unit is arranged in the display area 11 along the first direction D1.
In view of the technical problem in the prior art that the frame width of the display device 50 is increased due to the fact that a portion of the common electrode signal traces of the display device 50 are disposed on the two side frames of the display area 11, in the embodiment of the present application, the plurality of first terminals 1211 are disposed in the first terminal area 121, the plurality of second terminals 1221 are disposed in the second terminal area 122, the plurality of first-type signal lines 111 are disposed in the display area 11, the first ends of the first-type signal lines 111 are electrically connected to the first terminals 1211, and the second ends of the first-type signal lines 111 are electrically connected to the second terminals 1221, wherein the first-type signal lines 111 are used for outputting the common electrode signal on the color film substrate 21 side in the display panel 100, and each of the first-type signal traces 111 is disposed between two adjacent sub-pixels 116 arranged along the first direction D1, so as to dispose the common electrode signal traces on the two sides of the display area 11 in the display area 11, the frame widths of the two sides of the display panel 100 are reduced, and the real extremely narrow frame display of the periphery of the display device 50 is realized under the condition that the display effect of the display device 50 is not influenced.
Fig. 4 is a schematic distribution diagram of a portion of signal traces in the display panel 100 according to the second embodiment of the present application. The second embodiment of the present application is different from the first embodiment of the present application only in that each of the first-type signal traces 111 is disposed on the corresponding sub-pixel 116; the first signal trace 111 may be made of a transparent metal material (such as a transparent ito material) to avoid affecting the display effect of the display panel 100.
It is understood that each of the second signal traces 119 may also be disposed on the corresponding sub-pixel 116, and the material of the second signal trace 119 may be a transparent metal material (such as a transparent ito material), so as to avoid affecting the display effect of the display panel 100.
In view of the technical problem in the prior art that the frame width of the display device 50 is increased due to the fact that a portion of the common electrode signal traces of the display device 50 are disposed on the two side frames of the display area 11, in the embodiment of the present application, the plurality of first terminals 1211 are disposed in the first terminal area 121, the plurality of second terminals 1221 are disposed in the second terminal area 122, the plurality of first-type signal lines 111 are disposed in the display area 11, the first ends of the first-type signal lines 111 are electrically connected to the first terminals 1211, and the second ends of the first-type signal lines 111 are electrically connected to the second terminals 1221, wherein the first-type signal lines 111 are used for outputting the common electrode signals on the color film substrate 21 side of the display panel 100, and each of the first-type signal traces 111 is disposed on the sub-pixel 116 corresponding thereto, so as to reduce the distribution area of the first-type signal lines 111 in the display area 11, thereby disposing the common electrode signals on the two sides of the trace areas 11 in the display area 11, while the influence on the display effect of the display device 50 is further reduced, the frame widths on the two sides of the display panel 100 are reduced, and the real extremely narrow frame display of the periphery of the display device 50 is realized.
As shown in fig. 5, a trace diagram of the display device 50 located on the color filter substrate 21 side according to the embodiment of the present disclosure is shown. The display device 50 includes a plurality of flip-chip films 51 and the display panel 100 as described above, the flip-chip films 51 are disposed on one side of the display panel 100 close to the first terminal area 121, a plurality of second signal traces 119 are disposed between two adjacent flip-chip films 51, a first end of the second signal trace 119 is electrically connected to the flip-chip film 51, and a second end of the second signal trace 119 is electrically connected to the first common electrode layer 113 through the electrical connector array substrate 10 side of the electrical connector 23.
The chip on film 51 is internally provided with a gate driving circuit, and the gate driving circuit includes cascaded multi-stage gate driving units and scanning lines connected with the multi-stage gate driving units.
Specifically, the scan lines connected to the multiple stages of gate driving units are the second scan lines 118, and the common electrode signals output by the second signal traces 119 and on the side of the array substrate 10 are provided by the chip on film 51.
In this embodiment of the application, a first end of the first-type signal line 111 is electrically connected to the second-type signal trace 119 through the transparent conductive layer 115, and a second end of the first-type signal line 111 is electrically connected to the second common electrode layer 22 through the electrical connector 23 on the color filter substrate 21 side.
Each first-type signal trace 111 is connected in parallel with another first-type signal trace 111. The first signal traces 111 are connected in parallel, so that impedance (loss of a resistor and a capacitor to a transmission signal) between two adjacent first signal traces 111 can be reduced, and thus the delay degree of a common electrode signal transmitted from the array substrate 10 to the color film substrate 21 side is reduced.
In the embodiment of the present application, each first-type signal line 111 is disposed between two adjacent flip-chip films 51, so that the impedance generated between the signal line connected to the flip-chip film 51 and the first-type signal line 111 can be reduced.
The embodiment of the present application is not specifically limited to the application of the display device 50, and the display device may be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a wearable display device (e.g., a smart band, a smart watch, etc.), a mobile phone, a virtual reality device, an augmented reality device, a vehicle-mounted display, an advertisement light box, etc.
The embodiment of the application provides a display panel 100 and a display device 50, the display panel 100 includes a display area 11, and a first terminal area 121 and a second terminal area 122 disposed at two sides of the display area 11, a plurality of first terminals 1211 disposed in the first terminal area 121, a plurality of second terminals 1221 disposed in the second terminal area 122, a plurality of first-type signal lines 111 disposed in the display area 11, a first end of the first-type signal line 111 electrically connected to the first terminal 1211, and a second end of the first-type signal line 111 electrically connected to the second terminal 1221; the first-type signal lines 111 are used for outputting common electrode signals on the side of the color film substrate 21 in the display panel 100, so that the common electrode signals on the two sides of the display area 11 are routed in the display area 11, the frame width on the two sides of the display panel 100 is reduced, meanwhile, the delay degree of the common electrode signals transmitted from the array substrate 10 side to the color film substrate 21 side is reduced, and the real extremely narrow frame display of the periphery of the display device 50 is realized without affecting the display effect of the display device 50.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel 100 and the display device 50 provided in the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel is characterized by comprising a display area, a first terminal area and a second terminal area, wherein the first terminal area and the second terminal area are arranged on two sides of the display area; wherein the display panel includes:
a plurality of first terminals disposed within the first terminal region;
a plurality of second terminals disposed within the second terminal area; and
and the first ends of the first signal lines are electrically connected with the first terminals, and the second ends of the first signal lines are electrically connected with the second terminals.
2. The display panel according to claim 1, wherein each of the first type signal traces is connected in parallel with another of the first type signal traces.
3. The display panel according to claim 1, wherein the display panel further comprises an array substrate, the array substrate is further provided with a first common electrode layer and a transparent conductive layer on the first common electrode layer, the first terminal is disposed on the transparent conductive layer, and the first end of the first signal line is electrically connected to the first common electrode layer through the transparent conductive layer.
4. The display panel of claim 1, wherein the display panel further comprises a plurality of sub-pixels arranged in an array, and each of the first signal traces is disposed between two adjacent sub-pixels arranged along the first direction.
5. The display panel according to claim 4, wherein the display panel further comprises a scan line and a power supply cathode trace, the scan line comprises a first sub-scan line extending along the first direction and a second sub-scan line extending along a second direction, and each first sub-scan line is electrically connected to its corresponding second sub-scan line through an input point;
the second sub-scanning line and the power source cathode wiring respectively extend from the first terminal area to the second terminal area and are arranged in parallel with the first type of signal wiring.
6. The display panel according to claim 4, wherein the display panel further comprises a plurality of second-type signal traces, the second-type signal traces are disposed in parallel with the first-type signal traces, and each of the second-type signal traces extends from the first terminal area to the second terminal area;
each second-type signal routing is arranged between two adjacent sub-pixels arranged along the first direction, and each second-type signal routing is used for transmitting a first common electrode signal on the side of the array substrate.
7. The display panel according to claim 6, wherein the number of the first type signal traces and the second type signal traces in the display area are equal.
8. The display panel according to claim 6, wherein at least two subpixels with different colors are spaced between each second signal trace and the adjacent first signal trace.
9. The display panel according to any one of claims 3 to 8, wherein the display panel further comprises a color film substrate, and an electrical connector disposed between the array substrate and the color film substrate;
the color film substrate comprises a second common electrode layer, and the second common electrode layer is electrically connected with the second terminal through the electric connecting piece.
10. A display device, comprising a plurality of flip-chips and the display panel according to any one of claims 1 to 9, wherein the flip-chips are disposed on the display panel at a side close to the first terminal area;
the chip on film is internally provided with a grid driving circuit, and the grid driving circuit comprises cascaded multi-stage grid driving units and scanning lines connected with the multi-stage grid driving units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110732330.XA CN113448129A (en) | 2021-06-30 | 2021-06-30 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110732330.XA CN113448129A (en) | 2021-06-30 | 2021-06-30 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113448129A true CN113448129A (en) | 2021-09-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114677927A (en) * | 2022-03-16 | 2022-06-28 | Tcl华星光电技术有限公司 | Display panel |
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| CN114677927A (en) * | 2022-03-16 | 2022-06-28 | Tcl华星光电技术有限公司 | Display panel |
| CN114677927B (en) * | 2022-03-16 | 2023-08-22 | Tcl华星光电技术有限公司 | display panel |
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