CN113447788A - Silicon carbide MOSFET transient thermal test method and device - Google Patents

Silicon carbide MOSFET transient thermal test method and device Download PDF

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Publication number
CN113447788A
CN113447788A CN202110719753.8A CN202110719753A CN113447788A CN 113447788 A CN113447788 A CN 113447788A CN 202110719753 A CN202110719753 A CN 202110719753A CN 113447788 A CN113447788 A CN 113447788A
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test
silicon carbide
gate
carbide mosfet
tested
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杨连乔
简毛亮
张建华
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University of Shanghai for Science and Technology
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University of Shanghai for Science and Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G01R31/2628—Circuits therefor for testing field effect transistors, i.e. FET's for measuring thermal properties thereof

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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The invention discloses a transient thermal test method and a transient thermal test device for a silicon carbide MOSFET (metal oxide semiconductor field effect transistor). A test parameter is set, a positive voltage is applied to a grid electrode of the silicon carbide MOSFET, after a gate and a delay, a heating current is applied to the silicon carbide MOSFET for heating, after heating for a certain time, heating is completed, a test current is applied, and simultaneously, after a gate and a delay, a negative voltage is applied to the grid electrode of the silicon carbide MOSFET to start testing the silicon carbide MOSFET. And when the heating is finished and the test delay is passed, starting to collect a thermal test signal to obtain the potential difference between the drain electrode and the source electrode of the silicon carbide MOSFET. The positive and negative voltages are provided by a gate voltage source, the heating current is provided by a heating current source and controlled by a first switch, and the test current is provided by a test current source and controlled by a second switch. The method solves the problem that the voltage signal to be tested has oscillation phenomenon in the transient thermal test process, and improves the accuracy of the transient thermal test of the silicon carbide MOSFET.

Description

Silicon carbide MOSFET transient thermal test method and device
Technical Field
The invention relates to the technical field of additive manufacturing, in particular to a transient thermal test method and device for a silicon carbide MOSFET.
Background
With the increasing demand for high-speed switching devices with high voltage capacity, semiconductors represented by silicon carbide (SiC) materials are being developed. Silicon carbide MOSFETs gradually replace power devices made of Si due to their advantages of high critical breakdown field strength, high switching frequency, high temperature resistance, etc. However, as silicon carbide MOSFETs are widely used, the problems caused by high-speed switching are very significant, wherein the important problems are the lifetime and reliability of the devices, and the excessive junction temperature is an important factor that limits the lifetime and reliability of the silicon carbide MOSFETs. Therefore, in order to effectively carry out heat dissipation design and performance detection on the semiconductor device, the temperature change of the active region of the device is accurately measured, and the thermal resistance composition distribution of the active region is analyzed, so that the method is very important for commercial production of the silicon carbide MOSFET.
Since the semiconductor device has many electrical characteristics having a good linear relationship with temperature, such as a PN junction forward conduction voltage, a threshold voltage, and the like, junction temperature and thermal resistance are obtained by measuring the electrical characteristics. However, the device optimizer wants to extract the thermal resistance of the chip layer to optimize the device design, and the packaging tester wants to extract the thermal resistance of the solder layer to detect the soldering effect, so that it is not enough to obtain the thermal resistance and junction temperature. The transient thermal test method is widely applied to extracting the thermal resistance and the thermal capacity of the device structure due to the specific structure function.
Since conventional silicon-based MOSFET transient thermal testing is not suitable for silicon carbide MOSFETs. For a silicon-based power MOSFET device, a structural function and a thermal resistance can be obtained by adopting modes such as threshold voltage, diode drop or on-state resistance. However, because a large number of interface traps exist at the SiC/SiO2 interface of the silicon carbide MOSFET, under a forward bias, the interface traps trap carriers in a channel to cause a forward drift of the threshold voltage of the gate, and the larger the gate voltage is, the larger the drift degree is. The drift of the threshold voltage often affects the testing of the junction temperature of the device, and the uncertainty is added to the transient thermal testing of the device. In addition, in some configurations, the motion of trapped charge can cause heating currents in the transient thermal test and electrical interference within a few seconds after switching of the test current, and these effects can cause false transient thermal test signals in the transient thermal test within a time frame in which most information about the device structure can be obtained.
The threshold voltage mode and the diode mode are common test modes, namely, the threshold voltage mode and the diode mode, need to acquire the voltage of a grid electrode to the ground during testing, and are not suitable for being used as transient thermal test modes of the silicon carbide MOSFET device. In addition, the on-resistance mode, although less sensitive to oscillations, still requires the selection of an appropriate compensation.
Disclosure of Invention
The invention provides a transient thermal test method and a device for a silicon carbide MOSFET,
in order to achieve the purpose, the invention provides the following scheme:
a method of transient thermal testing of a silicon carbide MOSFET, the method comprising:
setting test parameters including a positive voltage VGate+Negative voltage VGate-Heating current IHeatHeating time THeatTest current ISenseTest time TSenseGate delay TdAnd a test delay Tmd；
Applying the positive voltage V on the gate of a silicon carbide MOSFETGate+Opening a channel of the silicon carbide MOSFET;
applying the positive voltage V to the gateGate+TdApplying the heating current I on the channel of the silicon carbide MOSFET after a period of timeHeatTo heat the silicon carbide MOSFET;
when the heating time reaches the heating time THeatWhile applying the heating current IHeatSwitching to the test current ISense；
When heating is completed TdAfter a period of time, applying the negative voltage V on the gate of the silicon carbide MOSFETGate-Closing the channel of the silicon carbide MOSFET;
applying the test current ISenseApplying to the channel of the silicon carbide MOSFET to enable testing of the silicon carbide MOSFET;
applying the negative voltage V to the gateGate-TmdAfter a period of time, starting to collect a thermal test signal; the thermal test signal is a potential difference between the drain and the source of the silicon carbide MOSFET; wherein, Tmd≥Td；
When the time for collecting the test signal reaches TSenseAnd then, finishing the collection.
Preferably, the doorExtreme delay TdThe value range of (A) is 1-50 mus.
Preferably, the test delay TmdThe value range of (A) is 1-500 mus.
Preferably, the positive voltage VGate+Is +15V, the negative voltage VGate-is-7V.
Preferably, the silicon carbide MOSFET is an N-channel silicon carbide MOSFET.
Preferably, a transient response curve is constructed from the collected thermal test signals.
A silicon carbide MOSFET transient thermal test apparatus suitable for use in the above method, the apparatus comprising:
the device comprises a grid voltage source, a heating current source, a test current source, a first switch, a second switch and a device to be tested;
the positive electrode of the grid voltage source is connected with the first end of the device to be tested; the negative electrode of the grid voltage source is connected with the third end of the device to be tested;
the anode of the heating current source is connected with the second end of the device to be tested; the negative electrode of the heating current source is connected with the third end of the device to be tested;
the anode of the test current source is connected with the third end of the device to be tested; the negative electrode of the test current source is connected with the second end of the device to be tested;
the first switch is arranged on a loop of the heating current source and the device to be tested;
the second switch is arranged on a loop of the test current source and the device to be tested;
the gate voltage source is used for providing a positive voltage VGate+And a negative voltage VGate-；
The heating current source is used for applying a heating current I to the device to be testedHeat；
The test current source is used for applying a test current I to the device to be testedSense；
The first switch is used for controlling the heating current source to work; the second switch is used for controlling the test current source to work;
the device to be tested is a silicon carbide MOSFET; the first end of the device to be tested is a grid electrode, the second end of the device to be tested is a drain electrode, and the third end of the device to be tested is a source electrode.
Preferably, one end of each of the gate voltage source, the heating current source, the test current source and the test device is grounded.
Preferably, the first switch is installed between the anode of the heating current source and the second end of the device to be tested.
Preferably, the second switch is installed between a negative electrode of the test current source and the second end of the device to be tested.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a transient thermal test method and a transient thermal test device for a silicon carbide MOSFET (metal oxide semiconductor field effect transistor). the transient thermal test is carried out on the silicon carbide MOSFET through adding a gate, delaying and testing delaying, so that a voltage signal to be tested is accurately measured, and the silicon carbide MOSFET is prevented from being subjected to SiC/SiO2The influence of threshold voltage drift caused by a large number of interface traps exists on the interface, the problem that a voltage signal to be tested oscillates in the transient thermal test process is solved, and the accuracy of the transient thermal test of the silicon carbide MOSFET is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a flow chart of a method for transient thermal testing of silicon carbide MOSFETs;
FIG. 2 is a diagram of a silicon carbide MOSFET transient thermal test apparatus;
FIG. 3 is a timing diagram illustrating control of transient thermal testing of silicon carbide MOSFETs;
FIG. 4 is a diagram of a silicon carbide MOSFET structure;
FIG. 5 is a schematic of step power and forward voltage drop;
FIG. 6 is a graph of a differential structure function;
FIG. 7 is a graph of an integral structure function;
FIG. 8 is a graph of a silicon carbide MOSFET transient response;
FIG. 9 is a graph of data collected after gate delay and delay measurements.
Description of the symbols:
1-grid voltage source, 2-heating current source, 3-testing current source, 4-device to be tested, 4.1-first terminal, 4.2-second terminal, 4.3-third terminal, 5-first switch, 6-second switch, 7-channel, 8-grid, 9-source and 10-drain.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The purpose of the invention is
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
As shown in fig. 1 and 3, the present embodiment discloses a method for transient thermal testing of a silicon carbide MOSFET, the method comprising:
s1: setting test parameters, including positive voltage VGate+Negative voltage VGate-Heating current IHeatHeating time THeatTest current ISenseTest time TSenseGate delay TdAnd a test delay Tmd。
S2: applying a positive voltage V to the gate of a silicon carbide MOSFETGate+Of silicon carbide MOSFETThe channel is opened.
S3: applying the positive voltage V to the gateGate+TdAfter a period of time, a heating current I is applied to the channel of the silicon carbide MOSFETHeatSo as to heat the silicon carbide MOSFET.
S4: when the heating time reaches the heating time THeatWhile heating current IHeatSwitching to a test current ISense。
S5: when heating is completed TdAfter a period of time, applying a negative voltage V to the gate of the silicon carbide MOSFETGate-The channel of the silicon carbide MOSFET is turned off.
S6: will test the current ISenseIs applied to the channel of a silicon carbide MOSFET to allow testing of the silicon carbide MOSFET.
S7: applying the negative voltage V to the gateGate-TmdAfter a period of time, starting to collect a thermal test signal; the thermal test signal is the potential difference between the drain and source of the silicon carbide MOSFET.
S8: when the time for collecting the test signal reaches TSenseAnd then, finishing the collection.
In particular, the gate delay TdIs in the range of 1-50 mus, the test delay TmdHas a value in the range of 1-500 mu s, Tmd≥Td。
Specifically, the positive voltage VGate + is +15V and the negative voltage VGate-is-7V.
Specifically, the silicon carbide MOSFET is an N-channel silicon carbide MOSFET.
Specifically, a transient response curve is constructed according to the heat collection test signal.
Specifically, when the heating phase is finished, the test phase is switched to. The key point is to switch to the test stage, turn off the heating current and turn on the test current. Wherein the heating current is switched on and off by the first switch S1, and the test current is controlled by the second switch S2. When the grid voltage does not reach the threshold voltage, the drain electrode D and the source electrode S are disconnected because no channel is formed, and the heating current does not flow through the device under test although the switch is closedTherefore, it is necessary to apply a gate voltage greater than the threshold voltage to open the channel of the device, i.e., to apply a voltage V of 15VgateSo that V isgateIn cooperation with S1, to apply a heating current to the channel of the device. When the heating time reaches the set value, S1 is opened, S2 is closed, and VgateAnd switching to-7V after passing through a gate and delay, closing a channel, enabling test current to flow in from a source electrode, pass through a body diode and then flow out from a grid electrode, and testing the silicon carbide MOSFET.
Specifically, the transient thermal test is a measurement method which has good repeatability, does not damage the internal structure of the device, and can obtain a structural function. And measuring the total thermal resistance and the junction temperature of the semiconductor device and the thermal resistance of each layer of the internal structure of the device through transient thermal test. Junction temperature generally refers to the temperature of a PN junction of a semiconductor device, in kelvin or celsius degrees; the thermal resistance is the ability of obstructing the heat flow, the larger the thermal resistance is, the larger the ability of obstructing the heat flow is, the heat flow is accumulated, thereby leading to the temperature rise; the smaller the thermal resistance, the smaller the blocking capability, and the heat flow will flow easily without causing temperature rise. Thermal resistance is defined as how many degrees celsius or kelvin the temperature rises at a unit of power. The thermal resistance is a comprehensive parameter reflecting the capability of preventing heat transfer when the semiconductor device works along the ratio of the temperature difference on the thermal flow channel to the heat dissipation power, and the unit is K/W or DEG C/W, and the physical meaning is that when the heat dissipation power of the device to be tested is equal to 1W, the junction temperature is increased by degrees.
The transient thermal test specifically comprises a first step of calibrating a temperature coefficient K and a second step of obtaining a transient response curve.
Specifically, other conditions are not changed, the temperature is changed, certain parameters of the device are changed along with the change of the temperature, a proportional relation between the two is fitted, and the coefficient of the proportional relation is the temperature coefficient K. The temperature sensitive parameter is the forward voltage drop of the PN junction, that is, the ambient temperature value is changed under the condition that other conditions are not changed, and the default device junction temperature is the same as the ambient temperature value after the ambient temperature value is stable. And then measuring the forward voltage drop of the PN junction of the semiconductor device at different environmental temperature values, wherein the forward voltage drop is different at different temperatures, and the forward voltage drop is reduced along with the temperature rise. Therefore, when the forward voltage drop at any time is measured, the junction temperature corresponding to the forward voltage drop can be obtained.
Specifically, the transient response curve is a curve of the junction temperature of the device changing along with time, a forward voltage drop is measured, and then the junction temperature of the device is obtained through a K coefficient, so that the transient response curve is constructed.
In particular, the transient response curve reflects the thermal resistance of the various layers of the internal structure, requiring a step power to be applied to the device. The junction temperature inside the device varies with time after the step power is applied to the device.
The step power and forward voltage drop are shown schematically in fig. 5, with time on the abscissa and current and voltage on the ordinate. I isSenseIs referred to as the test current, IHeatIs the heating current, and is divided by the lower half of fig. 5 into the change in forward voltage drop at different stages.
At the arrival of t0After the moment, using heating current IHeatIn place of ISenseApplying the mixture to two ends of a device to be tested, and heating for a certain time THeatUntil the device heat conduction reaches a steady state at t1At the moment, ISenseRapid substitution of IHeatThe voltage is added to two ends of the PN to be measured, the voltage at two ends of the PN junction is collected, the collection can be stopped until the interior of the device is stable, the specific collection time can also be specified, but the specific collection time cannot be too short or too long, the temperature of the device is not stable due to too short time, the measured data are too much due to too long time, and the processing difficulty is increased. Therefore, a transient response curve is obtained, and the transient response curve is also obtained after the change of the PN junction forward voltage drop along with time is processed by the K coefficient.
Specifically, smooth fitting, derivation, deconvolution, network Morse signal conversion are performed on the transient response curve to obtain a structural function curve, and each part of the structural function path represents a physical structure encountered by heat. The locations on the structure function near the Y-axis represent structures on the actual heat flow conduction path near the active region of the device, while the locations further away from the Y-axis represent heat flow to structures on the path further away from the active region of the device. And (3) calculating according to a structural function curve to obtain a differential structure function graph 6 and an integral structure function graph 7, wherein in the differential structure, the inflection point of a peak and a trough is the boundary of the two structures, the peak represents that the region has high thermal conductivity, namely, the structure with large thermal capacitance and small thermal resistance, and the trough represents that the region has low thermal conductivity, namely, the structure with small thermal capacitance and large thermal resistance, so that each layer structure in the device can be conveniently identified. The flat area on the integral structure function represents a structure with large internal thermal resistance and small heat capacity, such as a solid crystal layer; the steep regions represent structures with low internal thermal resistance and high thermal capacity of the device, such as chips, metal pedestals and aluminum substrates. In addition, a region with a small slope indicates a region with a low thermal conductivity or a small cross-sectional area, and a region with a large slope indicates the opposite.
Specifically, the silicon carbide MOSFET transient response curve shown in FIG. 8, at T0Before the moment, the electric interference at the moment of switching the heating current and the test current is eliminated through data fitting and back-stepping, and the electric interference is eliminated at T0And T1The data in between generates oscillation, which is that the interface trap captures carriers in the channel to cause the threshold voltage of the gate to drift forward, so that correct thermal test data cannot be obtained through fitting and reverse estimation of the data.
Specifically, the data plot collected after the gate delay and delay measurements, as shown in FIG. 9, is for the acquisition T1The data after the segment was fit and extrapolated.
Specifically, the first transient thermal test measurement directly dry-contacts the device to the heat sink.
Second transient thermal test measurement: a separate layer is placed between the device and the heat sink. Since the change of the two heat dissipation paths only occurs outside the device package (Case), the boundary of the two measurements on the structure function represents the Case of the device.
Specifically, the characteristic that the thermal resistance of a solid crystal layer in the device can be measured in a nondestructive mode through a structural function is utilized, and the method can be used for realizing packaging materials, process optimization devices and reliability screening in practical application.
Example 2
As shown in fig. 2 and 4, the present embodiment discloses a transient thermal testing apparatus for a silicon carbide MOSFET, the apparatus including:
a grid voltage source 1, a heating current source 2, a test current source 3, a first switch 5, a second switch 6 and a device to be tested 4.
The positive electrode of the grid voltage source 1 is connected with a first end 4.1 of the device to be tested 4; the negative pole of the grid voltage source 1 is connected with the third end 4.3 of the device to be tested 4.
The anode of the heating current source 2 is connected with the second end 4.2 of the device to be tested 4; the negative pole of the heating current source 2 is connected with the third end 4.3 of the device to be tested 4.
The anode of the test current source 3 is connected with the third end 4.3 of the device to be tested 4; the negative pole of the test current source 3 is connected to the second end 4.2 of the device under test 4.
The first switch 5 is installed on the loop of the heating current source 2 and the device to be tested 4.
The second switch 6 is installed on the loop of the test current source 3 and the device under test 4.
The gate voltage source 1 is used for providing a positive voltage VGate+And a negative voltage VGate-。
The heating current source 2 is used for applying a heating current I to the device to be tested 4Heat。
The test current source 3 is used for applying a test current I to the device to be tested 4Sense。
The first switch 5 is used for controlling the heating current source 2 to work; the second switch 6 is used for controlling the test current source 3 to work.
The device to be tested 4 is a silicon carbide MOSFET; the first end 4.1 of the device to be tested 4 is a grid 8, the second end 4.2 is a drain 10, and the third end 4.3 is a source 9.
Specifically, one end of each of the gate voltage source 1, the heating current source 2, the test current source 3, and the test device 4 is grounded.
In particular, the first switch 5 is mounted between the positive pole of the heating current source 2 and the second end 4.2 of the device under test 4.
In particular, the second switch 6 is mounted between the negative pole of the test current source 3 and the second end 4.2 of the device under test 4.
The embodiment discloses a transient thermal test method and a transient thermal test device for a silicon carbide MOSFET (metal oxide semiconductor field effect transistor). the transient thermal test is carried out on the silicon carbide MOSFET through an addition gate, delay and test delay, so that a voltage signal to be tested is accurately measured, and the silicon carbide MOSFET is prevented from being subjected to SiC/SiO2The influence of threshold voltage drift caused by a large number of interface traps exists on the interface, the problem that a voltage signal to be tested oscillates in the transient thermal test process is solved, and the accuracy of the transient thermal test of the silicon carbide MOSFET is improved. The electric interference caused by the threshold voltage drift within a range of several seconds after the heating current and the test current are switched can be effectively eliminated through the gate delay, so that the false thermal test signal caused by the threshold voltage drift is reduced.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (10)

1. A method of transient thermal testing of a silicon carbide MOSFET, the method comprising:
setting test parameters including a positive voltage VGate+Negative voltage VGate-Heating current IHeatHeating time THeatTest current ISenseTest time TSenseGate delay TdAnd a test delay Tmd；
Applying the positive voltage V on the gate of a silicon carbide MOSFETGate+Opening a channel of the silicon carbide MOSFET;
applying the positive voltage V to the gateGate+TdAfter a period of time, in the carbonApplying the heating current I to the channel of the silicon MOSFETHeatTo heat the silicon carbide MOSFET;
when the heating time reaches the heating time THeatWhile applying the heating current IHeatSwitching to the test current ISense；
When heating is completed TdAfter a period of time, applying the negative voltage V on the gate of the silicon carbide MOSFETGate-Closing the channel of the silicon carbide MOSFET;
applying the test current ISenseApplying to the channel of the silicon carbide MOSFET to enable testing of the silicon carbide MOSFET;
applying the negative voltage V to the gateGate-TmdAfter a period of time, starting to collect a thermal test signal; the thermal test signal is a potential difference between the drain and the source of the silicon carbide MOSFET; wherein, Tmd≥Td；
When the time for collecting the test signal reaches TSenseAnd then, finishing the collection.
2. The method of claim 1 wherein the gate delay T is determined by a transient thermal test of the silicon carbide MOSFETdThe value range of (A) is 1-50 mus.
3. The silicon carbide MOSFET transient thermal test method of claim 1, wherein the test delay T ismdThe value range of (A) is 1-500 mus.
4. The silicon carbide MOSFET transient thermal test method of claim 1, wherein the positive voltage V is positiveGate+Is +15V, the negative voltage VGate-is-7V.
5. The method of claim 1, wherein the silicon carbide MOSFET is an N-channel silicon carbide MOSFET.
6. The method of claim 1, wherein a transient response curve is constructed from the collected thermal test signals.
7. A silicon carbide MOSFET transient thermal test apparatus adapted for use in the method of any of claims 1-6, the apparatus comprising: the device comprises a grid voltage source, a heating current source, a test current source, a first switch, a second switch and a device to be tested;
the positive electrode of the grid voltage source is connected with the first end of the device to be tested; the negative electrode of the grid voltage source is connected with the third end of the device to be tested;
the anode of the heating current source is connected with the second end of the device to be tested; the negative electrode of the heating current source is connected with the third end of the device to be tested;
the anode of the test current source is connected with the third end of the device to be tested; the negative electrode of the test current source is connected with the second end of the device to be tested;
the first switch is arranged on a loop of the heating current source and the device to be tested;
the second switch is arranged on a loop of the test current source and the device to be tested;
the gate voltage source is used for providing a positive voltage VGate+And a negative voltage VGate-；
The heating current source is used for applying a heating current I to the device to be testedHeat；
The test current source is used for applying a test current I to the device to be testedSense；
The first switch is used for controlling the heating current source to work; the second switch is used for controlling the test current source to work;
the device to be tested is a silicon carbide MOSFET; the first end of the device to be tested is a grid electrode, the second end of the device to be tested is a drain electrode, and the third end of the device to be tested is a source electrode.
8. The silicon carbide MOSFET transient thermal test apparatus of claim 7, wherein one end of the gate voltage source, the heating current source, the test current source, and the test apparatus are all grounded.
9. The silicon carbide MOSFET transient thermal testing device of claim 7, wherein the first switch is mounted between the positive pole of the heating current source and the second end of the device under test.
10. The silicon carbide MOSFET transient thermal testing device of claim 7, wherein the second switch is mounted between a negative terminal of the test current source and the second end of the device under test.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114217198A (en) * 2021-12-07 2022-03-22 北京工业大学 Short-pulse heavy-current-based SiC MOSFET module thermal resistance measurement method
CN114325286A (en) * 2021-12-31 2022-04-12 浙江大学杭州国际科创中心 SiC MOSFET power cycle test circuit and control method thereof
CN116500400A (en) * 2022-09-08 2023-07-28 南京信息工程大学 Online in-situ characterization system and method for failure state of solder layer of silicon carbide power device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178817A1 (en) * 2003-03-13 2004-09-16 Advanced Micro Devices, Inc. Method for independent measurement of mosfet source and drain resistances
CN212586493U (en) * 2020-03-13 2021-02-23 陕西三海测试技术开发有限责任公司 Transient thermal resistance test circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178817A1 (en) * 2003-03-13 2004-09-16 Advanced Micro Devices, Inc. Method for independent measurement of mosfet source and drain resistances
CN212586493U (en) * 2020-03-13 2021-02-23 陕西三海测试技术开发有限责任公司 Transient thermal resistance test circuit

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
YUTA TANIMOTO等: "Power-Loss Prediction of High-Voltage SiC-MOSFET Circuits with Compact Model Including Carrier-Trap Influences", 《IEEE TRANSACTIONS ON POWER ELECTRONICS》 *
周郁明等: "SiC/SiO_2界面态电荷对SiC MOSFET短路特性影响的研究", 《电子科技大学学报》 *
孙铣: "功率器件的瞬态热阻测试", 《中国集成电路》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114217198A (en) * 2021-12-07 2022-03-22 北京工业大学 Short-pulse heavy-current-based SiC MOSFET module thermal resistance measurement method
CN114217198B (en) * 2021-12-07 2023-10-10 北京工业大学 Short pulse-based high-current SiC MOSFET module thermal resistance measurement method
CN114325286A (en) * 2021-12-31 2022-04-12 浙江大学杭州国际科创中心 SiC MOSFET power cycle test circuit and control method thereof
CN116500400A (en) * 2022-09-08 2023-07-28 南京信息工程大学 Online in-situ characterization system and method for failure state of solder layer of silicon carbide power device
CN116500400B (en) * 2022-09-08 2023-12-01 南京信息工程大学 Online in-situ characterization system and method for failure state of solder layer of silicon carbide power device

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