CN113434457A - High output frame rate data processing method, device, equipment, system and storage medium - Google Patents
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Abstract
The embodiment of the invention discloses a method, a device, equipment, a system and a storage medium for processing high-output frame rate data, wherein the method comprises the following steps: performing transformation processing on the original collected data through a first processing unit to obtain data to be calculated; calculating the data to be calculated by the first processing unit based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated; and transmitting the preset target data to a second processing unit through the first processing unit, wherein the second processing unit is used for outputting the preset target data. The scheme solves the problem of low data processing efficiency in the prior art, and realizes the remarkable improvement of data processing capacity.
Description
Technical Field
The embodiment of the application relates to the field of data processing, in particular to a method, a device, equipment, a system and a storage medium for processing high-output frame rate data.
Background
With the improvement of the processing capacity of the hardware equipment, the hardware equipment realizes the rapid processing of data so as to complete corresponding software functions. Existing mainstream processing platforms typically employ a hardware architecture of multiple processing cores. Due to the application of the multi-processing core architecture, the corresponding software platform has high computational power and flexibility. However, the multi-processing core architecture has obvious disadvantages while improving the data operation capability, such as complex design size, need of linkage of each processing core, higher cost, high development difficulty and longer development period.
In order to solve the above problems in the prior art, a scheme for implementing chip integrated processing is designed, however, in the chip integrated processing scheme, data transmission between chip subsystems is mostly implemented in a bus control manner, a data output rate of the scheme is limited by bus transmission capability, processing capability of data with a high output frame rate is significantly affected, data processing cannot be efficiently implemented, and improvement is needed.
Disclosure of Invention
Embodiments of the present invention provide a method, an apparatus, a device, a system, and a storage medium for processing data with a high output frame rate, which solve the problem of low data processing efficiency in the prior art, and achieve significant improvement of data processing capability.
In a first aspect, an embodiment of the present invention provides a method for processing high-output frame rate data, where the method includes:
performing transformation processing on the original collected data through a first processing unit to obtain data to be calculated;
calculating the data to be calculated by the first processing unit based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated;
and transmitting the preset target data to a second processing unit through the first processing unit, wherein the second processing unit is used for outputting the preset target data.
In a second aspect, an embodiment of the present invention further provides an apparatus for processing high-output frame rate data, where the apparatus includes:
the first processing unit is used for performing transformation processing on the original collected data to obtain data to be calculated, calculating the data to be calculated based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated, and transmitting the preset target data to the second processing unit;
and the second processing unit is used for outputting the preset target data.
In a third aspect, an embodiment of the present invention further provides a high-output frame rate data processing system, where the system includes a front-end processing module, a data processing module, and a data output module, the data processing module is respectively connected to the front-end processing module and the data output module, and the data processing module includes a first processing unit and a second processing unit;
the front-end processing module is used for acquiring original acquisition data;
the first processing unit is used for performing transformation processing on the original collected data to obtain data to be calculated, calculating the data to be calculated based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated, and transmitting the preset target data to the second processing unit;
the second processing unit is used for outputting the preset target data to the data output module;
and the data output module is used for outputting the calculation result of the data processing module.
In a fourth aspect, an embodiment of the present invention further provides a high-output frame rate data processing apparatus, where the apparatus includes:
two or more processors; and a storage device, configured to store two or more programs, where when the two or more programs are executed by the two or more processors, the two or more processors implement the high-output frame rate data processing method according to the embodiment of the present invention.
In a fifth aspect, an embodiment of the present invention further provides a radar apparatus, including: the front-end processing module is used for acquiring original acquisition data; the data processing module is used for processing the original collected data by the high-output frame rate data processing method provided by the embodiment of the invention.
In a sixth aspect, an embodiment of the present invention further provides a movable platform, including the radar apparatus described in the implementation of the present invention.
In a seventh aspect, an embodiment of the present invention further provides a storage medium storing computer-executable instructions, which are used to execute the high-output frame rate data processing method according to the embodiment of the present invention when executed by a computer processor.
In the embodiment of the invention, the conversion processing is performed on the original acquired data through the first processing unit to obtain the data to be calculated, the data to be calculated is calculated based on the pre-imported processing algorithm to obtain the preset target data, the data volume of the preset target data is smaller than that of the data to be calculated, and the preset target data is transmitted to the second processing unit through the first processing unit and is used for the second processing unit to output the preset target data.
Drawings
Fig. 1 is a flowchart of a high frame rate output data processing method according to an embodiment of the present invention;
FIG. 2 is a flowchart of another high frame rate output data processing method according to an embodiment of the present invention;
FIG. 3 is a flowchart of another high frame rate output data processing method according to an embodiment of the present invention;
fig. 3a is a schematic diagram of original acquired data after one-dimensional transformation processing according to an embodiment of the present invention;
fig. 3b is a schematic diagram of deleting non-target information from a one-dimensional transform processing result according to an embodiment of the present invention;
fig. 3c is a schematic diagram illustrating a one-dimensional transform processing result after deleting non-target information according to an embodiment of the present invention;
fig. 3d is a schematic diagram illustrating that preset target data is obtained by calculating data to be calculated according to an embodiment of the present invention;
FIG. 4 is a flowchart of another high frame rate output data processing method according to an embodiment of the present invention;
FIG. 5 is a block diagram of a high frame rate output data processing apparatus according to an embodiment of the present invention;
FIG. 6 is a block diagram of a high frame rate output data processing system according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a high frame rate output data processing apparatus according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a radar apparatus according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad invention. It should be further noted that, for convenience of description, only some structures, not all structures, relating to the embodiments of the present invention are shown in the drawings.
Fig. 1 is a flowchart of a high output frame rate data processing method according to an embodiment of the present invention, where the embodiment is applicable to data processing under a multi-processing unit architecture, and data output at a high output frame rate is achieved, and the method may be executed by a computing device, such as an unmanned device, a handheld device, an intelligent mobile device, an intelligent automobile, an intelligent helmet, an intelligent glasses, a tablet computer, and other devices having a data processing function. In this embodiment, an example in which two processing units process millimeter wave radar signals will be described. The method specifically comprises the following steps:
and S101, performing transformation processing on the original collected data through a first processing unit to obtain data to be calculated.
The raw collected data may be information collected by a data collecting device such as a sensing device. Taking the radar device as an example, it may be an echo signal of a target object collected by a signal receiving front end. For example, the data may be received by a plurality of channels virtually using MIMO (Multiple input Multiple output) technology through a plurality of receiving antennas.
The first processing unit may be an FPGA (programmable gate array) processing unit, where the FPGA processing unit is a semi-custom circuit in an asic, and is a programmable logic array, and can effectively solve the problem of a small number of gate circuits in the original device. The basic structure of the system comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit.
In one embodiment, the transform process may be a fourier transform process performed on the raw acquisition data, and may be a one-dimensional fourier transform process and a two-dimensional fourier transform process performed on the radar echo signal, for example. The original collected data may be subjected to one-dimensional fourier transform, and then two-dimensional fourier transform processing is performed based on a result of the one-dimensional fourier transform, so as to obtain a distance and a speed of a target corresponding to the radar echo signal.
Step S102, calculating the data to be calculated through the first processing unit based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated.
In one embodiment, the preset target data is obtained by pre-importing a processing algorithm in the first processing unit to calculate the data to be calculated, where the imported algorithm is, for example, radar signal processing, and includes a digital beam forming algorithm or other algorithms for obtaining a target angle. Taking the data to be calculated as radar signal data after two-dimensional Fourier transform as an example, the data to be calculated is calculated through a processing algorithm to obtain data containing a target angle. Different from the existing processing mode of the architecture, in the existing multi-processing unit architecture, the first processing unit transmits the data to be calculated to the second processing unit through the bus to perform algorithm processing, and the information transmission between the processing units is performed in a bus control mode, so that the time consumption is obviously increased along with the increase of the data processing amount. For the case of data with high output frame rate, such as radar device application, when the echo signal receiving channel is usually 16 channels or more, the final data output by the bus control method needs at least tens of milliseconds, and when the radar device is applied in function extension, such as application of rotating radar or swinging radar, the performance of the radar device will be greatly affected.
In the step, the corresponding processing algorithm is pre-imported into the first processing unit to complete the processing of the data to be calculated in the first processing unit to obtain the preset target information, the data volume of the preset target information is obviously smaller than that of the data to be calculated, and the problems of data blockage and high transmission data delay caused by a bus control transmission mode in the subsequent data transmission process are avoided.
Step S103, transmitting the preset target data to a second processing unit through the first processing unit, so that the second processing unit outputs the preset target data.
The second processing unit can be an ARM processing unit, and the ARM processing unit is a low-power-consumption and low-cost processing unit, supports a Thumb (16-bit)/ARM (32-bit) dual instruction set, and is compatible with an 8-bit/16-bit device. The first processing unit transmits the preset target data with the significantly reduced data volume to the second processing unit, and the data volume is significantly reduced, so that the preset target data can be transmitted from the first processing unit to the second processing unit in a bus control transmission mode. The second processing unit can correspondingly output the preset target data after receiving the preset target data.
According to the scheme, the processing algorithm pre-introduced into the first processing unit is used for self-processing the data to be calculated, which has a large data volume and needs to be transmitted to the second processing unit originally, so that a small amount of data interaction between the first processing unit and the second processing unit is realized, the problem that the bus transmission rate is limited due to the transmission of a large amount of data is solved, the problem that the transmission rate is limited due to the fact that the data to be calculated generated by the FPGA unit is transmitted to the ARM unit to be processed in the Xilinx Zynq70xx series in the existing hardware design framework in an AXI bus control mode is solved, and the data processing capacity is remarkably improved.
On the basis of the above scheme, the first processing unit performs a first transformation process on the raw acquisition data, including: the first processing unit executes transformation processing on the original acquisition data, and synchronously acquires the original acquisition data, wherein the original acquisition data comprises radar echo data. In one embodiment, taking the first processing unit as an FPGA processing unit as an example, by using the data concurrent processing capability of the FPGA processing unit, the original acquired data is synchronously acquired while being transformed, so that the data processing speed is further increased.
On the basis of the above scheme, before the first processing unit performs the transformation processing on the original acquired data, the method further includes a system initialization step performed by the second processing unit, taking the second processing unit as an ARM processing unit as an example, and specifically includes: and the ARM processing unit initializes the FPGA processing unit and configures a front-end processing module. The initialization configuration performed by the ARM processing unit comprises information transmission configuration performed on the FPGA processing unit, and configuration of a front-end processing module such as a radar chip comprises configuration of a phase-locked loop, a voltage-controlled oscillator, a transmitting front end and a receiving front end. Besides, the FPGA unit also includes a configuration for the data size of the raw collected data and a specific transform process, for example, the transform process is a fourier transform process, which includes a configuration of specific fourier transform related calculation parameters.
Fig. 2 is a flowchart of another high-output frame rate data processing method according to an embodiment of the present invention, which shows a specific process of importing a processing algorithm into a first processing unit. As shown in fig. 2, the technical solution is as follows:
step S201, the first processing unit executes transformation processing on the test acquisition data to obtain test calculation data.
In one embodiment, the generation of the processing algorithm and for subsequent import may be performed by means of external software, such as Matlab software. Specifically, in the process of generating the processing algorithm, the first processing unit may first perform transformation processing on the test acquisition data, where the test acquisition data includes real or virtual data used by a developer to obtain a preset processing algorithm. Likewise, the first processing unit transforms the data to obtain corresponding results, which are defined herein as test calculation data.
Step S202, outputting the test calculation data to simulation software through the first processing unit for calculation to generate an executable file of the first processing unit.
In one embodiment, the test calculation data is obtained and input into simulation software for calculation to generate an executable file of the first processing unit. Specifically, the test calculation data obtained by the conversion processing of the first processing unit may be stored in the memory and imported into the computer processing device through a memory card, a usb disk, or other storage media, or the test calculation data may be wirelessly transmitted to the computer processing device by the first processing unit with wireless transmission capability. The simulation software is installed in the computer equipment, and the processing algorithm for the test calculation data, such as a CFAR algorithm or a variant CFAR algorithm, is realized by using Matlab software or other simulation software to perform algorithm writing, but the algorithm can also be an algorithm applied to other scenes. The specific algorithm parameters and the processing mode are adjusted according to the result of the operation of the test calculation data, and a proper processing algorithm is selected and determined according to the accuracy of the obtained calculation result. Optionally, if the first processing unit cannot identify the corresponding simulation software program, the determined code corresponding to the processing algorithm is translated into a program that can be identified by the first processing unit, and then the program is compiled to obtain the executable file of the first processing unit.
Step S203, importing the executable file by the first processing unit.
After the executable file containing the preset processing algorithm and recognizable by the first processing unit is obtained, the executable file can be imported into the first processing unit through a transmission medium such as a memory card, a U disk or a wireless network.
And S204, performing transformation processing on the original collected data through the first processing unit to obtain data to be calculated.
Step S205, calculating the data to be calculated by the first processing unit based on a pre-imported processing algorithm to obtain preset target data.
Step S206, the first processing unit transmits the preset target data to a second processing unit, so that the second processing unit outputs the preset target data.
In one embodiment, the filtering process performed on the second operation result includes a filtering process of extracting preset target data in the second operation result, where the preset target data is, for example, the determined data including the target distance and the speed. Optionally, a detection algorithm may be used for data screening.
According to the scheme, the executable file containing the preset algorithm is generated by using the simulation software, is imported into the first processing unit for complex data processing, is subjected to calculation processing in the first processing unit, and is only subjected to small-amount data transmission with the second processing unit, so that the output of the data with the high output frame rate can be realized without being limited by the transmission rate limit of the bus.
On the basis of the above scheme, after the first processing unit imports the executable file, the method further includes: and the first processing unit outputs data to be debugged to the simulation software for debugging calculation so as to generate an executable file of the first processing unit and then import the executable file. Therefore, debugging processing of the import processing algorithm is further realized, and the method can be better suitable for different scenes and the development of the technology.
Fig. 3 is a flowchart of another high-output frame rate data processing method according to an embodiment of the present invention, which provides an optimized data processing manner to improve data processing efficiency. As shown in fig. 3, the technical solution is as follows:
step S301, performing one-dimensional Fourier transform on the original collected data through a first processing unit, and deleting data of non-target information on a result after the one-dimensional Fourier transform processing based on the pre-imported processing algorithm.
After the one-dimensional Fourier transform is performed, in order to reduce the subsequent data processing amount, the operation of deleting the data of the non-target information is further included. The non-target information refers to information that is not useful for the final calculation result and is included in the first calculation result, such as noise information or other parameter information that is not used by the current function. Specifically, the deletion of the non-target information can be realized by a detection algorithm introduced in advance.
For example, fig. 3a is a schematic diagram of original acquired data subjected to one-dimensional transformation processing according to an embodiment of the present invention, as shown in fig. 3a, the original acquired data collectively includes 4 channels of data, and when deleting non-target information, as shown in fig. 3b, fig. 3b is a schematic diagram of a result of the one-dimensional transformation processing according to an embodiment of the present invention. As shown in fig. 3b, the area under the peak of each channel data is deleted, and the upper area is retained as shown in fig. 3 c. Fig. 3c is a schematic diagram of a one-dimensional transform processing result after deleting non-target information according to an embodiment of the present invention. As shown in fig. 3c, the data size obtained after screening is significantly smaller than the data size of the first operation result.
And S302, performing two-dimensional Fourier transform processing on the data deleted result to obtain data to be calculated.
In the step, because the data after the one-dimensional Fourier transform processing is greatly reduced, useless data is filtered, and the efficiency of the two-dimensional Fourier transform processing is obviously improved. Taking radar signal data processing as an example, distance information which is obtained by performing one-dimensional Fourier transform on original collected data and is taken as a target is subjected to two-dimensional Fourier transform, the two-dimensional Fourier transform aims at obtaining speed information of the target, the data containing the speed information is determined as data to be calculated, and then the data is processed by a preset processing algorithm for importing to obtain preset target data, such as angle data of the target.
Step S303, calculating the data to be calculated by the first processing unit based on a pre-imported processing algorithm to obtain preset target data, where a data amount of the preset target data is smaller than a data amount of the data to be calculated.
In an embodiment, a final result is shown in fig. 3d, and fig. 3d is a schematic diagram of calculating data to be calculated to obtain preset target data according to an embodiment of the present invention. The distance of the target corresponding to the x coordinate, the speed of the target of the y coordinate (calculated according to the set radio frequency parameters), and a preset processing algorithm for importing each distance peak value and speed peak value in the direction of the antenna channel, i.e. the z axis, such as a digital beam forming algorithm, can obtain the distance, speed and angle of a plurality of targets.
Step S304, the first processing unit transmits the preset target data to a second processing unit, so that the second processing unit outputs the preset target data.
Step S305, storing the screening result data in the shared memory through the second processing unit.
According to the scheme, the first processing unit performs one-dimensional Fourier transform on the original collected data, performs data deletion of non-target information on the result after the one-dimensional Fourier transform processing based on a pre-imported processing algorithm, and performs two-dimensional Fourier transform processing on the result after the data deletion to obtain the data to be calculated, so that the data operation amount is remarkably reduced, and the data processing efficiency is further improved.
On the basis of the above technical solution, after the first processing unit transmits the preset target data to the second processing unit, the method further includes: and the second processing unit outputs the preset target data to a data output module when the second processing unit is in an idle state at present.
Fig. 4 is a flowchart of another high-output frame rate data processing method according to an embodiment of the present invention, which shows a specific transmission manner of preset target data. As shown in fig. 4, the technical solution is as follows:
step S401, the original collected data are transformed through the first processing unit, and data to be calculated are obtained.
Step S402, calculating the data to be calculated through the first processing unit based on a pre-imported processing algorithm to obtain preset target data.
Step S403, storing the preset target data in a shared memory through the first processing unit, and notifying the second processing unit to read the preset target data, so that the second processing unit outputs the preset target data.
In one embodiment, the data acquisition and storage of the first processing unit and the second processing unit are realized by using a shared memory, the problem that the bus data transmission rate is limited in a bus control mode is solved, and the data transmission speed can be remarkably improved.
According to the scheme, in the data processing of the multi-processing unit, the problem of low data processing efficiency in the prior art is solved by using the shared memory for information transmission, and the data processing capacity is remarkably improved. By the scheme, the final processing result can be efficiently and timely obtained by aiming at multi-channel data calculation, and the timeliness of data processing is guaranteed.
Fig. 5 is a block diagram of a high-output frame rate data processing apparatus according to an embodiment of the present invention, which is configured to execute the high-output frame rate data processing method according to the above embodiment, and has functional modules and beneficial effects corresponding to the execution method. As shown in fig. 5, the apparatus specifically includes: a first processing unit 101 and a second processing unit 102, wherein,
the first processing unit 101 is configured to perform transformation processing on original acquired data to obtain data to be calculated, calculate the data to be calculated based on a pre-imported processing algorithm to obtain preset target data, where the data volume of the preset target data is smaller than that of the data to be calculated, and transmit the preset target data to the second processing unit;
the second processing unit 102 is configured to output the preset target data.
According to the scheme, the first processing unit performs conversion processing on the original acquired data to obtain the data to be calculated, the data to be calculated is calculated based on a pre-imported processing algorithm to obtain the preset target data, the data volume of the preset target data is smaller than that of the data to be calculated, and the first processing unit transmits the preset target data to the second processing unit for the second processing unit to output the preset target data.
In a possible embodiment, the first processing unit 101 is further configured to:
before the transformation processing is carried out on the original collected data, the transformation processing is carried out on the test collected data to obtain test calculation data;
outputting the test data to simulation software for calculation to generate an executable file of the first processing unit, wherein the executable file comprises a processing algorithm for the test calculation data;
and importing the executable file for subsequent calculation processing of the data to be calculated.
In a possible embodiment, the first processing unit 101 is further configured to:
after the first processing unit imports the executable file, outputting data to be debugged to the simulation software for debugging calculation so as to generate the executable file of the first processing unit and then imports the executable file.
In a possible embodiment, the first processing unit 101 is specifically configured to:
and after the one-dimensional Fourier transform processing is carried out on the original collected data, the two-dimensional Fourier transform processing is carried out to obtain the data to be calculated.
In a possible embodiment, the first processing unit 101 is specifically configured to:
performing one-dimensional Fourier transform on the original acquired data, and deleting non-target information data of the result after the one-dimensional Fourier transform processing based on the pre-imported processing algorithm;
and performing two-dimensional Fourier transform processing on the result after the data deletion to obtain the data to be calculated.
In a possible embodiment, the first processing unit 101 is specifically configured to:
transmitting the preset target data to a second processing unit based on a data transmission bus; or the like, or, alternatively,
and storing the preset target data into a shared memory, and informing the second processing unit to read.
In a possible embodiment, the first processing unit 101 is specifically configured to:
and performing transformation processing on the original acquisition data, and synchronously acquiring the original acquisition data, wherein the original acquisition data comprises radar echo data.
In a possible embodiment, the second processing unit 102 is further configured to:
and when the current state is in an idle state, outputting the preset target data to a data output module.
In one possible embodiment, the first processing unit comprises an FPGA processing unit, the second processing unit comprises an ARM processing unit, and the ARM processing unit is further configured to:
before the first processing unit performs conversion processing on the original acquired data, the FPGA processing unit is initialized, and a front-end processing module is configured.
Fig. 6 is a block diagram of a high-output frame rate data processing system according to an embodiment of the present invention, where the system includes a front-end processing module 201, a data processing module 202, and a data output module 203, where the data processing module 202 is connected to the front-end processing module 201 and the data output module 203, respectively, and the data processing module 202 includes a first processing unit 2021 and a second processing unit 2022;
the front-end processing module 201 is configured to collect original collected data;
the first processing unit 2021 is configured to obtain original collected data collected by the front-end processing module 201, perform transformation processing on the original collected data to obtain data to be calculated, calculate the data to be calculated by using a pre-imported processing algorithm to obtain preset target data, where a data amount of the preset target data is smaller than a data amount of the data to be calculated, transmit the preset target data to the second processing unit 2022, and use the second processing unit 2022 to output the preset target data;
the second processing unit 2022 is configured to obtain and output preset target data obtained by the first processing unit 2021;
the data output module 203 is configured to output the calculation result of the data processing module 202.
Therefore, the problem of low data processing efficiency caused by data transmission by using a bus under a multi-processing unit architecture in the prior art when high-output frame rate data is processed is solved, and the data processing capability is remarkably improved.
Fig. 7 is a schematic structural diagram of a high-output frame rate data processing apparatus according to an embodiment of the present invention, and as shown in fig. 7, the apparatus includes a first processing unit 301, a second processing unit 302, a front-end processing module 303, and a data output module 304. The first processing unit 301, the second processing unit 302, the front-end processing module 303 and the data output module 304 in the device may be connected by a bus or other means, and the bus connection is taken as an example in fig. 7. Wherein each processing unit is provided with a respective processor chip, a program storage device, which is a computer readable storage medium and can be used for storing software programs, computer executable programs, and modules, such as program instructions/modules corresponding to the high output frame rate data processing method in the embodiment of the present invention. The processor chip executes various functional applications and data processing of the device by running software programs, instructions and modules stored in the program storage device, namely, the high output frame rate data processing method is realized. The front-end processing module 303 may be configured to receive an external signal for analysis processing by the processing unit. The data output module 304 is used for outputting the calculation result data of the processing unit.
Fig. 8 is a schematic structural diagram of a radar apparatus according to an embodiment of the present invention, and as shown in fig. 8, the radar apparatus 400 includes a front-end processing module 401 for collecting raw collected data; the data processing module 402 is configured to process the raw collected data by using the high-output frame rate data processing method according to the embodiment of the present invention, and may be understood as: when the original collected data is processed by the data processing module, the data processing module realizes the high-output frame rate data processing method of the embodiment of the invention. The radar device may be a device that can implement a radar function integrated in an unmanned device. The embodiment of the invention also provides a movable platform, which comprises the radar equipment described in the embodiment of the invention, for example, the radar equipment can be carried in the movable platform to realize the radar function, and meanwhile, the high-output frame rate data processing method described in the embodiment of the invention is realized.
Embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a method for high output frame rate data processing, the method including:
the first processing unit executes transformation processing on the original collected data to obtain data to be calculated;
the first processing unit calculates the data to be calculated based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated;
and the first processing unit transmits the preset target data to a second processing unit, and the second processing unit is used for outputting the preset target data.
It should be noted that, in the embodiment of the high output frame rate data processing, the included units and modules are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the embodiment of the invention.
The foregoing is considered as illustrative of the preferred embodiments of the invention and the technical principles employed. Those skilled in the art will appreciate that the embodiments of the present invention are not limited to the specific embodiments described herein, and that various obvious changes, adaptations, and substitutions are possible, without departing from the scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention have been described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and many other equivalent embodiments may be included without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.
Claims (15)
1. The high-output frame rate data processing method is characterized by comprising the following steps:
performing transformation processing on the original collected data through a first processing unit to obtain data to be calculated;
calculating the data to be calculated by the first processing unit based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated;
and transmitting the preset target data to a second processing unit through the first processing unit, wherein the second processing unit is used for outputting the preset target data.
2. The method as claimed in claim 1, further comprising, before the performing the transformation process on the raw collected data by the first processing unit:
executing transformation processing on the test acquisition data through a first processing unit to obtain test calculation data;
outputting the test data to simulation software through the first processing unit for calculation so as to generate an executable file of the first processing unit, wherein the executable file comprises a processing algorithm of the test calculation data;
and importing the executable file through the first processing unit so as to be used for the subsequent calculation processing of the data to be calculated.
3. The method as claimed in claim 2, further comprising, after the importing of the executable file by the first processing unit, the following steps:
and outputting data to be debugged to the simulation software through the first processing unit for debugging calculation so as to generate an executable file of the first processing unit and then importing the executable file.
4. The method as claimed in claim 1, wherein the performing transformation processing on the raw collected data by the first processing unit to obtain data to be calculated includes:
the first processing unit executes one-dimensional Fourier transform processing on the original collected data, and then executes two-dimensional Fourier transform processing to obtain data to be calculated.
5. The method as claimed in claim 1, wherein the transforming the original collected data by the first processing unit to obtain the data to be calculated comprises:
performing one-dimensional Fourier transform on the original acquired data through a first processing unit, and deleting data of non-target information on a result after the one-dimensional Fourier transform processing based on the pre-imported processing algorithm;
and performing two-dimensional Fourier transform processing on the result after the data deletion to obtain the data to be calculated.
6. The method as claimed in any of claims 1 to 5, wherein the transmitting the preset target data to a second processing unit by the first processing unit comprises:
transmitting the preset target data to a second processing unit through the first processing unit based on a data transmission bus; or the like, or, alternatively,
and storing the preset target data into a shared memory through the first processing unit, and informing the second processing unit to read.
7. The method as claimed in any of claims 1-5, wherein the performing, by the first processing unit, the transformation process on the raw collected data comprises:
and performing transformation processing on the original acquired data through a first processing unit, and synchronously acquiring the original acquired data, wherein the original acquired data comprises radar echo data.
8. The method as claimed in any of claims 1 to 5, further comprising, after the transmitting the preset target data to a second processing unit by the first processing unit:
and when the second processing unit is in an idle state currently, outputting the preset target data to a data output module through the second processing unit.
9. The method of any of claims 1-5, wherein the first processing unit comprises an FPGA processing unit, the second processing unit comprises an ARM processing unit, and before the performing the transformation process on the raw collected data by the first processing unit, the method further comprises:
and initializing the FPGA processing unit through the ARM processing unit, and configuring a front-end processing module.
10. A high output frame rate data processing apparatus, comprising:
the first processing unit is used for performing transformation processing on the original collected data to obtain data to be calculated, calculating the data to be calculated based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated, and transmitting the preset target data to the second processing unit;
and the second processing unit is used for outputting the preset target data.
11. The high-output frame rate data processing system comprises a front-end processing module, a data processing module and a data output module, wherein the data processing module is respectively connected with the front-end processing module and the data output module, and comprises a first processing unit and a second processing unit;
the front-end processing module is used for acquiring original acquisition data;
the first processing unit is used for performing transformation processing on the original collected data to obtain data to be calculated, calculating the data to be calculated based on a pre-imported processing algorithm to obtain preset target data, wherein the data volume of the preset target data is smaller than that of the data to be calculated, and transmitting the preset target data to the second processing unit;
the second processing unit is used for outputting the preset target data to the data output module;
and the data output module is used for outputting the calculation result of the data processing module.
12. A high output frame rate data processing apparatus, the apparatus comprising: two or more processors; a storage device, configured to store two or more programs, when the two or more programs are executed by the two or more processors, so that the two or more processors implement the high-output frame rate data processing method according to any one of claims 1 to 9.
13. A radar apparatus, comprising: the front-end processing module is used for acquiring original acquisition data; a data processing module, configured to process the raw collected data by the high output frame rate data processing method according to any one of claims 1 to 9.
14. A movable platform comprising the radar apparatus of claim 13.
15. A storage medium storing computer executable instructions for performing the high output frame rate data processing method of any one of claims 1 to 9 when executed by a computer processor.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103616681A (en) * | 2013-12-04 | 2014-03-05 | 西安电子科技大学 | Radar imaging method based on Zynq-series FPGA |
| US20190336101A1 (en) * | 2016-11-16 | 2019-11-07 | Teratech Corporation | Portable ultrasound system |
| CN112731302A (en) * | 2021-04-06 | 2021-04-30 | 湖南纳雷科技有限公司 | STM32 and FPGA-based reverse radar signal processing system and method |
-
2021
- 2021-06-29 CN CN202110728791.XA patent/CN113434457A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103616681A (en) * | 2013-12-04 | 2014-03-05 | 西安电子科技大学 | Radar imaging method based on Zynq-series FPGA |
| US20190336101A1 (en) * | 2016-11-16 | 2019-11-07 | Teratech Corporation | Portable ultrasound system |
| CN112731302A (en) * | 2021-04-06 | 2021-04-30 | 湖南纳雷科技有限公司 | STM32 and FPGA-based reverse radar signal processing system and method |
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