CN113422670B - Low-complexity seven-path CCSDS standard near-earth communication encoder and control method - Google Patents

Low-complexity seven-path CCSDS standard near-earth communication encoder and control method Download PDF

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CN113422670B
CN113422670B CN202110619694.7A CN202110619694A CN113422670B CN 113422670 B CN113422670 B CN 113422670B CN 202110619694 A CN202110619694 A CN 202110619694A CN 113422670 B CN113422670 B CN 113422670B
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unit
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bits
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CN113422670A (en
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张南
丁泽光
宫丰奎
杨浩
张师笑
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Xidian University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
    • H04L1/0618—Space-time coding
    • H04L1/0675—Space-time coding characterised by the signaling
    • H04L1/0681—Space-time coding characterised by the signaling adapting space time parameters, i.e. modifying the space time matrix
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention belongs to the technical field of channel coding of space communication, and discloses a low-complexity seven-path CCSDS standard ground proximity communication encoder and a control method thereof, wherein the low-complexity seven-path CCSDS standard ground proximity communication encoder comprises a generating matrix loading unit, a delay unit, an encoding processing unit, a data selection unit and a data shaping unit; after the coded information bits are input, the information bits are respectively triggered to generate a matrix loading unit and a delay unit to carry out coding preprocessing operation; the information bits for generating the matrix delay are loaded and sent to an encoding processing unit for block encoding operation; under the control of the data selection unit, outputting the delayed information bits and the encoded check bits to obtain encoded blocks; and the seven paths of coding blocks are converted into eight paths of coding blocks through the data shaping unit, and the eight paths of coding blocks finally used for transmission are obtained. The invention uses the idea of parallel computation, increases a small amount of hardware resource consumption, replaces the great improvement of the throughput of the encoder, and is suitable for hardware realization.

Description

Low-complexity seven-path CCSDS standard near-earth communication encoder and control method
Technical Field
The invention belongs to the technical field of channel coding of space communication, and particularly relates to a low-complexity seven-path CCSDS standard ground proximity communication encoder and a control method thereof.
Background
At present, in the field of channel coding of spatial communication, an LDPC code has the characteristics of complete coding theory, low coding and decoding complexity, suitability for designing a high-throughput parallel coder and the like. After 2010, the LDPC code starts to become a channel coding standard for near-earth space and deep space communication recommended by spatial communication standardization organizations such as CCSDS and ETSI. In 2011, the moon detector of goddess-ei china adopts an LDPC code as a coding scheme of a downlink data link. With the development of space technology, the demand for real-time transmission of high-definition images and even high-definition video data is more and more extensive. This requirement places a gigabit transmission requirement on the downstream transmission rate of data on the spacecraft. The space-borne equipment has the characteristic of low resource occupancy rate due to the special environment of the space communication equipment, and the high-speed downlink channel coding poses a challenge to the low resource requirement of the space-borne coder. Therefore, a low-complexity and high-throughput coding algorithm and an architecture scheme are provided, and the method has high research and application values.
In the research and implementation of a low-complexity LDPC code encoding and decoding algorithm of Xiaojing Jingning of Harbin industry university, a 7-channel parallel basic type (8176, 7154) encoding implementation FPGA implementation block diagram is given, and an encoding algorithm in the scheme is not suitable for actual system channel transmission; in the key technical research of low-density parity check codes in spatial communication, 8-path parallel shortened codes (8160, 7136) are designed by Yanwei university of Chinese academy of sciences, namely, a data preprocessing unit, a delay unit, a code operation unit, an output cache unit and an output data switching unit are sequentially carried out on input information bits, and the realization complexity and the occupied logic resources are high.
Through the above analysis, the problems and defects of the prior art are as follows:
(1) the existing basic type (8176, 7154) coding architecture is not suitable for actual system channel transmission.
(2) The existing CCSDS standard has the problem that complexity and throughput are difficult to meet simultaneously in the design of the near-earth communication codes.
(3) The existing method for designing 8-path parallel shortened (8160, 7136) codes has high implementation complexity and occupied logic resources.
The difficulty in solving the above problems and defects is:
in order to solve the problems existing in the existing CCSDS standard ground proximity communication coding, the structure of the coder needs to be improved, and the realization complexity and the hardware resource occupation of the coder can be reduced while the throughput can not be obviously reduced.
The significance for solving the problems and the defects is as follows:
the LDPC encoder scheme which simultaneously meets the requirements of a satellite-borne system on the throughput is designed, the cost of the system can be reduced, and the LDPC encoder scheme has a very wide application prospect.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a low-complexity seven-path CCSDS standard ground proximity communication encoder and a control method, in particular to a low-complexity seven-path CCSDS standard ground proximity communication encoder and a control method based on an FPGA, aiming at solving the problem that the complexity and the throughput in the existing CCSDS standard ground proximity communication are difficult to meet simultaneously.
The invention is realized in this way, a low-complexity seven-path CCSDS standard near-ground communication encoder, which comprises a generating matrix loading unit, a delay unit, an encoding processing unit, a data selection unit and a data shaping unit;
the generating matrix loading unit comprises a loading generating matrix module and a seven-path generating matrix generating module;
the coding processing unit comprises seven coding modules and an accumulation summation module;
and the data shaping unit is used for shaping the seven paths of coding blocks into eight paths of transmission code blocks.
Further, the generator matrix loading unit includes:
the loading generation matrix module is used for loading a generation matrix;
and the seven-path generating matrix generating module is used for generating a generating matrix corresponding to each path of coding information bits.
Further, in the loading generator matrix module, the loading generator matrix is divided into two cases:
initializing and reading a generating matrix in an RAM when an input information bit is just input; and secondly, after the initial loading is finished, pre-reading a generated matrix in the RAM.
Further, the encoding processing unit includes:
the seven-path coding module is used for simultaneously processing each path of codes and carrying out operation coding operation;
and the accumulation summation module is used for performing modulo two summation operation on the part of each path and the intermediate variable.
Another object of the present invention is to provide a method for controlling a low-complexity seven-path CCSDS standard ground proximity communication encoder, using the low-complexity seven-path CCSDS standard ground proximity communication encoder, the method comprising:
after the coded information bit is input, triggering the information bit to generate a matrix loading unit and a delay unit respectively to carry out coding preprocessing operation;
step two, the loaded information bits for generating the matrix delay are sent to an encoding processing unit for block encoding operation;
thirdly, under the control of the data selection unit, obtaining a coding block from the delayed information bit and the coded check bit;
and step four, converting the seven paths of coding blocks into eight paths of coding blocks through the data shaping unit to obtain the eight paths of coding blocks finally used for transmission.
Further, the method for controlling the low-complexity seven-path CCSDS standard ground proximity communication encoder further includes:
seven paths of information bits 7154 to be coded which are input in parallel are divided into two parts, one part is sent into a delay unit, the delay unit carries out proper delay operation on the sent 7-bit parallel data, and the delayed clock period is only 5 system clocks; the other part of the information bits to be coded are sent to a coding operation unit in a 7-bit parallel mode, the data to be coded of the coding operation unit execute 7-bit parallel coding operation, the coding operation unit comprises 14 cyclic shifters, each cyclic shifter shifts 7 bits in each clock period, and the information bits to be coded obtain 1022-bit parts and intermediate variables; the encoding operation unit carries out modulo two summation on the generated 1022-bit intermediate variables in the accumulator;
when the encoding is finished, the accumulation register transmits the stored 1022-bit check bits to the output data selection unit in a left shift mode; the output data selection unit selects data to be output according to the control signal sent by the state machine; for a shortened encoder, the first 18 bits of data are removed when the encoder outputs the data; secondly, selecting information bit data, and outputting seven paths of delay data bits sent by the delay unit in parallel by a data output selection unit; then, selecting check bit data, and outputting the check bit data sent by the accumulation register by an output data selection unit in seven paths in parallel; shaping the output data, and adding 20 s, wherein the data output by the output data shaping unit is the code word of the final code; the whole parallel coding process is controlled by a state machine, a control signal is given out, and matrix reading, coding state control, output signal selection control and data shaping control are carried out.
Further, the method for controlling the low-complexity seven-path CCSDS standard ground proximity communication encoder further includes:
for the non-unit array part, 14 generator matrixes are divided into 7 parts, the length of each part is 1022, the first row of the cyclic sub-array is respectively stored in the address of a ROM, the bit width of the ROM is 1022, and the depth of the ROM is 7; inputting 511 bits of the information sequence and reloading a new generating matrix after encoding until all the encoding bits are finished; when the input information sequence starts to be input, the enabling of the coding module is pulled up, and the coding module starts to work;
firstly, a first row 1022 of a cyclic sub-block is divided into two parts from a ROM, a generating matrix of each part 511 is properly shifted and respectively sent into 7 cyclic shift registers, and the number of the cyclic shift registers is 14; adding 1 to the address of the ROM to read out the first row data of the next row of cyclic sub-block after 73 clocks and writing the first row data into 14 cyclic shift registers; under the drive of a clock, each bit of input bit information bits is respectively subjected to bitwise AND operation with a corresponding cyclic shift register, and the output of the bitwise AND operation and an accumulator are respectively subjected to bitwise XOR operation; when the next clock edge comes, all the shift registers with 7 bits are circularly shifted to the right, the new information bits operated in the encoder are respectively operated with the corresponding circular shift registers according to the bitwise AND operation, and the output of the bitwise AND operation and the accumulator obtained in the previous step are respectively operated according to the bitwise XOR operation; sequentially carrying out the steps until the shift registers are all circulated to the last state, and all values of one circulation sub-block are traversed in the circulation shift of the shift registers;
when the next clock comes, updating 14 cyclic shift registers, and putting the first row of data of the next row of cyclic sub-blocks; adding 1 to the address of the ROM to read out the first row data of the next row of cyclic sub-block after 73 clocks and writing the first row data into 14 cyclic shift registers; when the next clock comes, different data are respectively read in the registers, and the next operation is as shown in the step, until the address in the ROM is 7, the generated matrix is completely read, and the coding of each sub-block is completed; the bitwise exclusive-or operation yields the value of the final accumulator, which is the 1022-bit check bits.
Further, the method for controlling the low-complexity seven-path CCSDS standard ground proximity communication encoder further includes:
the 7 paths of parallel code blocks after the encoding are sent to a data shaping unit; the data shaping unit deletes the first 18 bits of zero of the input 7 paths of code block data; carrying out 7-path to 8-path data shaping operation on the rear 8158-bit data; outputting coded data after each 8-bit data is obtained; when the last 8 bits of data are input, 2 bits of zeros are added to obtain the last codeword for transmission.
Another object of the present invention is to provide a FPAG implementation circuit, wherein the circuit architecture includes a logic circuit and a control circuit, the logic circuit has a specific circuit implementation, and the control circuit, when the FPGA executes, causes the circuit to perform the following steps:
after the coded information bit is input, the information bit is respectively triggered to generate a matrix loading unit and a delay unit to carry out coding preprocessing operation; sending the loaded information bits for generating the matrix delay to an encoding processing unit for block encoding operation; under the control of the data selection unit, obtaining a coding block from the delayed information bit and the coded check bit; and converting the seven paths of coding blocks into eight paths of coding blocks through the data shaping unit to obtain the eight paths of coding blocks finally used for transmission.
Another object of the present invention is to provide a channel coding processing terminal for implementing the low-complexity seven-path CCSDS standard ground proximity communication encoder.
By combining all the technical schemes, the invention has the advantages and positive effects that: the invention provides a low-complexity seven-path CCSDS standard ground proximity communication encoder, which belongs to the technical field of error detection or forward error correction of redundant items in data representation, mainly relates to the ground proximity communication direction of a channel coding CCSDS standard, and can be used for a high-throughput channel coding system. For a seven-path CCSDS standard ground proximity communication encoder, the invention removes a data preprocessing unit, adds a data shaping unit and improves an encoding processing method, and finally greatly reduces the complexity of realizing the FPGA of the encoder on the basis of sacrificing small throughput.
The invention provides a short-type (8160, 7136) coding method and an LDPC coder in a low-complexity seven-path CCSDS standard based on FPGA, and the FPGA is used for carrying out channel coding on a coding sequence, carrying out delay, coding processing, data selection and data shaping operation on the sequence, and still realizing gigabit throughput under the condition of greatly reducing the complexity of a parallel coder.
The invention greatly reduces the complexity of FPGA realization due to the simplification of the generating matrix loading unit 1 and the coding processing unit 3, and the simplification content is as follows:
in the FPGA implementation scheme of the existing ultra-high speed encoder, taking a seven-channel parallel encoder in Shoujingting's Master thesis as an example, a data selection unit is modified, and a data shaping unit is added, so that a code block obtained by encoding is convenient for a 32-bit processor to process, and is convenient for transmission; and modifying the coding processing method, and performing generation matrix preprocessing, thereby reducing delay and further improving throughput.
In the existing implementation scheme of an FPGA, taking an eight-way parallel encoder in the doctor thesis of yanwei as an example, a data preprocessing unit is used for performing zero-padding and zero-insertion preprocessing operations on 18 bits of code words before encoding, the throughput of a design algorithm of the FPGA reaches about 1.6Gbps, a resource consumption Slice needs 10337, a trigger needs 11802, and a lookup table with 4 inputs needs 18903. The invention removes the data preprocessing module, adopts seven paths of parallel coding, the throughput reaches 1.4Gbps, the Slice on the resource needs 1502, the trigger needs 2709, and the lookup table input by 4 needs 2320.
Compared with the FPGA implementation scheme of the existing ultra-high-speed encoder, the low-complexity seven-path CCSDS standard near-earth communication encoding method and the FPGA implementation encoder provided by the invention are proved by experiments that the throughput is reduced by about 12.5%, and compared with the existing scheme, the resources in the FPGA are respectively saved by 85.5% of Slice resources, 77.0% of trigger resources and 87.7% of LUT resources of a lookup table.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for controlling a low-complexity seven-path CCSDS standard ground proximity communication encoder according to an embodiment of the present invention.
Fig. 2 is a block diagram of an overall implementation of a low-complexity seven-path CCSDS standard ground proximity communication encoder provided by an embodiment of the present invention.
Fig. 3 is a flowchart of an encoding algorithm provided by an embodiment of the present invention.
Fig. 4 is a block diagram of an FPGA implemented by an existing seven-way basic type (8176, 7154) encoding according to an embodiment of the present invention.
Fig. 5 is a block diagram of an FPGA implemented by an existing eight-way shortened (8160, 7136) code according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Aiming at the problems in the prior art, the invention provides a low-complexity seven-path CCSDS standard ground proximity communication encoder and a control method thereof, and the invention is described in detail below with reference to the attached drawings.
As shown in fig. 1, the method for controlling a low-complexity seven-path CCSDS standard ground proximity communication encoder provided in the embodiment of the present invention includes the following steps:
s101, after the coded information bit is input, the information bit is respectively triggered to generate a matrix loading unit and a delay unit to carry out coding preprocessing operation;
s102, sending the loaded information bits for generating the matrix delay to an encoding processing unit for block encoding operation;
s103, under the control of the data selection unit, obtaining a coding block from the delayed information bit and the coded check bit;
and S104, converting the seven paths of coding blocks into eight paths of coding blocks through the data shaping unit to obtain eight paths of coding blocks for transmission finally.
The low-complexity seven-path CCSDS standard ground proximity communication encoder provided by the embodiment of the invention comprises a generating matrix loading unit, a delay unit, an encoding processing unit, a data selection unit and a data shaping unit.
The generating matrix loading unit comprises a loading generating matrix module and a seven-path generating matrix generating module;
the loading generation matrix module is used for loading a generation matrix; the loading of the generator matrix is divided into two cases: initializing and reading a generating matrix in the RAM when an input information bit is just input; after initial loading, pre-reading a generated matrix in the RAM;
and the seven-path generating matrix generating module is used for generating a generating matrix corresponding to each path of coding information bits.
The coding processing unit comprises seven coding modules and an accumulation summation module;
the seven-path coding module is used for simultaneously processing each path of codes and carrying out operation coding operation;
and the accumulation summation module is used for performing modulo two summation operation on the part of each path and the intermediate variable.
And the data shaping unit is used for shaping the seven paths of coding blocks into eight paths of transmission code blocks.
The technical solution of the present invention will be further described with reference to the following examples.
Referring to fig. 4, the input information sequence is divided equally into seven portions, each having a length of 1022. For the non-unitary array portion, the first row of its circular sub-array is stored in 7 ROMs in blocks as shown, each ROM having a bit width of 1022 and a depth of 2. When the input information sequence is completed, the encoding module is enabled to be pulled high, and the encoding module starts to work. First, the first row of the cyclic sub-block is fed from 7 ROMs into 14 shift registers, respectively. Under the drive of a clock, inputting bit information bits, respectively carrying out bitwise AND operation with the corresponding shift registers, and respectively carrying out bitwise XOR operation on the output of the bitwise AND operation and an accumulator. When the next clock edge comes, all the shift registers are circularly shifted to the right, bit information bits are calculated in the encoder, bitwise AND operation is carried out on the bit information bits and the corresponding shift registers, and bitwise XOR operation is carried out on the output of the bitwise AND operation and the accumulator. The above steps are performed in sequence until the shift registers have all been cycled to the last state, and all values of a cyclic sub-block have been traversed in the cyclic shift of the shift registers. When the next clock comes, the first row of data of the next row of the cyclic sub-block is put into the 14 shift register registers. At this time, it is necessary to change the address of the ROM so that the first row data of the next row cycle sub-block can be read out at the next clock and written into 14 registers. When the next clock arrives, different data are read into the shift registers respectively, and the next operation is as shown in the foregoing. Until the data in the ROM has been read and the encoding of each sub-block has been completed. Finally, splicing the check sequences obtained by bitwise XOR operation can obtain complete 1022-bit check bits.
Referring to fig. 5, 8-way parallel input information bits to be encoded are first fed into a data preprocessing unit and a delay unit. The data preprocessing unit adds 18-bit zeros to the incoming data. And simultaneously, starting from the added zero bit, inserting 1 bit of zero at intervals of 511 bits of information bits to be coded. And sending the preprocessed information bits to be coded into a coding operation unit in parallel by 8 bits. The delay unit performs an appropriate delay operation on the inputted 8-bit parallel data. The number of delayed clock cycles is related to the number of delayed clocks from the code input to the code output of the coding unit. After the delay unit carries out delay operation on the data, 8 bits of delay data are output to the output data switching unit in parallel, and meanwhile, a selection signal is output to inform the output data switching unit of whether the data selected to be output is information bit data or check bit data generated after encoding. The data to be encoded sent to the encoding arithmetic unit, in which 16 cyclic shifters each of which shifts 8 bits per clock cycle are total, performs an encoding operation similar to that in low-parallelism encoding. The encoding arithmetic unit stores the generated 1022-bit check bits in the output buffer unit. After the encoding is finished, the output buffer unit transmits the stored 1022 bits to the output data switching unit in a left shift mode. The output data switching unit selects data to be output according to the selection signal sent by the delay unit. When the selection signal is information bit data, the output data switching unit outputs 8 paths of delay data bits sent by the delay unit in parallel; when the selection signal is check bit data, the output data switching unit outputs 8 paths of the check bit data sent by the output cache unit in parallel, and the data output by the output data switching unit is the code word of the final code.
Referring to fig. 2, the low-complexity seven-path CCSDS standard ground-proximity communication encoder based on FPGA of the present invention includes: the device comprises a generator matrix loading unit 1, a delay unit 2, an encoding processing unit 3, a data selection unit 4 and a data shaping unit 5. Seven parallel inputs of information bits 7154 to be encoded are first fed into delay element 2. The information bits to be coded are sent to the coding arithmetic unit 3 in parallel by 7 bits. The delay unit 2 performs an appropriate delay operation on the fed 7-bit parallel data. The delayed clock period is only 5 system clocks. There are 14 cyclic shifters in the code arithmetic unit 3, and each cyclic shifter shifts 7 bits per clock cycle. The encoding arithmetic unit 3 performs accumulation modulo 2 summation on the generated 1022-bit intermediate variables in the accumulator. When the encoding is completed, the accumulator register transfers the stored 1022-bit check bits to the output data selection unit 4 by shifting left. The output data selection unit 4 selects data to be output in accordance with a control signal sent from the state machine. For the shortened (81760, 7136) encoder, the first 18 bits of data are firstly removed when the encoder outputs the data; secondly, selecting information bit data, and outputting seven paths of delay data bits sent by the delay unit 2 in parallel by a data selection unit 4; then, selecting check bit data, and outputting seven paths of check bit data sent by the accumulation register in parallel by the data selection unit 4; and finally, shaping the output data, and adding 20 s, wherein the data output by the output data shaping unit is the finally coded code word. The whole parallel coding process is controlled by a state machine, a control signal is given out, the reading of a generating matrix, the state control of the coding process, the selection control of an output signal and the shaping control of data are carried out.
Referring to fig. 3, first, data fir _ rowB stored in the head address of the generator matrix processing module ROM is assigned to the initialization shift register shift _ fir _ rowB, which is 1022 bits and corresponds to 2 circular shift registers in the coding unit. Shift _ fir _ rowB _ s0, shift _ fir _ rowB _ s1, shift _ fir _ rowB _ s2, shift _ fir _ rowB _ s3, shift _ fir _ rowB _ s4, shift _ fir _ rowB _ s5, and shift _ fir _ rowB _ s6 are obtained by appropriate shifting of shift _ fir _ rowB. Then, the information bits and shift _ fir _ rowB _ s0, shift _ fir _ rowB _ s1, shift _ fir _ rowB _ s2, shift _ fir _ rowB _ s3, shift _ fir _ rowB _ s4, shift _ fir _ rowB _ s5, and shift _ fir _ rowB _ s6 respectively perform and logical operation, the obtained result is exclusive-or-ed with sum _ prod, and the accumulator register sum _ prod is updated. Each time information bit data is input, sum _ prod updates the assignment value according to the above procedure. When the counting module counts the information bit number to be integral multiple of 73, the generated matrix vector fir _ rowB is reloaded, the value of the shift register shift _ fir _ rowB is replaced, and the shift _ fir _ rowB is assigned each time to pre-read the data in the address in advance, so that the corresponding generated matrix sub-matrix is ensured to be obtained. When the input of the last information bit is finished, the data in the register sum _ prod is the check sequence corresponding to the information sequence, and after the output of the information sequence and the check sequence of the data selector is finished, the register sum _ prod is cleared, so that the information sequence of the next frame can be directly input.
In summary, for a seven-path CCSDS standard ground proximity communication encoder, the present invention removes a data preprocessing unit, adds a data shaping unit, and improves an encoding processing method, and finally, on the basis of reducing a small throughput, greatly reduces the complexity of implementing an encoder FPGA.
Compared with the FPGA implementation scheme of the existing ultra-high-speed encoder, the low-complexity seven-path CCSDS standard ground-to-earth communication encoding method and the FPGA implementation encoder provided by the invention have the following results: the throughput of the invention is reduced by about 12.5%, and compared with the existing scheme, the resources in the used FPGA respectively save 85.5% Slice resources, 77.0% trigger resources and 87.7% lookup table LUT resources.
The above description is only for the purpose of illustrating the embodiments of the present invention, and the scope of the present invention should not be limited thereto, and any modifications, equivalents and improvements made by those skilled in the art within the technical scope of the present invention as disclosed in the present invention should be covered by the scope of the present invention.

Claims (9)

1. A control method for a low-complexity seven-path CCSDS standard ground proximity communication encoder is characterized in that the control method for the low-complexity seven-path CCSDS standard ground proximity communication encoder comprises the following steps:
respectively triggering the input coding information bits to generate a matrix loading unit and a delay unit for coding preprocessing;
sending the loaded information bits for generating matrix delay to an encoding processing unit for block encoding;
obtaining seven encoding blocks through the delayed information bits and the encoded check bits under the control of the data selection unit;
converting the seven paths of coding blocks by a data shaping unit to obtain eight paths of coding blocks for transmission;
the control method of the low-complexity seven-path CCSDS standard ground proximity communication encoder further comprises the following steps:
seven paths of information bits 7154 to be coded which are input in parallel are divided into two parts, one part is sent into a delay unit, the delay unit carries out proper delay operation on the sent 7-bit parallel data, and the delayed clock period is only 5 system clocks; the other part of the information bits to be coded are sent to a coding operation unit in a 7-bit parallel mode, the data to be coded of the coding operation unit execute 7-bit parallel coding operation, the coding operation unit comprises 14 cyclic shifters, each cyclic shifter shifts 7 bits in each clock period, and the information bits to be coded obtain 1022-bit parts and intermediate variables; the encoding operation unit carries out modulo two summation on the generated 1022-bit intermediate variables in an accumulator;
when the encoding is finished, the accumulation register transmits the stored 1022-bit check bits to the output data selection unit in a left shift mode; the output data selection unit selects data to be output according to the control signal sent by the state machine; for a shortened encoder, the first 18 bits of data are removed when the encoder outputs the data; selecting information bit data, and outputting seven paths of delay data bits sent by the delay unit in parallel by the output data selection unit; then, selecting check bit data, and outputting the check bit data sent by the accumulation register by an output data selection unit in seven paths in parallel; shaping the output data, adding 20 s, and the data output by the output data shaping unit is the code word of the last code; the whole parallel coding process is controlled by a state machine, a control signal is given, and matrix reading, coding state control, output signal selection control and data shaping control are carried out.
2. The method of claim 1, wherein the method further comprises:
for the non-unit array part, 14 generator matrixes are divided into 7 parts, the length of each part is 1022, the first row of a cyclic sub-array of each part is respectively stored in the address of a Read Only Memory (ROM), the bit width of the ROM is 1022, and the depth of the ROM is 7; inputting 511 bits of the information sequence and reloading a new generating matrix after encoding until all the encoding bits are finished; when the input information sequence starts to be input, the enabling of the coding module is pulled up, and the coding module starts to work;
firstly, a first row 1022 of a cyclic sub-block is divided into two parts from a ROM, a generated matrix of each part 511 is properly shifted and respectively sent into 7 cyclic shift registers, and the number of the cyclic shift registers is 14; adding 1 to the address of the ROM to read out the first row data of the next row of cyclic sub-block after 73 clocks and writing the first row data into 14 cyclic shift registers; under the drive of a clock, each bit of input bit information bits is respectively subjected to bitwise AND operation with a corresponding cyclic shift register, and the output of the bitwise AND operation and an accumulator are respectively subjected to bitwise XOR operation; when the next clock edge arrives, all the shift registers with 7 bits are circularly shifted to the right, at the moment, the new information bits operated in the encoder are respectively operated with the corresponding circular shift registers according to the bitwise AND operation, and the output of the bitwise AND operation and the accumulator obtained in the last step are respectively operated according to the bitwise XOR operation; sequentially carrying out the steps until the shift registers are all circulated to the last state, and all values of one circulation sub-block are traversed in the circulation shift of the shift registers;
when the next clock comes, updating 14 cyclic shift registers, and putting the first row of data of the next row of cyclic sub-blocks; adding 1 to the address of the ROM to read out the first row data of the next row of cyclic sub-block after 73 clocks and writing the first row data into 14 cyclic shift registers; when the next clock comes, different data are respectively read in the registers, and the next operation is as shown in the step, until the address in the ROM is 7, the generated matrix is completely read, and the coding of each sub-block is completed; the bitwise exclusive-or operation yields the value of the final accumulator, which is the 1022-bit check bits.
3. The method of claim 1, wherein the method further comprises:
the 7 paths of parallel code blocks after the encoding are sent to a data shaping unit; the data shaping unit deletes the first 18 bits of zero of the input 7 paths of code block data; carrying out 7-path to 8-path data shaping operation on the rear 8158-bit data; outputting the coded data by performing coded data according to the 8-bit data; when the last 8 bits of data are input, 2 bits of zeros are added to obtain the last codeword for transmission.
4. A low-complexity seven-path CCSDS standard ground proximity communication encoder for implementing the control method of any one of claims 1 to 3, wherein the low-complexity seven-path CCSDS standard ground proximity communication encoder comprises a generator matrix loading unit, a delay unit, an encoding processing unit, a data selection unit and a data shaping unit;
the generating matrix loading unit comprises a loading generating matrix module and a seven-path generating matrix generating module;
the coding processing unit comprises seven coding modules and an accumulation summation module;
and the data shaping unit is used for shaping the seven paths of coding blocks into eight paths of transmission code blocks.
5. The low complexity seven-way CCSDS standard ground proximity communications encoder of claim 4, wherein said generator matrix loading unit comprises:
the loading generation matrix module is used for loading a generation matrix;
and the seven-path generating matrix generating module is used for generating a generating matrix corresponding to each path of coding information bits.
6. The low complexity seven-way CCSDS standard ground proximity communication encoder of claim 4, wherein in the load generator matrix module, said load generator matrix is divided into two cases:
initializing and reading a generating matrix in the RAM when an input information bit is just input; and secondly, after the initial loading is finished, pre-reading a generated matrix in the RAM.
7. The low complexity seven-pass CCSDS standard ground proximity communication encoder of claim 4, wherein said encoding processing unit comprises:
the seven-path coding module is used for simultaneously processing each path of codes and carrying out operation coding operation;
and the accumulation summation module is used for performing modulo two summation operation on the part of each path and the intermediate variable.
8. An FPAG implementation circuit, wherein the circuit architecture includes a logic circuit and a control circuit, the logic circuit has a specific circuit implementation, and the control circuit, when the FPGA executes, causes the circuit to execute the steps of the low-complexity seven-way CCSDS standard ground proximity communication encoder control method according to any one of claims 1 to 3.
9. A channel coding processing terminal, characterized in that the channel coding processing terminal is configured to implement the low-complexity seven-path CCSDS standard ground-proximity communication encoder control method according to any of claims 1-3.
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