CN113422645A - Pulse width modulation system and method - Google Patents

Abstract

The invention discloses a pulse width modulation system and a method, belonging to the technical field of communication and comprising a transmitting device, a receiving device, a Laser Diode (LD) and a photodiode array (PD); the transmitting device drives the LD to transmit pulse laser PWM signals, the PWM signals transmitted by the LD are transmitted through a channel and generate echo PWM signals after encountering an object, and the PWM signals are received by the PD array and then are transmitted to the receiving device, so that laser communication is realized. The pulse width modulation system and the method solve the problems of poor anti-interference capability, high error rate and the like in the existing laser communication mode, and the problem of strict synchronization of clock signals of a transmitting system and a receiving system is not required to be considered in Pulse Width Modulation (PWM), so that the cross-clock data transmission is more convenient, the transmission rate can reach 10MB/S, the data modulation and demodulation processes are greatly simplified, the data transmission accuracy is increased, the transmission efficiency is improved, and the pulse width modulation system and the method have certain reference value for the encoding communication of military and civil laser radars.

Description

Pulse width modulation system and method

Technical Field

The invention belongs to the technical field of communication, and particularly relates to a pulse width modulation system and a pulse width modulation method.

Background

With the development of the information era, the research prospect of the space laser communication technology is very wide, and because laser has high coherence and directivity, the laser communication has the advantages of strong anti-interference capability, good confidentiality, convenient wave band selection, large information capacity and the like. Currently, common modulation methods in laser communication include: on-off keying (OOK) modulation, Pulse Position (PPM) modulation, Pulse Interval Modulation (PIM), etc., wherein OOK modulation has high transmission power, poor interference rejection, and high error rate; PPM reduces the average power, but increases the bandwidth, and reduces the transmission speed of data; compared with the two modulation modes, the PIM modulation reduces the average symbol length, but the three modulation modes all need strict synchronization of a transmitting system and a receiving system to ensure effective transmission of data, and simultaneously, check bits are added in the OOK and PPM modulation modes during data transmission, so that data coding is more complicated.

Disclosure of Invention

The invention provides a pulse width modulation system and a pulse width modulation method, which solve the problems of poor anti-interference capability, high error rate and the like in the existing laser communication mode, and the problem of strict synchronization of clock signals of a transmitting system and a receiving system is not required to be considered in Pulse Width Modulation (PWM), so that the cross-clock data transmission is more convenient, the transmission rate can reach 10MB/S, the data modulation and demodulation processes are greatly simplified, the data transmission accuracy is increased, the transmission efficiency is improved, and the pulse width modulation system and the pulse width modulation method have certain reference value for the encoding communication of military and civil laser radars.

The invention is realized by the following technical scheme:

a pulse width modulation system comprises a transmitting device 1, a receiving device 2, a Laser Diode (LD)6 and a photodiode array (PD) 8; the transmitting device 1 drives the LD6 to transmit a pulse laser PWM1 signal, the PWM1 signal transmitted by the LD6 is transmitted through a channel and generates an echo PWM2 signal after encountering an object 7, and the PWM2 signal is received by the PD array 8 and then sent to the receiving device 2, so that laser communication is realized.

Preferably, the transmitting device 1 is composed of a first Microcontroller (MCU)3, a first Field Programmable Gate Array (FPGA)4, a laser driving circuit 5 and a Laser Diode (LD) 6; the first microcontroller 3 decodes Data sources such as texts, pictures and audios, and sends the decoded Data1 to the first FPGA4, and a sending signal TXD of the first FPGA4 triggers the laser driving circuit 5 to drive the LD6 to generate pulsed laser.

Preferably, the receiving device 2 is composed of a laser receiving circuit 9, an ADC10, a second FPGA11, a second microcontroller 12 and an LCD display screen 13; the second FPGA11 sends out Con1 and Con2 signals to control row gating and column gating of the PD array 8, the PD in the PD array 8 receives pulsed light signals in a channel after being selected, the laser receiving circuit 9 converts the light signals received by the PD array 8 into electrical signals and outputs the electrical signals as RXD1 signals, the ADC10 converts the electrical signals RXD1 into digital RXD2 and sends the digital RXD2 into the second FPGA11, the second FPGA11 demodulates the received RXD2 Data and sends the demodulated Data2 into the second Microcontroller (MCU)12, and the second Microcontroller (MCU)12 encodes the Data2 Data to obtain text, picture, audio and other Data, and finally displays the Data on the LCD display 13.

Another objective of the present invention is to provide a pulse width modulation method, which specifically includes the following steps:

the method comprises the following steps:

the microcontroller modulates the received data by a PWM (pulse-width modulation) module in the FPGA to generate corresponding pulse waves, a modulation signal (TXD) generated by the PWM module is used for driving a grid driver of the laser emitting circuit, and the grid driver drives an MOS (metal oxide semiconductor) tube and is used for controlling the conduction of a laser diode to realize pulse laser (PWM) output; when the waveform of the PWM signal is at a high level, the Laser Diode (LD)6 emits light, and when the waveform of the PWM signal is at a low level, the Laser Diode (LD)6 does not emit light, so that the Data1 is converted into a light signal to be emitted;

step two:

receiving the optical signal sent in the first step and converting the optical signal into a voltage signal, specifically, when the optical signal is irradiated onto the PD array, the PD generates a photocurrent I, a transimpedance amplifier (TIA) in the laser receiving circuit converts the photocurrent I generated by the PD into a voltage V1, and a secondary Amplifier (AMP) further amplifies the voltage V1 to obtain a voltage V2, that is:

so that the laser receiving circuit converts the optical signal into a voltage signal (RXD) and outputs the voltage signal; wherein R is₁Is a feedback resistance of a transimpedance amplifier (TIA), R₂Is an input resistance of a two-stage Amplifier (AMP), R₃A feedback resistance being a secondary Amplifier (AMP);

step three: the ADC converts the voltage signal into digital quantity and sends the digital quantity to the FPGA, the FPGA demodulates the received RXD data and sends the demodulated data to the microcontroller, and the microcontroller encodes the data to obtain data such as text, pictures, audio and the like, and finally the data is displayed on the LCD screen.

Preferably, step one is as follows:

modulating Data1, wherein the Data1 is parallel Data, after the Data are converted into serial Data in the FPGA, judging whether each bit of the Data is Data '1' or Data '0' bit by bit from the highest bit of the Data, and the FPGA sends out a PWM signal according to the judgment condition; in the case of data1, the FPGA transmits a pulse signal having a narrow pulse width of T1-25 ns, and in the case of data 0, the FPGA transmits a pulse signal having a wide pulse width of T2-60 ns, thereby realizing modulation in which data is converted into a PWM signal.

Preferably, the frequency of the PWM signal is 10MHz, and the period T is 100 ns.

Preferably, step three is as follows:

demodulating the received PWM signal, when receiving the rising edge of the RXD signal, starting sampling by the ADC, sampling by the ADC for 6 times in each pulse period T, wherein the sampling frequency is 60MHz, the sampling time interval is tau-16.67 ns, the pulse width corresponding to data1 is narrow, and the pulse width time T1 meets the following requirements: τ < T1<2 τ, the pulse width corresponding to data 0 is wide, and the pulse width time T2 satisfies: 3 τ < T2<4 τ; when the ADC samples to a high level H, the value of an internal counter of the FPGA is added with one (Count +1), when the ADC samples to a low level L, the internal counter of the FPGA stops counting, at the moment, the value (Count) of the counter is interpreted, namely the number of times that the ADC samples to the high level, and the value (Count) of the counter is reset when the rising edge of the next RXD1 signal arrives; the Data is 1 or 0 can be distinguished by distinguishing the numerical value of the counter; namely:

compared with the prior art, the invention has the following advantages:

1. the FPGA realizes Pulse Width Modulation (PWM) to realize laser communication, so that the anti-interference capability in the data transmission process is improved, and the transmission rate can reach 10 MB/S;

2. the problem of strict synchronization of clock signals of a transmitting system and a receiving system does not need to be considered in sampling Pulse Width Modulation (PWM), so that data transmission across clocks is more convenient;

3. the ADC is adopted to sample data, so that the accuracy of data transmission can be ensured when signals are demodulated, and the error rate is low.

Drawings

FIG. 1 is a system block diagram of a pulse width modulation system of the present invention;

in the figure: a transmitting device 1; a receiving device 2; a first Microcontroller (MCU) 3; a first transmitting end Field Programmable Gate Array (FPGA) 4; a laser drive circuit 5; a Laser Diode (LD) 6; an object 7; a receiving end PD array 8; a laser receiving circuit 9; an ADC 10; a second transmitting end field programmable logic gate array 11; a second microcontroller 12; an LCD display 13;

data1. transmitting end data; transmitting a modulated signal; pwm1. laser diode emitting pulses; pwm2. echo pulses after reflection by an object; RXD1, echo to-be-demodulated signal; RXD2. ADC sampling signal of receiving end; con1, controlling signals gated by PD array rows by a receiving end FPGA; con2, controlling signals gated by PD array columns by a receiving end FPGA; data2. receiving end data;

FIG. 2 illustrates the pulse modulation principle of a pulse width modulation method according to the present invention;

in the figure: DATA [ n ] the nth bit of the 8-bit DATA to be written;

FIG. 3 is a pulse transmission modulation circuit of a pulse width modulation system according to the present invention;

in the figure: DATA [7:0]Parallel data to be written (8 bits); transmitting a modulated signal; v_LDA laser diode bias voltage; PWM, emitting pulse signals by a laser diode;

FIG. 4 illustrates the pulse signal receiving principle of a PWM system according to the present invention;

in the figure: and PWM, receiving the pulse signals received by the PD array at the receiving end. S1, a receiving end PD array gates a first row of switches; s2, gating a switch of a second row by a PD array of the receiving end; s3, gating a switch in a third row by a PD array at the receiving end; s4, gating a fourth row of switches by the PD array of the receiving end; s5, gating a switch of a fifth row by a PD array at the receiving end; C1. the PD array of the receiving end gates the switch of the first column; C2. the PD array of the receiving end gates the switches of the second column; C3. the PD array of the receiving end gates the switch of the third column; C4. the PD array of the receiving end gates the switch of the fourth column; C5. the PD array of the receiving end gates the switch of the fifth column; RXD, converting the current signal into a voltage signal to be demodulated;

FIG. 5 illustrates the pulse demodulation principle of a pulse width modulation method according to the present invention;

in the figure: the high level duration of the pwm signal (representing logic 1); high level duration of the pwm signal (representing logic 0); τ. ADC sampling interval time; t. interval time for sending one bit of data; l, logic level low; H. the logic level is high; count the number of times that the ADC of the receiving end samples to a high level;

FIG. 6 is a pulse demodulation circuit of a pulse width modulation system according to the present invention;

in the figure: RXD, converting the current signal into a voltage signal to be demodulated; DATA [7:0]. parallel DATA (8 bits) output after demodulation.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Example 1

As shown in fig. 1, the present embodiment provides a pulse width modulation system, which includes a transmitting device 1, a receiving device 2, a Laser Diode (LD)6, and a photodiode array (PD) 8; the transmitting device 1 drives the LD6 to transmit a pulse laser PWM1 signal, the PWM1 signal transmitted by the LD6 is transmitted through a channel and generates an echo PWM2 signal after encountering an object 7, and the PWM2 signal is received by the PD array 8 and then sent to the receiving device 2, so that laser communication is realized.

The transmitting device 1 consists of a first Microcontroller (MCU)3, a first Field Programmable Gate Array (FPGA)4, a laser driving circuit 5 and a Laser Diode (LD) 6; the first microcontroller 3 decodes Data sources such as texts, pictures and audios, and sends the decoded Data1 to the first FPGA4, and a sending signal TXD of the first FPGA4 triggers the laser driving circuit 5 to drive the LD6 to generate pulsed laser.

The receiving device 2 consists of a laser receiving circuit 9, an ADC10, a second FPGA11, a second microcontroller 12 and an LCD display screen 13; the second FPGA11 sends out Con1 and Con2 signals to control row gating and column gating of the PD array 8, the PD in the PD array 8 receives pulsed light signals in a channel after being selected, the laser receiving circuit 9 converts the light signals received by the PD array 8 into electrical signals and outputs the electrical signals as RXD1 signals, the ADC10 converts the electrical signals RXD1 into digital RXD2 and sends the digital RXD2 into the second FPGA11, the second FPGA11 demodulates the received RXD2 Data and sends the demodulated Data2 into the second Microcontroller (MCU)12, and the second Microcontroller (MCU)12 encodes the Data2 Data to obtain text, picture, audio and other Data, and finally displays the Data on the LCD display 13.

Example 2

The embodiment provides a pulse width modulation method, which specifically comprises the following steps:

the method comprises the following steps:

the method is characterized in that Data1 (Data obtained by decoding Data sources such as texts, pictures and audios by the MCU 3) is converted into optical signals to be emitted, and the method mainly comprises the steps of modulating the Data1 and driving a Laser Diode (LD) 6. Fig. 2 is a modulation schematic block diagram. DATA [ n ]]For the nth bit of 8-bit data to be written, the nth bit of data is judged to be data1 or data 0 in the FPGA through a discriminator, the frequency of the PWM signal is 10MHz, the period T is 100ns, if the data is data1, the FPGA sends out a pulse signal with a narrow pulse width, the pulse width is T1 is 25ns, if the data is data 0, the FPGA sends out a pulse with a wide pulse width, the pulse width is T2 is 60ns, and the data corresponding to the PWM waveform in fig. 2 is 1001. Fig. 3 shows a pulse width modulation circuit, which is composed of a pulse generator (implemented in FPGA), a laser emitting circuit and an LD. FPGA as the master controller, parallel DATA DATA [7:0]]The DATA stored in FIFO inside FPGA is converted into serial DATA through parallel-to-serial module inside FPGA, and the parallel DATA DATA [7:0]]Each bit of the Pulse Width Modulation (PWM) signal can generate corresponding pulse wave after being modulated by a PWM modulation module in the FPGA, a modulation signal (TXD) generated by the PWM modulation module drives a grid driver of the laser emission circuit, the grid driver drives an MOS (metal oxide semiconductor) tube to control the conduction of an LD (laser diode) so as to realize pulse laser (PWM) output, V_LDIs the bias voltage of the LD. When the PWM signal waveform is at a high level, the Laser Diode (LD)6 emits light, and when the PWM signal waveform is at a low level, the Laser Diode (LD)6 does not emit light, thereby converting the Data1 into an optical signal to emit light.

Step two:

receiving the optical signal sent in the first step and converting the optical signal into a voltage signal, which is mainly completed by a PD array and a laser receiving circuit, as shown in fig. 4, which is a signal receiving schematic diagram, the laser receiving circuit is composed of a transimpedance amplifier (TIA) and an operational amplifier. The driving control circuit is arranged in the FPGA and comprises a scanning control module which is used for controlling the conduction of a PD in the PD array. When an optical signal irradiates on the PD array, the PD generates a photocurrent I, a transimpedance amplifier (TIA) in the laser receiving circuit converts the photocurrent I generated by the PD into a voltage V1, and the secondary amplifier further amplifies the voltage V1 to obtain a voltage V2, that is:

transimpedance R in FIG. 4₁200K Ω, input resistance R₂100 Ω, feedback resistance R₃The two-stage amplification factor is 2 ≧ 200 Ω, so that the laser receiving circuit converts the optical signal into a voltage signal (RXD) for output.

Step three:

and D, demodulating the voltage signal waveform in the step two. As shown in fig. 5, the demodulation principle of the pulse width signal is that a receiving end (RXD) receives 1001 binary data, the pulse width T1 corresponding to data1 is narrow, τ < T1<2 τ, the pulse width T2 corresponding to data 0 is wide, and 3 τ < T2<4 τ. The ADC starts sampling when the rising edge of the RXD signal arrives, the ADC samples for 6 times in each pulse period T, the sampling time interval is tau, when the ADC samples to a high level H, the value of the counter is added with one (Count +1), when the ADC samples to a low level L, the counter stops counting, at the moment, the value (Count) of the counter is interpreted, namely the number of times that the ADC samples to the high level, and the value (Count) of the counter is reset when the rising edge of the next RXD signal arrives. The Data is 1 or 0 can be distinguished by distinguishing the numerical value of the counter. Namely:

fig. 6 shows a PWM demodulation circuit, which uses an FPGA as a main controller (inside the FPGA), and includes a clock synchronization module, an ADC sampling module, a bit detection module, a sampling counting module, a discriminator, and a serial-to-parallel module. After the receiving circuit converts the optical signal into an electrical signal RXD, the RXD signal is subjected to clock synchronization through the clock synchronization module, the synchronized signal is sampled at a high speed by the ADC, the sampling counting module counts the high level times sampled by the ADC, the discriminator judges whether the DATA is DATA1 or DATA 0 according to the counting value of the sampling counting module, meanwhile, the bit detection module acquires the bit of the received 8-bit DATA in a counting mode, and the serial-parallel converter converts the serial DATA into parallel DATA (DATA [7:0]) and outputs the parallel DATA.

The above steps mainly focus on the signal processing processes at all levels in the system, and the preferred embodiment of the present invention is described in detail above with reference to the drawings, however, the present invention is not limited to the specific details in the above embodiment, and within the scope of the technical idea of the present invention, many simple modifications may be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.

In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.

Claims (7)

1. A pulse width modulation system is characterized by comprising a transmitting device (1), a receiving device (2), a laser diode LD (6) and a photodiode array PD (8); the emitting device (1) drives the LD (6) to emit pulse laser PWM (1) signals, the PWM (1) signals emitted by the LD (6) are transmitted through a channel, echo PWM (2) signals are generated after encountering an object (7), and the PWM (2) signals are received by the PD array (8) and then sent to the receiving device (2), so that laser communication is realized.

2. A pulse width modulation system according to claim 1, characterized in that the transmitting device 1 is composed of a first microcontroller MCU (3), a first field programmable gate array FPGA (4), a laser driving circuit (5) and a laser diode LD (6); the first microcontroller (3) decodes Data sources such as texts, pictures and audios, the decoded Data1 is sent into the first FPGA (4), and a sending signal TXD of the first FPGA (4) triggers the laser driving circuit (5) to drive the LD (6) to generate pulse laser.

3. A pulse width modulation system according to claim 1, characterized in that the receiving means (2) is composed of a laser receiving circuit (9), an ADC (10), a second FPGA (11) and a second microcontroller (12) and an LCD display screen (13); the second FPGA (11) sends out Con (1) and Con (2) signals to respectively control row gating and column gating of the PD array (8), a PD in the PD array (8) receives pulse light signals in a channel after being selected, a laser receiving circuit (9) converts the light signals received by the PD array (8) into electrical signals and then converts the electrical signals into RXD (1) signals to be output, an ADC (10) converts the electrical signals RXD (1) into digital quantities RXD (2) and then sends the digital quantities RXD (2) to the second FPGA (11), the second FPGA (11) demodulates the received RXD (2) Data, the demodulated Data2 is sent to a second microcontroller MCU (12), and the second microcontroller MCU (12) encodes the Data2 to obtain text, picture and audio Data which are finally displayed on an LCD display screen (13).

4. A pulse width modulation method is characterized by comprising the following steps:

the method comprises the following steps:

the microcontroller modulates the received data by a PWM (pulse-width modulation) module in the FPGA to generate corresponding pulse waves, a modulation signal TXD generated by the PWM module is used for driving a grid driver of the laser emitting circuit, and the grid driver drives an MOS (metal oxide semiconductor) tube and is used for controlling the conduction of a laser diode to realize pulse laser PWM output; when the waveform of the PWM signal is at a high level, the laser diode LD6 emits light, and when the waveform of the PWM signal is at a low level, the laser diode LD6 does not emit light, so that the Data1 is converted into an optical signal to be emitted;

step two:

receiving the optical signal sent in the first step and converting the optical signal into a voltage signal, specifically, when the optical signal is irradiated onto the PD array, the PD generates a photocurrent I, a transimpedance amplifier TIA in the laser receiving circuit converts the photocurrent I generated by the PD into a voltage V1, and a secondary amplifier AMP further amplifies the voltage V1 to obtain a voltage V2, that is:

the laser receiving circuit converts the optical signal into a voltage signal RXD and outputs the voltage signal RXD; wherein R is₁Is the feedback resistance of TIA₂Is an input resistance, R, of a two-stage amplifier AMP₃A feedback resistor which is a secondary amplifier AMP;

step three: the ADC converts the voltage signal into digital quantity and sends the digital quantity to the FPGA, the FPGA demodulates the received RXD data and sends the demodulated data to the microcontroller, and the microcontroller encodes the data to obtain data such as text, pictures, audio and the like, and finally the data is displayed on the LCD screen.

5. The method of claim 4, wherein step one is as follows:

modulating Data1, wherein the Data1 is parallel Data, after the Data are converted into serial Data in the FPGA, judging whether each bit of the Data is Data '1' or Data '0' bit by bit from the highest bit of the Data, and the FPGA sends out a PWM signal according to the judgment condition; in the case of data1, the FPGA transmits a pulse signal having a narrow pulse width of T1-25 ns, and in the case of data 0, the FPGA transmits a pulse signal having a wide pulse width of T2-60 ns, thereby realizing modulation in which data is converted into a PWM signal.

6. A pulse width modulation method according to claim 5, wherein the PWM signal has a frequency of 10MHz and a period T-100 ns.

7. A pulse width modulation method according to claim 4,

the third step is as follows:

demodulating the received PWM signal, when receiving the rising edge of the RXD signal, starting sampling by the ADC, sampling by the ADC for 6 times in each pulse period T, wherein the sampling frequency is 60MHz, the sampling time interval is tau-16.67 ns, the pulse width corresponding to data1 is narrow, and the pulse width time T1 meets the following requirements: τ < T1<2 τ, the pulse width corresponding to data 0 is wide, and the pulse width time T2 satisfies: 3 τ < T2<4 τ; when the ADC samples to a high level H, the value of an internal counter of the FPGA is added with one (Count +1), when the ADC samples to a low level L, the internal counter of the FPGA stops counting, at the moment, the value (Count) of the counter is interpreted, namely the number of times that the ADC samples to the high level, and the value (Count) of the counter is reset when the rising edge of the next RXD1 signal arrives; the Data is 1 or 0 can be distinguished by distinguishing the numerical value of the counter; namely:

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