CN113421820A - Oxidation annealing method - Google Patents

Oxidation annealing method Download PDF

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Publication number
CN113421820A
CN113421820A CN202110689226.7A CN202110689226A CN113421820A CN 113421820 A CN113421820 A CN 113421820A CN 202110689226 A CN202110689226 A CN 202110689226A CN 113421820 A CN113421820 A CN 113421820A
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temperature
reaction furnace
wafer
reducing
oxidation annealing
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朱泽中
张超
王成森
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Jiejie Semiconductor Co ltd
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Jiejie Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Formation Of Insulating Films (AREA)

Abstract

The application provides an oxidation annealing method, and relates to the technical field of semiconductor annealing processes. Firstly, placing a wafer to be processed in a reaction furnace at a low temperature; then introducing oxygen, raising the temperature in the reaction furnace to a threshold temperature and maintaining for a first preset time; and finally, cooling the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is recovered to a low temperature so as to separate out the internal defects of the wafer to be processed to the surface in the oxidation annealing process. The oxidation annealing method has the advantages that the lattice defects in the wafer can be repaired, and the stress of the wafer is improved.

Description

Oxidation annealing method
Technical Field
The application relates to the technical field of semiconductor annealing processes, in particular to an oxidation annealing method.
Background
The conventional wafer manufacturing process includes a process step of oxidation annealing, which is generally performed after the wafer is subjected to impurity diffusion or after a damaged layer appears on the surface of the wafer, and aims to repair a part of lattice defects and precipitate a part of impurity defects in the wafer at a high temperature, release a part of stress of a chip, and grow an oxide layer with a certain film thickness on the surface to prepare for the subsequent process step.
As the N + diffusion region of the wafer is generally diffused by doping phosphorus, the diffusion temperature is generally about 1200 ℃, the normal oxidation annealing mode adopts the high temperature less than 1200 ℃ to carry out the oxidation annealing operation, and the influence of the over-high temperature on the concentration and the depth of the phosphorus diffusion is avoided. The oxidation annealing step is not considered in the wafer manufacturing process, generally, the thickness of the oxide layer after the furnace is obtained to meet the requirement, the temperature rise and fall rate of the temperature in the operation process is not required to be too large, the shorter the time is, the better the time is, but the improvement of the chip stress and the crystal lattice defect of the wafer is not really significant.
In summary, the prior art has the problem that the effect of the oxidation annealing process on the improvement of the stress of the wafer and the improvement of the lattice defect of the wafer is small.
Disclosure of Invention
The present application aims to provide an oxidation annealing method to solve the problem that the oxidation annealing process in the prior art has a small effect on improving the stress of a wafer and improving the lattice defect of the wafer.
In order to solve the above problems, the present application provides an oxidation annealing method including:
placing a wafer to be processed in a reaction furnace at a low temperature;
introducing oxygen, raising the temperature in the reaction furnace to a threshold temperature and maintaining for a first preset time;
and reducing the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is recovered to the low temperature so as to separate out the internal defects of the wafer to be processed to the surface in the oxidation annealing process.
Optionally, the step of introducing oxygen to raise the temperature in the reaction furnace to a threshold temperature and maintaining the temperature for a first preset time includes:
and introducing oxygen, raising the temperature in the reaction furnace to over 1200 ℃ and maintaining the temperature for 1-2H.
Optionally, the step of introducing oxygen to raise the temperature in the reaction furnace to over 1200 ℃ and maintain 1-2H comprises:
and introducing 1-5 LPM of oxygen, and simultaneously raising the temperature in the reaction furnace to over 1200-1250 ℃ and maintaining 1-2H.
Optionally, the step of raising the temperature inside the reaction furnace to a threshold temperature and maintaining the temperature for a first preset time comprises:
and raising the temperature of the reaction furnace to a threshold temperature at a speed of 6-10 ℃/min and maintaining for a first preset time.
Optionally, the threshold temperature is greater than 1200 ℃, and before the step of reducing the temperature in the reaction furnace at a rate less than or equal to 1 ℃/min, the method further comprises:
reducing the temperature in the reaction furnace to 900-1200 ℃;
and introducing wet oxygen, and maintaining for a second preset time to grow an oxide film on the wafer to be processed.
Optionally, before the step of reducing the temperature in the reaction furnace to 900-:
determining target temperature and target time according to the target thickness of the oxide film, wherein the target temperature and the target time are positively correlated with the target thickness, and the target temperature is any one value of 900-1200 ℃;
the step of reducing the temperature in the reaction furnace to 900-1200 ℃ comprises the following steps:
reducing the temperature within the reaction furnace to the target temperature;
the step of introducing wet oxygen and maintaining for a second preset time comprises the following steps:
and introducing wet oxygen, and maintaining the target time.
Optionally, the step of reducing the temperature in the reaction furnace to 900-1200 ℃ comprises:
the temperature in the reaction furnace is reduced to 900-1200 ℃ at a rate of less than or equal to 1 ℃/min.
Optionally, the step of reducing the temperature in the reaction furnace to 900-1200 ℃ comprises:
reducing the temperature in the reaction furnace to 900-1200 ℃ according to a preset rate, wherein the preset rate is less than or equal to 1 ℃/min;
the step of reducing the temperature in the reaction furnace at a rate of less than or equal to 1 ℃/min until the temperature in the reaction furnace returns to the low temperature comprises:
and reducing the temperature in the reaction furnace according to the preset rate until the temperature in the reaction furnace is restored to the low temperature.
Optionally, the step of reducing the temperature in the reaction furnace at a rate of less than or equal to 1 ℃/min until the temperature in the reaction furnace returns to the low temperature comprises:
and introducing dry oxygen, and reducing the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is restored to the low temperature.
Optionally, the step of placing the wafer to be processed in the reaction furnace at a low temperature comprises:
and maintaining the temperature in the reaction furnace to 400-600 ℃, and placing the wafer to be processed in the reaction furnace.
Compared with the prior art, the method has the following beneficial effects:
the application provides an oxidation annealing method, firstly, a wafer to be processed is placed in a reaction furnace at a low temperature; then introducing oxygen, raising the temperature in the reaction furnace to a threshold temperature and maintaining for a first preset time; and finally, cooling the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is recovered to a low temperature so as to separate out the internal defects of the wafer to be processed to the surface in the oxidation annealing process. Because the oxidation annealing method provided by the application adopts the ultra-slow cooling mode of less than or equal to 1 ℃/min to reduce the temperature in the furnace, the defects in the wafer can be gradually separated out to the surface of the wafer in the process, meanwhile, the stress resistance of the wafer is gradually improved in the slow cooling process, and finally, the oxidation annealing of the wafer is completed, so that the effects of repairing the lattice defects in the wafer and improving the stress of the wafer are achieved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a graph of time versus temperature for an oxidation annealing process of the prior art.
Fig. 2 is an exemplary flowchart of an oxidation annealing method provided in an embodiment of the present application.
Fig. 3 is a time-temperature diagram of an oxidation annealing method according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
As mentioned in the background, the prior art does not have much demand on the temperature increase and decrease rate during the operation, and it is generally desirable that the time is as short as possible, but it does not actually play a great role in the increase of the stress of the wafer and the improvement of the lattice defect of the wafer.
For example, fig. 1 is a graph of time versus temperature for a prior art oxidation annealing process. Firstly, placing a wafer to be processed into a reaction furnace under a low temperature condition (400-600 ℃), then raising the temperature in the reaction furnace according to a temperature raising slope of less than 6 ℃/min on the basis of introducing dry oxygen until the temperature is raised to 900-1200 ℃, introducing a proper amount of wet oxygen and maintaining the temperature for a period of time, wherein the time can be defined as SIO which needs to grow2The thickness of the film. Then introducing dry oxygen and reducing the temperature to 400-600 ℃ according to a temperature reduction slope of more than 1 ℃/min.
As the N + diffusion region of the wafer is generally diffused by doping phosphorus, the diffusion temperature is generally about 1200 ℃, the normal oxidation annealing mode adopts the high temperature less than 1200 ℃ to carry out the oxidation annealing operation, and the influence of the over-high temperature on the concentration and the depth of the phosphorus diffusion is avoided. The oxidation annealing step is not taken a great deal of attention in the wafer manufacturing process, generally, the thickness of the oxide layer after the furnace is obtained can meet the requirement, the temperature raising and lowering rate of the temperature in the operation process is not too high, and the shorter the time is, the better the time is.
Therefore, it can be understood that although the oxidation annealing method shown in fig. 1 can rapidly perform the oxidation annealing, it does not substantially contribute to the increase of the stress of the wafer and the improvement of the lattice defect of the wafer.
In view of the above, in order to solve the above problems, the present application provides an oxidation annealing method, which performs an operation in an ultra-slow cooling annealing manner, so as to achieve the purposes of repairing lattice defects in a wafer and increasing wafer stress.
The oxidation annealing method described in the present application is exemplified below:
as an alternative implementation, referring to fig. 2 and fig. 3, the oxidation annealing method includes:
s102, placing the wafer to be processed in a reaction furnace at low temperature.
And S104, introducing oxygen, raising the temperature in the reaction furnace to a threshold temperature and maintaining the temperature for a first preset time.
And S106, cooling the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace returns to low temperature, so that the internal defects of the wafer to be processed are separated out to the surface in the oxidation annealing process.
Wherein, the temperature of the furnace is gradually reduced to the temperature of the furnace by using an ultra-slow cooling mode of less than or equal to 1 ℃/min, so that the internal defects of the wafer are gradually separated out to the surface of the wafer, and meanwhile, the stress resistance of the wafer is gradually improved in the slow cooling process, and finally, the oxidation annealing of the wafer is completed. By the implementation mode, the effect on improving the stress of the chip and the crystal lattice defect of the wafer is better, and meanwhile, the toughness of the chip can be greatly improved.
Optionally, the step of S102 includes:
and maintaining the temperature in the reaction furnace to 400-600 ℃, and placing the wafer to be processed in the reaction furnace.
Namely, the low temperature is 400-600 ℃.
The step of S104 includes:
and introducing oxygen, raising the temperature in the reaction furnace to over 1200 ℃ and maintaining the temperature for 1-2H.
In the application, the temperature is raised to over 1200 ℃ by adopting a relatively rapid heating method, 1-2H is maintained, and the wafer is enabled to recombine the inner cells and activate and improve partial lattice defects at the high temperature. Meanwhile, the method of full-speed cooling is matched, so that the internal defects of the wafer are gradually separated out to the surface of the wafer, and the improvement effect of the crystal lattice defects is better.
It should be noted that, since the typical wafer diffusion N + region employs phosphorus-doped diffusion, the diffusion temperature is generally about 1200 ℃, so the high temperature cannot be too high, and the applicant finds that the high temperature oxidation annealing operation at 1200-.
On this basis, the step of S104 actually includes:
and introducing 1-5 LPM of oxygen, and simultaneously raising the temperature in the reaction furnace to 1200-1250 ℃ and maintaining 1-2H.
Dry oxygen is introduced at the temperature of 1200-1250 ℃ to improve the recombination of unit cells and the repair of lattice defects of the semiconductor material. Meanwhile, under the condition that the N + region is formed to a certain depth, the N + junction depth is not influenced by selecting the high temperature of 1200-1250 ℃ to carry out the oxidation annealing operation of 1-2H.
In addition, in order to improve the effect of the lattice defect, it is necessary to rapidly raise the temperature in the reaction furnace to 1200-1250 ℃ after the wafer to be processed is placed in the reaction furnace.
On this basis, as one implementation manner, S104 includes:
and raising the temperature of the reaction furnace to a threshold temperature at the speed of 6-10 ℃/min and maintaining for a first preset time.
It should be noted that, by means of rapid temperature rise, on one hand, the wafer to be processed can be in a high temperature environment as soon as possible, so that the semiconductor material crystal cell recombination and the crystal lattice defect repair improvement are realized, and the effect is better. On the other hand, the time consumption of oxidation annealing is shortened by the rapid heating mode, and the efficiency of the oxidation annealing is improved.
It should be noted that, in an alternative implementation, an oxide film (SIO) is generated on the surface of the wafer to be processed2The film) has no requirement, on the basis, dry oxygen can be directly introduced at the high temperature of 1200-1250 ℃ after the temperature is rapidly increased to 1200-1250 ℃, and the effect of impurity separation and stress improvement can be achieved in a slow cooling mode of less than or equal to 1 ℃/min.
In another alternative implementation, an oxide film (SIO) is grown on the surface of a wafer to be processed2Film) has certain thickness requirements, then on this basis,before S106, the method further includes:
s1052, reducing the temperature in the reaction furnace to 900-1200 ℃.
S1053, introducing wet oxygen, and maintaining for a second preset time to grow an oxide film on the wafer to be processed.
Optionally, before S1052, the method further comprises:
s1051, determining the target temperature and the target time according to the target thickness of the oxide film, wherein the target temperature and the target time are positively correlated with the target thickness, and the target temperature is any value of 900-1200 ℃;
s1052 includes:
reducing the temperature in the reaction furnace to a target temperature;
s1053 includes:
introducing wet oxygen and maintaining the target time.
Further, S1052 further includes:
the temperature in the reaction furnace is reduced to 900-1200 ℃ at a rate of less than or equal to 1 ℃/min.
As an implementation manner, taking the rate as a preset rate, the step of S106 may include:
and (4) cooling the temperature in the reaction furnace at a preset rate until the temperature in the reaction furnace returns to a low temperature.
In other words, the annealing temperature is reduced to about 1000-2And (3) a membrane.
In conclusion, the oxidation annealing process of the present application innovatively adopts the high temperature of 1200-1250 ℃ and simultaneously operates in cooperation with the annealing mode of ultra-slow temperature reduction, thereby achieving the purposes of repairing the lattice defects in the wafer and improving the stress of the wafer.
The applicant verifies that compared with the conventional production under normal process conditions, the oxidation annealing process of the invention is arranged on the same high-voltage rectifier diode, and the product operated by the invention has the following advantages:
1. the reverse voltage withstanding level is improved by about 5% -10%, and the voltage concentration of the single wafer is better.
2. Along with the improvement of the impurity defect in the wafer, the reverse leakage current level at normal temperature is obviously reduced to about half of the original level, and the reliability of the device during working is improved.
3. The wafer has better toughness, so that the wafer has higher whole wafer yield in the operation process of the subsequent step.
In summary, the present application provides an oxidation annealing method, first placing a wafer to be processed in a reaction furnace at a low temperature; then introducing oxygen, raising the temperature in the reaction furnace to a threshold temperature and maintaining for a first preset time; and finally, cooling the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is recovered to a low temperature so as to separate out the internal defects of the wafer to be processed to the surface in the oxidation annealing process. Because the oxidation annealing method provided by the application adopts the ultra-slow cooling mode of less than or equal to 1 ℃/min to reduce the temperature in the furnace, the defects in the wafer can be gradually separated out to the surface of the wafer in the process, meanwhile, the stress resistance of the wafer is gradually improved in the slow cooling process, and finally, the oxidation annealing of the wafer is completed, so that the effects of repairing the lattice defects in the wafer and improving the stress of the wafer are achieved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. An oxidation annealing method, characterized in that the method comprises:
placing a wafer to be processed in a reaction furnace at a low temperature;
introducing oxygen, raising the temperature in the reaction furnace to a threshold temperature and maintaining for a first preset time;
and reducing the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is recovered to the low temperature so as to separate out the internal defects of the wafer to be processed to the surface in the oxidation annealing process.
2. The oxidation annealing method of claim 1, wherein the step of introducing oxygen to raise the temperature in the reaction furnace to a threshold temperature for a first predetermined time comprises:
and introducing oxygen, raising the temperature in the reaction furnace to over 1200 ℃ and maintaining the temperature for 1-2H.
3. The oxidation annealing method according to claim 2, wherein the step of introducing oxygen to raise the temperature in the reaction furnace to 1200 ℃ or higher and maintaining the temperature for 1 to 2H comprises:
and introducing 1-5 LPM of oxygen, and simultaneously raising the temperature in the reaction furnace to 1200-1250 ℃ and maintaining 1-2H.
4. The oxidizing annealing method according to any one of claims 1 to 3, wherein the step of raising the temperature inside the reaction furnace to a threshold temperature for a first preset time comprises:
and raising the temperature of the reaction furnace to a threshold temperature at a speed of 6-10 ℃/min and maintaining for a first preset time.
5. The oxidation annealing method of claim 1, wherein the threshold temperature is greater than 1200 ℃, and prior to the step of reducing the temperature within the reaction furnace at a rate of less than or equal to 1 ℃/min, the method further comprises:
reducing the temperature in the reaction furnace to 900-1200 ℃;
and introducing wet oxygen, and maintaining for a second preset time to grow an oxide film on the wafer to be processed.
6. The oxidation annealing method of claim 5, wherein before the step of reducing the temperature in the reaction furnace to 900-1200 ℃, the method further comprises:
determining target temperature and target time according to the target thickness of the oxide film, wherein the target temperature and the target time are positively correlated with the target thickness, and the target temperature is any one value of 900-1200 ℃;
the step of reducing the temperature in the reaction furnace to 900-1200 ℃ comprises the following steps:
reducing the temperature within the reaction furnace to the target temperature;
the step of introducing wet oxygen and maintaining for a second preset time comprises the following steps:
and introducing wet oxygen, and maintaining the target time.
7. The oxidation annealing method of claim 5, wherein the step of reducing the temperature inside the reaction furnace to 900-1200 ℃ comprises:
the temperature in the reaction furnace is reduced to 900-1200 ℃ at a rate of less than or equal to 1 ℃/min.
8. The oxidation annealing method of claim 5, wherein the step of reducing the temperature inside the reaction furnace to 900-1200 ℃ comprises:
reducing the temperature in the reaction furnace to 900-1200 ℃ according to a preset rate, wherein the preset rate is less than or equal to 1 ℃/min;
the step of reducing the temperature in the reaction furnace at a rate of less than or equal to 1 ℃/min until the temperature in the reaction furnace returns to the low temperature comprises:
and reducing the temperature in the reaction furnace according to the preset rate until the temperature in the reaction furnace is restored to the low temperature.
9. The oxidation annealing method according to claim 1, wherein the step of lowering the temperature in the reaction furnace at a rate of 1 ℃/min or less until the temperature in the reaction furnace returns to the low temperature comprises:
and introducing dry oxygen, and reducing the temperature in the reaction furnace at a speed of less than or equal to 1 ℃/min until the temperature in the reaction furnace is restored to the low temperature.
10. The oxidation annealing method according to claim 1, wherein the step of placing the wafer to be processed in the reaction furnace at a low temperature comprises:
and maintaining the temperature in the reaction furnace to 400-600 ℃, and placing the wafer to be processed in the reaction furnace.
CN202110689226.7A 2021-06-22 2021-06-22 Oxidation annealing method Pending CN113421820A (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990005873A (en) * 1997-06-30 1999-01-25 김영환 Gate oxide film formation method of a semiconductor device
US6339022B1 (en) * 1999-12-30 2002-01-15 International Business Machines Corporation Method of annealing copper metallurgy
US20040097102A1 (en) * 2002-11-19 2004-05-20 Young-Hee Mun Annealed wafer and manufacturing method thereof
CN101067997A (en) * 2007-04-20 2007-11-07 中国电子科技集团公司第四十八研究所 Method for producing ion implantation thick film SOI wafer material
CN104637801A (en) * 2015-01-30 2015-05-20 株洲南车时代电气股份有限公司 Method for preparing SiC MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) grid oxide layer
CN104658903A (en) * 2015-01-30 2015-05-27 株洲南车时代电气股份有限公司 Method for preparing SiC MOSFET gate oxide layer
CN105200526A (en) * 2015-10-14 2015-12-30 盐城工学院 Gallium oxide wafer stress relieving annealing method
CN112928016A (en) * 2021-02-01 2021-06-08 广东省大湾区集成电路与系统应用研究院 Rapid annealing process for wafer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990005873A (en) * 1997-06-30 1999-01-25 김영환 Gate oxide film formation method of a semiconductor device
US6339022B1 (en) * 1999-12-30 2002-01-15 International Business Machines Corporation Method of annealing copper metallurgy
US20040097102A1 (en) * 2002-11-19 2004-05-20 Young-Hee Mun Annealed wafer and manufacturing method thereof
CN101067997A (en) * 2007-04-20 2007-11-07 中国电子科技集团公司第四十八研究所 Method for producing ion implantation thick film SOI wafer material
CN104637801A (en) * 2015-01-30 2015-05-20 株洲南车时代电气股份有限公司 Method for preparing SiC MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) grid oxide layer
CN104658903A (en) * 2015-01-30 2015-05-27 株洲南车时代电气股份有限公司 Method for preparing SiC MOSFET gate oxide layer
CN105200526A (en) * 2015-10-14 2015-12-30 盐城工学院 Gallium oxide wafer stress relieving annealing method
CN112928016A (en) * 2021-02-01 2021-06-08 广东省大湾区集成电路与系统应用研究院 Rapid annealing process for wafer

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