CN113421523A - Display module and display device - Google Patents
Display module and display device Download PDFInfo
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- CN113421523A CN113421523A CN202110676406.1A CN202110676406A CN113421523A CN 113421523 A CN113421523 A CN 113421523A CN 202110676406 A CN202110676406 A CN 202110676406A CN 113421523 A CN113421523 A CN 113421523A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The invention provides a display module and a display device. The display module comprises a driving module and a display panel, wherein the display panel comprises a plurality of rows of data lines, a plurality of rows of B-row pixel circuits and an N-row load circuit; b and N are both positive integers; the load circuit comprises a plurality of columns of load sub-circuits; the driving module comprises a multi-stage driving circuit and an N-stage pseudo driving circuit; the nth row load circuit comprises B columns of load sub-circuits; the b column load sub-circuit comprises an n row b column switch circuit and an n row b column tank circuit; n is a positive integer less than or equal to N, B is a positive integer less than or equal to B; and the nth row and nth column switch circuit is used for controlling the connection or disconnection between the nth column data line and the nth row and nth column energy storage circuit under the control of a signal provided by the output end of the nth stage pseudo driving circuit. The invention improves the defect of dark bottom when the display panel displays.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display module and a display device.
Background
In order to improve the afterimage defect of an OLED (organic light emitting diode) display product, a driving signal (for example, a gate driving signal) having at least two pulses is introduced, and the plate of the storage capacitor is reset multiple times by an initial voltage Vinit within one frame time, so as to reduce the afterimage defect. In the display stage, a row of data voltages are written into the pixel circuits in row a at the same time (a is an integer greater than 1), but when the last rows of pixel circuits included in the display panel are scanned, a row of data voltages are written into the pixel circuits in row C at the same time (C is a positive integer, and C is smaller than a), and the data voltages written into the corresponding rows are greater than a normal value, so that the brightness is low, and the problem that the bottom of the display panel is dark when displaying is caused.
Disclosure of Invention
The invention mainly aims to provide a display module and a display device, which can be used for improving the defect that the bottom of a display panel is dark when the display panel in the prior art displays.
The embodiment of the invention provides a display module, which comprises a driving module and a display panel, wherein the display panel comprises a plurality of rows of data lines, a plurality of rows of B-row pixel circuits and an N-row load circuit; the data lines are electrically connected with corresponding column pixel circuits included in the display panel; b and N are both positive integers; the load circuit comprises a plurality of columns of load sub-circuits;
the driving module comprises a multi-stage driving circuit and an N-stage pseudo driving circuit, and the driving circuit is used for providing driving signals for the pixel circuits of the corresponding row included in the display panel;
the input end of each stage of pseudo driving circuit except the first stage of pseudo driving circuit in the driving module is electrically connected with the output end of the adjacent previous stage of pseudo driving circuit, and the output end of the adjacent previous stage of pseudo driving circuit provides corresponding input signals for the input end of each stage of pseudo driving circuit;
the nth row load circuit comprises B columns of load sub-circuits;
the b column load sub-circuit comprises an n row b column switch circuit and an n row b column tank circuit; n is a positive integer less than or equal to N, B is a positive integer less than or equal to B;
the control end of the nth row and the nth column of switch circuits is electrically connected with the output end of the nth-stage pseudo drive circuit, the first end of the nth row and the nth column of switch circuits is electrically connected with the nth column of data line, and the second end of the nth row and the nth column of switch circuits is electrically connected with the nth row and the nth column of energy storage circuit; the nth row and nth column switch circuit is used for controlling the connection or disconnection between the nth column data line and the nth row and nth column energy storage circuit under the control of a signal provided by an output end of the nth stage pseudo driving circuit;
and the nth row and the mth column of the energy storage circuit are used for storing electric energy.
Optionally, the nth row and column switch circuit includes an nth row and column switch transistor, and the nth row and column tank circuit includes an nth row and column capacitor;
a control electrode of the nth row and the nth column of switch transistors is electrically connected with an output end of the nth-stage pseudo driving circuit, a first electrode of the nth row and the nth column of switch transistors is electrically connected with the nth column of data line, and a second electrode of the nth row and the nth column of switch transistors is electrically connected with a first polar plate of the nth row and the nth column of capacitors;
and the second polar plate of the nth row and the nth column capacitor is electrically connected with a first voltage end.
Optionally, the pixel circuit includes a storage capacitor; the capacitance value of the nth row and the mth column capacitor is the same as that of the storage capacitor.
Optionally, the pixel circuit further includes a light emitting element, a driving circuit, a light emission control circuit, a data writing circuit, a compensation control circuit, and a first reset circuit;
the first reset circuit is respectively electrically connected with a reset control line, an initial voltage line and a first plate of the storage capacitor, and is used for writing the initial voltage provided by the initial voltage line into the first plate of the storage capacitor under the control of a reset control signal provided by the reset control line;
the second electrode plate of the storage capacitor is electrically connected with the first voltage end;
the data writing circuit is respectively electrically connected with the corresponding row grid line, the corresponding column data line and the first end of the driving circuit and is used for supplying data voltage on the corresponding column data line to the first end of the driving circuit under the control of a grid driving signal supplied by the corresponding row grid line;
the compensation control circuit is respectively electrically connected with the corresponding row of grid lines, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the grid driving signal provided by the corresponding row of grid lines;
the light-emitting control circuit is respectively electrically connected with a light-emitting control line, the first voltage end, the first end of the driving circuit, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the first voltage end and the first end of the driving circuit and controlling the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control line;
and the second pole of the light-emitting element is electrically connected with the second voltage end.
Optionally, the pixel circuit further includes a second reset circuit;
the second reset circuit is electrically connected to the reset control line of the next row adjacent thereto, the initial voltage terminal, and the first electrode of the light emitting element, respectively, and is configured to write the initial voltage to the first electrode of the light emitting element under control of a reset control signal provided by the reset control line of the next row adjacent thereto.
Optionally, the display panel includes an effective display area and a peripheral area, the pixel circuit is disposed in the effective display area, and the load circuit is disposed in the peripheral area.
Optionally, the structure of the dummy driving circuit is the same as that of the driving circuit.
Optionally, the driving circuit is a gate driving circuit, and is configured to provide a corresponding gate driving signal to the pixel circuit of the corresponding row through the output terminal.
Optionally, in a frame time, the input signal received by the input end of the driving circuit includes M pulses, M is an integer greater than 1, and N is greater than or equal to M + 1.
The embodiment of the invention also provides a display device which comprises the display module.
According to the display module and the display device, the N-level pseudo driving circuit and the N-row load circuit are added, the pseudo driving circuit controls the corresponding row load circuit to share data voltage written by the pixel circuits of several rows, and the defect that the bottom of the display panel is dark when the display panel displays is improved.
Drawings
FIG. 1 is a diagram of a display module according to an embodiment of the present invention;
FIG. 2 is a block diagram of an embodiment of a b-th column load sub-circuit included in an n-th column load circuit of a display module according to the present invention;
FIG. 3 is a circuit diagram of one embodiment of a b-th column load sub-circuit included in the n-th row load circuit;
FIG. 4 is a diagram of a pixel circuit of a display panel of a display module according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of one embodiment of a pixel circuit;
FIG. 6 is a timing diagram of the operation of the embodiment of the pixel circuit shown in FIG. 5;
fig. 7 is a waveform diagram of a signal output from Gout1, a signal output from Gout2, a signal output from Gout3, a signal output from Gout4, a signal output from Gout5, a signal output from Gout6, a signal output from Dummy1, a signal output from Dummy2, a signal output from Dummy3, and a signal output from Dummy 4.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The display module comprises a driving module and a display panel, wherein the display panel comprises a plurality of columns of data lines, a plurality of rows of B-column pixel circuits and an N-row load circuit; the data lines are electrically connected with corresponding column pixel circuits included in the display panel; b and N are both positive integers; the load circuit comprises a plurality of columns of load sub-circuits;
the driving module comprises a multi-stage driving circuit and an N-stage pseudo driving circuit, and the driving circuit is used for providing driving signals for the pixel circuits of the corresponding row included in the display panel;
the input end of each stage of pseudo driving circuit except the first stage of pseudo driving circuit in the driving module is electrically connected with the output end of the adjacent previous stage of pseudo driving circuit, and the output end of the adjacent previous stage of pseudo driving circuit provides corresponding input signals for the input end of each stage of pseudo driving circuit;
the nth row load circuit comprises B columns of load sub-circuits;
the b column load sub-circuit comprises an n row b column switch circuit and an n row b column tank circuit; n is a positive integer less than or equal to N, B is a positive integer less than or equal to B;
the control end of the nth row and the nth column of switch circuits is electrically connected with the output end of the nth-stage pseudo drive circuit, the first end of the nth row and the nth column of switch circuits is electrically connected with the nth column of data line, and the second end of the nth row and the nth column of switch circuits is electrically connected with the nth row and the nth column of energy storage circuit; the nth row and nth column switch circuit is used for controlling the connection or disconnection between the nth column data line and the nth row and nth column energy storage circuit under the control of a signal provided by an output end of the nth stage pseudo driving circuit;
and the nth row and the mth column of the energy storage circuit are used for storing electric energy.
The embodiment of the invention adds the N-level pseudo driving circuit and the N-row load circuit, controls the corresponding row load circuit to share the data voltage written by the pixel circuits of several rows after the pseudo driving circuit, and improves the defect of dark bottom when the display panel displays.
In the embodiment of the present invention, the structure of the dummy driving circuit may be the same as the structure of the driving circuit, but is not limited thereto.
As shown in fig. 1, the driving module denoted by reference numeral S0 is a last stage driving circuit included in the driving module, and the driving module according to the embodiment of the present invention includes a first stage dummy driving circuit S1, a second stage dummy driving circuit S2, a third dummy driving circuit S3, and a fourth dummy driving circuit S4; the display panel further includes a first row load circuit F1, a second row load circuit F2, a third row load circuit F3, and a fourth row load circuit F4;
the output end of the S0 is electrically connected with the input end of the first-stage pseudo driving circuit S1;
the output end of the S1 is electrically connected with the input end of the S2; the output end of the S2 is electrically connected with the input end of the S3; the output end of the S3 is electrically connected with the input end of the S4; an output terminal of S0 is electrically connected to a last row of pixel circuits P0 included in the display panel;
the output end of S1 is electrically connected with F1; the output end of S2 is electrically connected with F2; the output end of S3 is electrically connected with F3; the output terminal of S4 is electrically connected to F4.
In a specific implementation, the display panel may include an effective display area and a peripheral area, the display panel includes B columns of pixel circuits and B columns of data lines disposed in the effective display area, where B is a positive integer; the b-th column data line is electrically connected with the b-th column pixel circuit;
the display panel also comprises N rows of load circuits arranged in the peripheral area; the nth row load circuit comprises B columns of load sub-circuits;
as shown in fig. 2, the b-th column load sub-circuit included in the n-th row load circuit may include an n-th row and b-th column switch circuit 41 and an n-th row and b-th column tank circuit 42; n is a positive integer less than or equal to N, B is a positive integer less than or equal to B;
the control end of the nth row and nth column switch circuit 41 is electrically connected with the output end of the nth stage pseudo drive circuit 40, the first end of the nth row and nth column switch circuit 41 is electrically connected with the nth column data line Db, and the second end of the nth row and nth column switch circuit 41 is electrically connected with the nth row and nth column energy storage circuit 42;
the nth row and column switch circuit 41 is used for controlling the connection or disconnection between the b column data line Db and the nth row and column energy storage circuit 42 under the control of a signal provided by an output end of the nth stage pseudo driving circuit 40;
the nth row and the b column of the energy storage circuit 42 are used for storing electric energy.
When the nth stage pseudo driving circuit 40 provides an effective driving signal through its output terminal, the nth row and column switch circuit 41 controls the communication between the column data line Db and the nth row and column tank circuit 42 to simulate the load of the pixel circuit in the effective display area.
The valid drive signals refer to: and the drive signal can make the nth row and the mth column switch circuit conductive. For example, when the transistor connected to the gate line included in the pixel circuit is a p-type transistor, the transistor included in the n-th row/b-th column switch circuit is also a p-type transistor, and the potential of the effective drive signal is a low voltage.
Optionally, the nth row and column switch circuit includes an nth row and column switch transistor, and the nth row and column tank circuit includes an nth row and column capacitor;
a control electrode of the nth row and the nth column of switch transistors is electrically connected with an output end of the nth-stage pseudo driving circuit, a first electrode of the nth row and the nth column of switch transistors is electrically connected with the nth column of data line, and a second electrode of the nth row and the nth column of switch transistors is electrically connected with a first polar plate of the nth row and the nth column of capacitors;
and the second polar plate of the nth row and the nth column capacitor is electrically connected with a first voltage end.
In the embodiment of the present invention, the first voltage terminal may be a high voltage terminal, but is not limited thereto.
As shown in fig. 3, on the basis of the embodiment of the load sub-circuit shown in fig. 2, the nth row and column switch circuit 41 includes an nth row and column switch transistor Tnb, and the nth row and column tank circuit 42 includes an nth row and column capacitor Cnb;
the gate of the nth row and column switch transistor Tnb is electrically connected to the output terminal of the nth stage pseudo driving circuit 40, the source of the nth row and column switch transistor Tnb is electrically connected to the b-th column data line Db, and the drain of the nth row and column switch transistor Tnb is electrically connected to the first plate of the nth row and column capacitor Cnb;
the second plate of the nth row and the mth column capacitor Cnb is electrically connected to the high voltage terminal VDD.
In the embodiment shown in fig. 3, Tnb is a p-type tft, and the first voltage terminal is the high voltage terminal VDD.
In operation, when the output terminal of the nth stage pseudo driver circuit 40 outputs a low voltage signal, Tnb is turned on to connect the b-th column data line Db to the first plate of the n-th row b-th column capacitor Cnb according to the embodiment of the present invention as shown in fig. 3.
Preferably, the pixel circuit includes a storage capacitor; the capacitance value of the nth row and the mth column capacitor and the capacitance value of the storage capacitor can be the same so as to simulate the load in the pixel circuit in the effective display area.
In an embodiment of the present invention, the driving circuit may be a gate driving circuit, and is configured to provide a corresponding gate driving signal to the pixel circuit of the corresponding row through the output terminal.
As shown in fig. 4, the display panel includes one embodiment of a pixel circuit including a light emitting element 40, a driving circuit 41, a light emission control circuit 42, a data writing circuit 43, a compensation control circuit 44, and a first reset circuit 45;
the first Reset circuit 45 is electrically connected to the Reset control line Reset, the initial voltage line and the first plate of the storage capacitor Cst, respectively, and is configured to write the initial voltage Vinit provided by the initial voltage line into the first plate of the storage capacitor Cst under the control of a Reset control signal provided by the Reset control line Reset;
the second plate of the storage capacitor Cst is electrically connected to the first voltage terminal V1;
the data writing circuit 43 is electrically connected to the corresponding row Gate line Gate, the corresponding column data line D0 and the first end of the driving circuit 41, respectively, and is configured to provide the data voltage Vdata on the corresponding column data line D0 to the first end of the driving circuit 41 under the control of the Gate driving signal provided by the corresponding row Gate line Gate;
the compensation control circuit 44 is electrically connected to the corresponding row Gate line Gate, the control end of the driving circuit 41 and the second end of the driving circuit 41, respectively, and is configured to control the connection between the control end of the driving circuit 41 and the second end of the driving circuit 41 under the control of the Gate driving signal provided by the corresponding row Gate line Gate;
the light-emitting control circuit 42 is electrically connected to the light-emitting control line EM, the first voltage terminal V1, the first terminal of the driving circuit 41, the second terminal of the driving circuit 41, and the first electrode of the light-emitting element 40, respectively, and is configured to control communication between the first voltage terminal V1 and the first terminal of the driving circuit 41 and communication between the second terminal of the driving circuit 41 and the first electrode of the light-emitting element 40 under the control of a light-emitting control signal provided by the light-emitting control line EM;
the second pole of the light emitting device 40 is electrically connected to the second voltage terminal V2.
In an embodiment of the present invention, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.
Optionally, as shown in fig. 4, an embodiment of the pixel circuit may further include a second reset circuit 46;
the second reset circuit 46 is electrically connected to the reset control line Reseta + 1 of the next adjacent row, the initial voltage terminal and the first pole of the light emitting element 40, respectively, and is configured to write the initial voltage Vinit to the first pole of the light emitting element 40 under the control of the reset control signal provided by the reset control line Reseta + 1 of the next adjacent row.
In an embodiment of the invention, the driving module may be configured to output a gate driving signal provided to the gate line.
In the embodiment shown in fig. 4, Reset may be a row a Reset control line, Reseta +1 may be a row a +1 Reset control line, and Gate may be a row a Gate line, the waveform of the Reset control signal provided by Reset may be the same as the waveform of the Gate driving signal provided by the adjacent upper row Gate line (i.e., the row a-1 Gate line), and the waveform of the Reset control signal provided by Reseta +1 may be the same as the waveform of the Gate driving signal provided by Gate. Wherein a is a positive integer.
As shown in fig. 5, on the basis of the embodiment shown in fig. 4, the light emitting element may be an organic light emitting diode O1; the first reset circuit 45 includes a first reset transistor T1, the compensation control circuit 44 includes a compensation control transistor T2, and the driving circuit 41 includes a driving transistor T3; the data write circuit 43 includes a data write transistor T4, and the light emission control circuit includes a first light emission control transistor T5 and a second light emission control transistor T6; the second reset circuit 46 includes a second reset transistor T7;
the grid electrode of the T2 is electrically connected with the grid electrode of the corresponding row grid line Gate, the source electrode of the T2 is electrically connected with the grid electrode of the T3, and the drain electrode of the T2 is electrically connected with the drain electrode of the T3;
the grid electrode of the T4 is electrically connected with the grid electrode Gate of the corresponding row, the source electrode of the T4 is electrically connected with the data line D0 of the corresponding column, and the drain electrode of the T4 is electrically connected with the drain electrode of the T5; the data line D0 is used for providing a data voltage Vdata;
the gate of T1 is electrically connected to a Reset control line Reset, the source of T1 is electrically connected to an initial voltage line, and the drain of T1 is electrically connected to the gate of T3; the initial voltage line is used for providing an initial voltage Vinit;
a gate of T5 is electrically connected to the emission control line EM, a source of T5 is electrically connected to the high voltage line VDD, and a drain of T5 is electrically connected to a source of T3;
the gate of the T6 is electrically connected to the emission control line EM, the source of the T6 is electrically connected to the drain of the T3, and the drain of the T6 is electrically connected to the anode of the O1;
the grid electrode of the T7 is electrically connected with the grid line Gate, the source electrode of the T7 is electrically connected with the adjacent next-stage reset control line Reseta + 1, and the drain electrode of the T7 is electrically connected with the anode of the GOUT 1;
the cathode of O1 is electrically connected to a low voltage terminal VSS.
In the embodiment shown in fig. 5, the first voltage terminal is the high voltage terminal VDD, and the second voltage terminal is the low voltage terminal VSS.
In the embodiment of the pixel circuit shown in fig. 5, all the transistors are p-type thin film transistors.
In operation of the embodiment of the pixel circuit shown in fig. 5, as shown in fig. 6, the gate line may provide the gate driving signal having three pulses (the gate driving signal is not limited to having three pulses, and may have at least two pulses) in one frame time, and the EM provides the low voltage signal only after the third pulse comes, so that the gate line provides the first two pulses, even though T2, T3, and T4 are turned on, the display is not affected.
In the embodiment of the present invention, the structure of the pixel circuit is not limited to that shown in fig. 4 and 5.
In specific implementation, in a frame time, the input signal received by the input end of the driving circuit includes M pulses, M is an integer greater than 1, and the number of the dummy driving circuits included in the driving module may be greater than or equal to M +1, so as to effectively improve the defect of dark bottom when the display panel displays.
When the display panel comprises six rows of pixel circuits arranged in an effective display area, the driving module comprises a six-stage driving circuit and a four-stage pseudo driving circuit; four rows of load circuits are arranged in the peripheral area of the display panel (the load circuits comprise B rows of load sub-circuits, each load sub-circuit comprises a capacitor and a switch transistor which are electrically connected with each other, the grid electrode of each switch transistor is electrically connected with the output end of the corresponding pseudo-drive circuit, the first electrode of each switch transistor is electrically connected with the corresponding row data line, the second electrode of each switch transistor is electrically connected with the first electrode plate of the capacitor, and the second electrode plate of each capacitor is electrically connected with the first voltage end);
an output end Gout1 of the first-stage driving circuit is electrically connected with a first row of grid lines, an output end Gout2 of the second-stage driving circuit is electrically connected with a second row of grid lines, an output end Gout3 of the third-stage driving circuit is electrically connected with a third row of grid lines, an output end Gout4 of the fourth-stage driving circuit is electrically connected with a fourth row of grid lines, an output end Gout5 of the fifth-stage driving circuit is electrically connected with a fifth row of grid lines, and an output end Gout6 of the sixth-stage driving circuit is electrically connected with a sixth row of grid lines;
the first row of pixel circuits in the effective display area are electrically connected with the first row of grid lines, the second row of pixel circuits in the effective display area are electrically connected with the second row of grid lines, the third row of pixel circuits in the effective display area are electrically connected with the third row of grid lines, the fourth row of pixel circuits in the effective display area are electrically connected with the fourth row of grid lines, the fifth row of pixel circuits in the effective display area are electrically connected with the fifth row of grid lines, and the sixth row of pixel circuits in the effective display area are electrically connected with the sixth row of grid lines;
the output end Dummy1 of the first stage Dummy driving circuit is electrically connected with the first row load circuit, the output end Dummy2 of the second stage Dummy driving circuit is electrically connected with the second row load circuit, the output end Dummy3 of the third stage Dummy driving circuit is electrically connected with the third row load circuit, and the output end Dummy4 of the fourth stage Dummy driving circuit is electrically connected with the fourth row load circuit;
fig. 7 shows waveforms of a signal output from Gout1, a signal output from Gout2, a signal output from Gout3, a signal output from Gout4, a signal output from Gout5, a signal output from Gout6, a signal output from Dummy1, a signal output from Dummy2, a signal output from Dummy3, and a signal output from Dummy 4.
In fig. 7, reference numeral MUX is a control signal of the data selection switch.
As shown in fig. 7, when Gout3 outputs the last downward pulse, Gout5 and Dummy1 also output the downward pulse, the data writing transistor included in the third row pixel circuit, the data writing transistor included in the fifth row pixel circuit, and the switching transistor in the first row load circuit are turned on, the data voltage is written in the third row pixel circuit, the fifth row pixel circuit, and the first row load circuit, and the fifth row pixel circuit and the first row load circuit share the data voltage supplied to the third row pixel circuit, so that the data voltage written in the third row pixel circuit is equivalent to a normal value;
when Gout4 outputs the last downward pulse, Gout6 and Dummy2 also output the downward pulse, a data writing transistor included in the fourth row pixel circuit, a data writing transistor included in the sixth pixel circuit, and a switching transistor in the second row load circuit are turned on, a data voltage is written in the fourth row pixel circuit, the sixth row pixel circuit, and the second row load circuit, and the sixth row pixel circuit and the second row load circuit share the data voltage supplied to the fourth row pixel circuit, so that the data voltage written in the fourth row pixel circuit is equivalent to a normal value;
when Gout5 outputs the last downward pulse, Dummy1 and Dummy3 also output downward pulses, the data writing transistor included in the pixel circuit of the fifth row, the switching transistor in the first load circuit, and the switching transistor in the third load circuit are all turned on, the data voltage is written in the pixel circuit of the fifth row, the load circuit of the first row, and the load circuit of the third row, and the load circuit of the first row and the load circuit of the third row share the data voltage supplied to the pixel circuit of the fifth row, so that the data voltage written in the pixel circuit of the fifth row is equivalent to a normal value;
when Gout6 outputs the last downward pulse, Dummy2 and Dummy4 also output the downward pulse, the data writing transistor included in the pixel circuit of the sixth row, the switching transistor in the second load circuit, and the switching transistor in the fourth load circuit are all turned on, the data voltage is written in the pixel circuit of the sixth row, the load circuit of the second row, and the load circuit of the fourth row, and the load circuit of the second row and the load circuit of the fourth row share the data voltage supplied to the pixel circuit of the sixth row, so that the data voltage written in the pixel circuit of the sixth row is equivalent to a normal value.
According to the embodiment of the invention, the problem of dark bottom when the display panel displays can be solved by additionally arranging the four-stage pseudo driving circuit and the four-row load circuit.
The display device provided by the embodiment of the invention comprises the display module.
The display device according to the embodiment of the present invention may be an OLED (organic light emitting diode) display device.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A display module is characterized by comprising a driving module and a display panel, wherein the display panel comprises a plurality of rows of data lines, a plurality of rows of B-row pixel circuits and an N-row load circuit; the data lines are electrically connected with corresponding column pixel circuits included in the display panel; b and N are both positive integers; the load circuit comprises a plurality of columns of load sub-circuits;
the driving module comprises a multi-stage driving circuit and an N-stage pseudo driving circuit, and the driving circuit is used for providing driving signals for the pixel circuits of the corresponding row included in the display panel;
the input end of each stage of pseudo driving circuit except the first stage of pseudo driving circuit in the driving module is electrically connected with the output end of the adjacent previous stage of pseudo driving circuit, and the output end of the adjacent previous stage of pseudo driving circuit provides corresponding input signals for the input end of each stage of pseudo driving circuit;
the nth row load circuit comprises B columns of load sub-circuits;
the b column load sub-circuit comprises an n row b column switch circuit and an n row b column tank circuit; n is a positive integer less than or equal to N, B is a positive integer less than or equal to B;
the control end of the nth row and the nth column of switch circuits is electrically connected with the output end of the nth-stage pseudo drive circuit, the first end of the nth row and the nth column of switch circuits is electrically connected with the nth column of data line, and the second end of the nth row and the nth column of switch circuits is electrically connected with the nth row and the nth column of energy storage circuit; the nth row and nth column switch circuit is used for controlling the connection or disconnection between the nth column data line and the nth row and nth column energy storage circuit under the control of a signal provided by an output end of the nth stage pseudo driving circuit;
and the nth row and the mth column of the energy storage circuit are used for storing electric energy.
2. The display module of claim 1, wherein the nth row and column switch circuit comprises an nth row and column switch transistor, and the nth row and column tank circuit comprises an nth row and column capacitor;
a control electrode of the nth row and the nth column of switch transistors is electrically connected with an output end of the nth-stage pseudo driving circuit, a first electrode of the nth row and the nth column of switch transistors is electrically connected with the nth column of data line, and a second electrode of the nth row and the nth column of switch transistors is electrically connected with a first polar plate of the nth row and the nth column of capacitors;
and the second polar plate of the nth row and the nth column capacitor is electrically connected with a first voltage end.
3. The display module of claim 2, wherein the pixel circuit comprises a storage capacitor; the capacitance value of the nth row and the mth column capacitor is the same as that of the storage capacitor.
4. The display module according to claim 3, wherein the pixel circuit further comprises a light emitting element, a driving circuit, a light emission control circuit, a data writing circuit, a compensation control circuit, and a first reset circuit;
the first reset circuit is respectively electrically connected with a reset control line, an initial voltage line and a first plate of the storage capacitor, and is used for writing the initial voltage provided by the initial voltage line into the first plate of the storage capacitor under the control of a reset control signal provided by the reset control line;
the second electrode plate of the storage capacitor is electrically connected with the first voltage end;
the data writing circuit is respectively electrically connected with the corresponding row grid line, the corresponding column data line and the first end of the driving circuit and is used for supplying data voltage on the corresponding column data line to the first end of the driving circuit under the control of a grid driving signal supplied by the corresponding row grid line;
the compensation control circuit is respectively electrically connected with the corresponding row of grid lines, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the grid driving signal provided by the corresponding row of grid lines;
the light-emitting control circuit is respectively electrically connected with a light-emitting control line, the first voltage end, the first end of the driving circuit, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the first voltage end and the first end of the driving circuit and controlling the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control line;
and the second pole of the light-emitting element is electrically connected with the second voltage end.
5. The display module of claim 4, wherein the pixel circuit further comprises a second reset circuit;
the second reset circuit is electrically connected to the reset control line of the next row adjacent thereto, the initial voltage terminal, and the first electrode of the light emitting element, respectively, and is configured to write the initial voltage to the first electrode of the light emitting element under control of a reset control signal provided by the reset control line of the next row adjacent thereto.
6. The display module according to any one of claims 1 to 3, wherein the display panel comprises an effective display area and a peripheral area, the pixel circuit is disposed in the effective display area, and the load circuit is disposed in the peripheral area.
7. The display module according to any one of claims 1 to 3, wherein the structure of the dummy driving circuit is the same as the structure of the driving circuit.
8. A display module according to any one of claims 1 to 3, wherein the drive circuit is a gate drive circuit for providing a respective gate drive signal to a respective row of pixel circuits via the output terminal.
9. The display module according to any one of claims 1 to 3, wherein the input signal received by the input terminal of the driving circuit comprises M pulses in a frame time, M is an integer greater than 1, and N is greater than or equal to M + 1.
10. A display device comprising the display module according to any one of claims 1 to 9.
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| WO2023206371A1 (en) * | 2022-04-29 | 2023-11-02 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
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