CN113411082A - Zero-delay circuit for multi-path clock output and input alignment - Google Patents
Zero-delay circuit for multi-path clock output and input alignment Download PDFInfo
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- CN113411082A CN113411082A CN202110863866.5A CN202110863866A CN113411082A CN 113411082 A CN113411082 A CN 113411082A CN 202110863866 A CN202110863866 A CN 202110863866A CN 113411082 A CN113411082 A CN 113411082A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
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Abstract
The application provides a zero delay circuit of multichannel clock output and input alignment, includes: the phase detector comprises a bus, a phase detector and a phase modulator, wherein a multi-path input clock and an output clock can be transmitted to the phase detector through the bus; the clock signals needing to be aligned are transmitted through the bus, so that the clock signals needing to be aligned can be arranged at any position on a chip, and the positions of the clock signals can be far away; the circuit architecture of the multi-channel clock output and input alignment zero-delay circuit is simple, the circuit architecture can be flexibly adjusted, various different clock alignment signals can be simultaneously realized, zero delay of the clock signals is realized, and therefore the precision of time synchronization of the clock signals is guaranteed.
Description
Technical Field
The present application relates to the field of electronic circuits, and in particular, to a zero-delay circuit for multi-channel clock output and input alignment.
Background
With the continuous development of communication networks, there is an increasingly wide demand for time synchronization of clock signals, and the precision requirement for the time synchronization is also higher and higher. If the accuracy of the clock signal time synchronization is poor, the communication quality and the data transmission efficiency of the communication network are affected.
In the prior art, time synchronization of clock signals is mainly achieved through clock alignment. In some cases it is desirable to align multiple output clocks with the input clock, or multiple different output clocks; in other cases, a plurality of different clock alignment signals need to exist simultaneously to meet different application requirements. How to take both situations into consideration has become a technical problem to be solved urgently in the field.
Disclosure of Invention
In view of the above-mentioned problems in the background art, the present application provides a simple and flexibly adjustable zero-delay circuit for aligning multiple clock outputs and inputs, so as to implement zero-delay of clock signals, thereby ensuring the accuracy of time synchronization of clock signals.
In order to achieve the above object, the present application provides the following technical solutions:
a multi-clock output and input aligned zero-delay circuit, comprising: bus, phase detector and phase modulator, wherein:
the bus is used for transmitting an input clock and an output clock of the phase modulator to the phase discriminator;
a first input end of the phase discriminator is used for acquiring a clock signal transmitted on the bus;
the second input end of the phase discriminator is connected with the output end of the phase modulator, and the phase discriminator is used for comparing the phases of the clock signal transmitted on the bus and the output clock processed by the phase modulator to obtain a signal representing the phase difference between the two;
the phase modulator is used for adjusting the phase of the local clock according to an output signal of the phase discriminator to obtain an output clock aligned with a clock signal transmitted on the bus;
when the output clock is required to be aligned with the input clock, transmitting the input clock to the phase discriminator through the bus; comparing the phases of the input clock and the output clock processed by the phase modulator through the phase discriminator to obtain a signal representing the phase difference between the input clock and the output clock; adjusting the phase of the local clock by the phase modulator according to the output signal of the phase discriminator to obtain an output clock aligned with the input clock, so as to realize zero delay of the output clock and the input clock;
when the different output clocks are required to be aligned, transmitting the target output clock processed by the phase modulator to the phase discriminator through the bus; comparing the phases of the target output clock and the output clock to be adjusted through the phase discriminator to obtain a signal representing the phase difference between the target output clock and the output clock; and the phase modulator adjusts the phase of the local clock according to the output signal of the phase discriminator to obtain an output clock aligned with a target output clock, so that zero delay of the output clock is realized.
Further, the bus may simultaneously access a variety of different clock signals.
Further, the number of buses is consistent with the number of different clock alignment signals simultaneously.
Further, the clock signal alignment mode is rising edge alignment and/or falling edge alignment.
The application a zero delay circuit is aimed at in multichannel clock output and input, include: the phase detector comprises a bus, a phase detector and a phase modulator, wherein a multi-path input clock and an output clock can be transmitted to the phase detector through the bus; when the output clock is required to be aligned with the input clock, the input clock is transmitted to the phase discriminator through the bus, then the phase discriminator compares the phases of the input clock and the output clock processed by the phase discriminator to obtain a signal representing the phase difference between the input clock and the output clock, and then the phase discriminator adjusts the phase of the local clock according to the output signal of the phase discriminator to obtain the output clock aligned with the input clock; when different output clocks are required to be aligned, a target output clock processed by the phase modulator is transmitted to the phase discriminator through the bus, then the phase discriminator compares the phases of the target output clock and the output clock required to be adjusted to obtain a signal representing the phase difference between the target output clock and the output clock, and then the phase modulator adjusts the phase of the local clock according to the output signal of the phase discriminator to obtain the output clock aligned with the target output clock.
The clock signals needing to be aligned are transmitted through the bus, so that the clock signals needing to be aligned can be arranged at any position on a chip, and the positions of the clock signals can be far away; meanwhile, the multi-channel clock output and input alignment zero-delay circuit is simple in circuit structure and flexible in adjustment, and can realize that a plurality of different clock alignment signals exist simultaneously, zero delay of the clock signals is achieved, and therefore the precision of time synchronization of the clock signals is guaranteed.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a multi-clock output and input alignment zero-delay circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another multi-clock output and input alignment zero-delay circuit according to an embodiment of the present disclosure.
Detailed Description
The application provides a simple and flexibly adjustable multi-channel clock output and input alignment zero-delay circuit, which is used for realizing zero delay of clock signals, thereby ensuring the time synchronization precision of the clock signals and realizing the time synchronization of the clock signals in a communication network.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
For convenience of understanding, in the technical solutions disclosed in the embodiments of the present application, two input clocks, two output clocks, and one bus are taken as examples to illustrate the principles of the embodiments of the present application.
Referring to fig. 1, a schematic structural diagram of a multi-clock output and input alignment zero-delay circuit according to an embodiment of the present application is shown. As shown in fig. 1, the multi-clock output and input alignment zero-delay circuit includes: bus 10, phase detector 21, phase modulator 31, phase detector 22, phase modulator 32, wherein:
the bus 10 is used to couple the input clock Clkin1Input clock Clkin2The output clock Clk of the phase modulator 31out1And an output clock Clk of the phase modulator 32out2To the phase detector 21 and the phase detector 22.
A first input terminal of the phase detector 21 is configured to obtain a clock signal transmitted on the bus 10, a second input terminal of the phase detector 21 is connected to an output terminal of the phase modulator 31, and the phase detector 21 is configured to compare the clock signal transmitted on the bus 10 with an output clock Clk processed by the phase modulator 31out1To obtain a phase representing the clock signal transmitted on said bus 10 and the output clock Clk processed by said phase modulator 31out1Signal V of the phase differencepd1。
A first input of said phase modulator 31 is used to derive a local clock Clklocal1A second input end of the phase modulator 31 is connected to an output end of the phase detector 21, and the phase modulator 31 is configured to output a signal V according to the phase detector 21pd1Adjusting the local clock Clklocal1To obtain an output clock Clk aligned with the clock signal transmitted on said bus 10out1。
A first input terminal of the phase detector 22 is configured to obtain a clock signal transmitted on the bus 10, a second input terminal of the phase detector 22 is connected to an output terminal of the phase modulator 32, and the phase detector 22 is configured to compare the clock signal transmitted on the bus 10 with an output clock Clk processed by the phase modulator 32out2To obtain a phase ofRepresenting the clock signal transmitted on the bus 10 and the output clock Clk processed by the phase modulator 32out2Signal V of the phase differencepd2。
A first input of said phase modulator 32 is used to derive a local clock Clklocal2A second input terminal of the phase modulator 32 is connected to an output terminal of the phase detector 22, and the phase modulator 32 is configured to output a signal V according to the phase detector 22pd2Adjusting the local clock Clklocal2To obtain an output clock Clk aligned with the clock signal transmitted on said bus 10out2。
When the output clock Clk is requiredout1And said output clock Clkout2And said input clock Clkin1Or the input clock Clkin2When aligned, the input clock Clk is setin1Or the input clock Clkin2Are transmitted to the phase detector 21 and the phase detector 22 via the bus 10. The input clocks Clk are then compared by the phase detector 21in1Or the input clock Clkin2Output clock Clk processed by the phase modulator 31outTo obtain a signal V representing the phase difference between the twopd1Then the phase modulator 31 outputs the signal V according to the phase detector 21pd1Adjusting the local clock Clklocal1To the input clock Clk, to obtain the phase of the input clock Clkin1Or the input clock Clkin2Aligned output clock Clkout1(ii) a Comparing the input clock Clk by the phase detector 22in1Or the input clock Clkin2Output clock Clk processed by the phase modulator 32out2To obtain a signal V representing the phase difference between the twopd2And then the phase modulator 32 outputs the signal V according to the phase detector 22pd2Adjusting the local clock Clklocal2To the input clock Clk, to obtain the phase of the input clock Clkin1Or the input clock Clkin2Aligned output clock Clkout2。
When the output clock Clk is requiredout1And said output clock Clkout2When aligned, the phase modulator 31 is adjustedProcessed output clock Clkout1Or the output clock Clk after processing by the phase modulator 32out2Transmitted to the phase detector 22 or the phase detector 21 through the bus 10, and then compared with the output clock Clk through the phase detector 22 or the phase detector 21out1And said output clock Clkout2To obtain a signal indicating the phase difference between them, and then the phase modulator 32 or the phase modulator 31 adjusts the local clock Clk according to the output signal of the phase detector 22 or the phase detector 21local2Or the local clock Clklocal1To obtain an aligned output clock Clkout1And Clkout2。
For convenience of understanding, in the technical solutions disclosed in the embodiments of the present application, two input clocks, two output clocks, and two buses are taken as examples to illustrate the principles of the embodiments of the present application.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another multi-clock output and input alignment zero-delay circuit disclosed in the embodiment of the present application. As shown in fig. 2, the multi-clock output and input alignment zero-delay circuit includes: bus 20, bus 30, data selector 11, phase detector 21, phase modulator 31, data selector 12, phase detector 22, phase modulator 32, wherein:
the bus 20 and the bus 30 are used for inputting the clock Clkin1Input clock Clkin2The output clock Clk of the phase modulator 31out1And an output clock Clk of the phase modulator 32out2To the data selector 11 and the data selector 12.
A first input terminal of the data selector 11 is configured to obtain the clock signal transmitted on the bus 20, a second input terminal of the data selector 11 is configured to obtain the clock signal transmitted on the bus 30, and the data selector 11 is configured to select the clock signal transmitted on the bus 20 or the bus 30 as required, as an output signal Clk of the data selector 111。
A first input terminal of the phase detector 21 is connected to the output terminal of the data selector 11, and a second input terminal of the phase detector 21The terminal of which is connected to the output terminal of the phase modulator 31, and the phase detector 21 is configured to compare the output signal Clk of the data selector 111And the output clock Clk processed by the phase modulator 31out1To obtain an output signal Clk representing said data selector 111And the output clock Clk processed by the phase modulator 31out1Signal V of the phase differencepd1。
A first input of said phase modulator 31 is used to derive a local clock Clklocal1A second input end of the phase modulator 31 is connected to an output end of the phase detector 21, and the phase modulator 31 is configured to output a signal V according to the phase detector 21pd1Adjusting the local clock Clklocal1To obtain an output clock Clk aligned with the clock signal transmitted on said bus 20 or said bus 30out1。
A first input terminal of the data selector 12 is configured to obtain the clock signal transmitted on the bus 20, a second input terminal of the data selector 12 is configured to obtain the clock signal transmitted on the bus 30, and the data selector 12 is configured to select the clock signal transmitted on the bus 20 or the bus 30 as required, as an output signal Clk of the data selector 122；
A first input terminal of the phase detector 22 is connected to the output terminal of the data selector 12, a second input terminal of the phase detector 22 is connected to the output terminal of the phase modulator 32, and the phase detector 22 is configured to compare the output signal Clk of the data selector 122And the output clock Clk processed by the phase modulator 32out2To obtain an output signal Clk representing said data selector 122And the output clock Clk processed by the phase modulator 32out2Signal V of the phase differencepd2。
A first input of said phase modulator 32 is used to derive a local clock Clklocal2A second input terminal of the phase modulator 32 is connected to an output terminal of the phase detector 22, and the phase modulator 32 is configured to output a signal V according to the phase detector 22pd2Adjusting the local clock Clklocal2Obtaining a phase ofClock signal aligned output clock Clk transmitted on bus 20 or bus 30out2。
When the output clock Clk is requiredout1And said input clock Clkin1Alignment, the output clock Clkout2And said input clock Clkin2When aligned, the input clock Clk is setin1The input clock Clkin2The data are transmitted to the data selector 11 and the data selector 12 through the bus 20 and the bus 30 respectively; the data selector 11 then selects the input clock Clkin1As an output signal, the data selector 12 selects the input clock Clkin2As an output signal; finally, the output signal Clk of the data selector 11 is compared by the phase detector 211Output clock Clk processed by the phase modulator 31out1To obtain a signal V representing the phase difference between the twopd1Then the phase modulator 31 outputs the signal V according to the phase detector 21pd1Adjusting the local clock Clklocal1To the input clock Clk, to obtain the phase of the input clock Clkin1Aligned output clock Clkout1(ii) a The output signal Clk of the data selector 12 is compared by the phase detector 222Output clock Clk processed by the phase modulator 32out2To obtain a signal V representing the phase difference between the twopd2And then the phase modulator 32 outputs the signal V according to the phase detector 22pd2Adjusting the local clock Clklocal2To the input clock Clk, to obtain the phase of the input clock Clkin2Aligned output clock Clkout2。
It should be noted that the clock signal alignment manner is a rising edge alignment and/or a falling edge alignment.
The embodiment of the application provides a zero delay circuit of multi-channel clock output and input alignment, including: the phase detector comprises a bus, a phase detector and a phase modulator, wherein a multi-path input clock and an output clock can be transmitted to the phase detector through the bus; when the output clock is required to be aligned with the input clock, the input clock is transmitted to the phase discriminator through the bus, then the phase discriminator compares the phases of the input clock and the output clock processed by the phase discriminator to obtain a signal representing the phase difference between the input clock and the output clock, and then the phase discriminator adjusts the phase of the local clock according to the output signal of the phase discriminator to obtain the output clock aligned with the input clock; when different output clocks are required to be aligned, a target output clock processed by the phase modulator is transmitted to the phase discriminator through the bus, then the phase discriminator compares the phases of the target output clock and the output clock required to be adjusted to obtain a signal representing the phase difference between the target output clock and the output clock, and then the phase modulator adjusts the phase of the local clock according to the output signal of the phase discriminator to obtain the output clock aligned with the target output clock.
The multi-channel clock output and input alignment zero-delay circuit provided by the embodiment of the application transmits clock signals needing to be aligned through a bus, so that the clock signals needing to be aligned can be arranged at any position on a chip, and the positions of the clock signals can be far away; meanwhile, the multi-channel clock output and input alignment zero-delay circuit provided by the embodiment of the application has the advantages that the circuit architecture is simple to realize, the circuit architecture can be flexibly adjusted, various different clock alignment signals can be simultaneously realized, the zero delay of the clock signals is realized, and the precision of the time synchronization of the clock signals is ensured.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Thus, it should be appreciated by those skilled in the art that while a number of exemplary embodiments of the present application have been illustrated and described in detail herein, many other variations and modifications consistent with the principles of the application may be ascertained or derived directly from the disclosure herein without departing from the spirit and scope of the application. Accordingly, the scope of the present application should be understood and interpreted to cover all such other variations or modifications.
Claims (4)
1. A multi-clock output and input aligned zero delay circuit, comprising: bus, phase detector and phase modulator, wherein:
the bus is used for transmitting an input clock and an output clock of the phase modulator to the phase discriminator;
a first input end of the phase discriminator is used for acquiring a clock signal transmitted on the bus;
the second input end of the phase discriminator is connected with the output end of the phase modulator, and the phase discriminator is used for comparing the phases of the clock signal transmitted on the bus and the output clock processed by the phase modulator to obtain a signal representing the phase difference between the two;
the phase modulator is used for adjusting the phase of the local clock according to an output signal of the phase discriminator to obtain an output clock aligned with a clock signal transmitted on the bus;
when the output clock is required to be aligned with the input clock, transmitting the input clock to the phase discriminator through the bus; comparing the phases of the input clock and the output clock processed by the phase modulator through the phase discriminator to obtain a signal representing the phase difference between the input clock and the output clock; adjusting the phase of the local clock by the phase modulator according to the output signal of the phase discriminator to obtain an output clock aligned with the input clock, so as to realize zero delay of the output clock and the input clock;
when the different output clocks are required to be aligned, transmitting the target output clock processed by the phase modulator to the phase discriminator through the bus; comparing the phases of the target output clock and the output clock to be adjusted through the phase discriminator to obtain a signal representing the phase difference between the target output clock and the output clock; and the phase modulator adjusts the phase of the local clock according to the output signal of the phase discriminator to obtain an output clock aligned with a target output clock, so that zero delay of the output clock is realized.
2. The multiple clock output and input aligned zero delay circuit of claim 1 wherein the bus is accessible to a plurality of different clock signals simultaneously.
3. The multiple clock output and input aligned zero delay circuit of claim 1 wherein the number of buses is consistent with the number of different clock alignment signals simultaneously.
4. The multiple clock output and input aligned zero delay circuit of claim 1, wherein the clock signal alignment is rising edge alignment and/or falling edge alignment.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114035417A (en) * | 2021-11-26 | 2022-02-11 | 杭州长川科技股份有限公司 | Head edge alignment method, head edge alignment circuit and system for multiple measurement links |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114035417A (en) * | 2021-11-26 | 2022-02-11 | 杭州长川科技股份有限公司 | Head edge alignment method, head edge alignment circuit and system for multiple measurement links |
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