CN113411076B - Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics - Google Patents

Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics Download PDF

Info

Publication number
CN113411076B
CN113411076B CN202110746404.5A CN202110746404A CN113411076B CN 113411076 B CN113411076 B CN 113411076B CN 202110746404 A CN202110746404 A CN 202110746404A CN 113411076 B CN113411076 B CN 113411076B
Authority
CN
China
Prior art keywords
turn
voltage
igbt
transient
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110746404.5A
Other languages
Chinese (zh)
Other versions
CN113411076A (en
Inventor
赵争鸣
凌亚涛
姬世奇
萧艺康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Priority to CN202110746404.5A priority Critical patent/CN113411076B/en
Publication of CN113411076A publication Critical patent/CN113411076A/en
Application granted granted Critical
Publication of CN113411076B publication Critical patent/CN113411076B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/0406—Modifications for accelerating switching in composite switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses a grid driving method for accurately controlling IGBT peak voltage and improving switching characteristics, which belongs to the technical field of power electronics PK Determining the digital quantity of the proportional relation, and finally outputting the digital quantity to a Field Programmable Gate Array (FPGA) on a driving board; the FPGA chip combines the digital quantity with a reference value V ref The corresponding digital quantity is subjected to proportional-integral PI operation to generate IGBT turn-off transient di obtained by a PI regulator C Driving voltage at the stage of/dt and at turn-off transient di C The/dt stage is applied to the IGBT gate; the invention realizes the v-pair under different load currents PK Lower turn-off delay and turn-off loss; and is adaptive to the change of working conditions; the control method is more v than the existing control method PK The control method has high precision.

Description

Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a grid driving method for accurately controlling IGBT peak voltage and improving switching characteristics, in particular to a pair v PK A self-adjusting peak control gate drive method that applies direct sampling and control.
Background
The IGBT device turn-off transient terminal voltage peak value directly influences the safe operation and reliability of the device and the system, and accurate control of the terminal voltage peak value has obvious significance for improving the bus voltage and the IGBT utilization rate, widening the safe working area of the device and further improving the power processing capacity of the device.
The three factors of the voltage peak value of the turn-off transient terminal, the bus voltage, the tube current reduction speed and the size of the stray inductance of the commutation loop form a positive correlation: the expression is shown as formula (1), wherein v is PK For IGBT turn-off transient terminal voltage peak value, V bus Is a DC bus voltage v os To turn off transient terminal voltage overshoot, L S For commutation loop stray inductance, di C And/dt is the tube current decrease rate. Thus, correspondingly, aimThe measures for controlling the voltage peak value of the front end mainly include two measures: adjusting the main circuit; active gate control is employed.
v PK ＝V bus +vo s ＝V bus +L S |di C /dt| (1)
The typical method for adjusting the main circuit is to optimize the busbar structure to reduce the stray inductance of the commutation loop, and finally realize the control of the voltage of the turn-off transient terminal, but from the viewpoint of feasibility and cost, the stray inductance of the busbar cannot be reduced too low generally. In order to achieve precise control of the terminal voltage peak, it is then necessary to start with control on the drive side. At present, many grid driving methods control terminal voltage peak values by adjusting the current dropping speed of a turn-off transient tube. To adjust di C Dt, a part of the existing driving methods, indirectly controlling di by applying a preset amount of drive C (dt); the remaining driving method is to sample and control the slope di directly C And/dt. Although the two modes can obviously inhibit the terminal voltage peak value, the control of the terminal voltage peak value is inaccurate and cannot adapt to the change of the commutation working condition (the working condition comprises bus voltage, load current, junction temperature of a semiconductor device, stray inductance of a commutation loop and the like) because the sampling and the control cannot be directly applied to the terminal voltage peak value. With both indirect and direct control of di C Different from the dt method, there is also a more effective Hybrid driving method (Hybrid Active Gate Drive, HAGD method) that can directly sample and suppress the terminal voltage peak, and when the terminal voltage peak exceeds its reference value V ref Only then is it suppressed, fig. 1 shows a schematic diagram of the HAGD method suppressing the peak terminal voltage.
As can be seen from fig. 1, when the terminal voltage exceeds the reference value V ref When the voltage-controlled current source VCCS is triggered, the extra current i is injected into the IGBT grid electrode OPC Therefore, the current reduction speed of the IGBT tube is slowed down, and the end voltage peak value is restrained. i.e. i OPC Is expressed as formula (2), where the coefficient α is the gain of the VCCS in fig. 1. Obviously, the HAGD method compares directly or indirectly with the control, due to the direct sampling and suppression of the terminal voltage peaksdi C The method of/dt is more adaptable to the working condition change. However, if the tube current decreases rapidly, the peak value of the terminal voltage exceeds the reference value V ref ，i OPC There will be even larger amplitudes. The suppressed terminal voltage peak will then still exceed or even significantly exceed the reference value V according to equation (2) ref 。
i OPC ＝α·(v CE -V ref ) (2)
In summary, for terminal voltage peak control, di is controlled directly and indirectly C The drive method of/dt can not adapt to the change of the commutation working condition, and the control precision of the opposite terminal voltage peak value can not be ensured like the HAGD method. These disadvantages have diminished the practical value of existing gate drive methods for end voltage peak control. In the actual system design, in order to ensure that the turn-off transient peak voltage of the IGBT is always within an acceptable range, on one hand, a large safety margin needs to be reserved for the bus voltage, which results in that the power processing capability of the IGBT cannot be fully utilized; on the other hand, the switching speed of the IGBT needs to be reduced by increasing the driving resistance, so that turn-off delay and turn-off loss of the IGBT are increased, and the electric energy conversion efficiency of the system is affected.
The invention provides a pair v from the driving side of the IGBT PK Self-adjusting Peak Control gate drive method (SRPVC) applying direct sampling and Control, which is applied to v PK The control is accurate and is suitable for the change of the current conversion working condition. The driving method can realize v pairs PK And other switching characteristics, under which, on the one hand, v is then controlled and regulated PK Accurate control or limitation can be carried out, and on the other hand, the turn-off delay and turn-off loss of the IGBT device are also obviously reduced.
Disclosure of Invention
The invention aims to provide a grid driving method for accurately controlling IGBT peak voltage and improving switching characteristics, which is characterized by comprising the following steps:
1. accurately collecting the voltage peak value of the IGBT turn-off transient state terminal voltage at each time through a peak voltage detection and digitization circuit;
2. digitizing the peak value of the voltage at the transient state of turn-off to obtain the actual peak voltage v PK To a digital quantity that determines the proportional relationship,
3. outputting the digital quantity to a Field Programmable Gate Array (FPGA) chip (Field Programmable Gate Array, hereinafter referred to as FPGA) on a driving board;
4, the FPGA chip combines the digital quantity with the reference value V ref Performing Proportional-Integral PI operation on the corresponding digital value to obtain corresponding driving voltage value v PK ；
5. The digital quantity and the reference value V are processed by the FPGA chip ref The corresponding digital quantity is used for proportional-integral PI operation to generate the turn-off transient di obtained by the PI regulator C Driving the voltage in the phase of/dt and in the turn-off transient di C The/dt stage is applied to the IGBT gate.
6. According to PWM switching command signal and sampling signal di C Dt identifies the current IGBT stage, and thus the turn-off transient di C Control is applied in the/dt stage;
di of the detection turn-off transient C A/dt stage to enable a delay stage of the IGBT turn-off transient, dv CE Dt stage and di C Decoupling control is realized in three stages of the/dt stage, so that v is accurately controlled PK Meanwhile, the turn-off delay and turn-off loss can be kept low;
for turn-off transient di in said step 6 C Control may be applied during the/dt phase at di C Applying a high drive voltage v during the phase/dt G,ifH To obtain a small terminal voltage peak value v PK,L Or by applying a small value of the drive voltage v G,ifL To obtain a large terminal voltage peak value v PK,H (ii) a Or in the delay and dv CE The lowest driving voltage V is always applied in the stage of/dt EE So as to obtain the lowest turn-off delay and turn-off loss and realize the optimization of turn-off delay and loss.
Under the self-regulation control, the device will convert v into V under rated load current PK Control to V ref (ii) a In addition, the sum dv CE V of the/dt stage G Is kept at a minimum V EE To achieve minimal turn-off delay and loss.
The invention has the beneficial effect of realizing the v-pair under different load currents PK While achieving lower turn-off delay and turn-off losses compared to lower IGBTs of existing methods. Since it is directly opposite to v PK Sampling and controlling are carried out, so that the peak voltage is accurately controlled and is adaptive to working condition change. The precision of the control method is higher than that of all the existing v PK The control method has high precision.
Drawings
Fig. 1 is a schematic diagram of an opposite-end voltage peak suppression method in the HAGD driving method.
Fig. 2 is a control block diagram of the terminal voltage peak value in the driving method.
Fig. 3 is a schematic time-domain waveform of the voltage peak at the control terminal of the SRPVC in the driving method, wherein (a) the turn-off transient is divided into 4 stages; and (b) shows the working process of the SRPVC method in practical application. V in FIG. 3 G Is IGBT drive voltage, V CC 、V EE Respectively an on-state and an off-state driving voltage value, V th Is the threshold voltage of IGBT, i C 、v CE Current and terminal voltage of IGBT tube, I L Is the load current.
FIG. 4 is a comparison of IGBT turn-off transient performance under the SRPVC method and the CGD method of the present driving method, wherein (a) the SRPVC method applies more than V EE Drive voltage v of G,if (ii) a (b) The turn-off performance of the CGD and SRPVC methods at low load current was compared.
FIG. 5 is a waveform of a turn-off transient test under the SRPVC and CGD driving methods of the present invention at 600V/300A; wherein (a) the CGD method, not v PK Control, IGBT Gate drive resistor R g =4 Ω; (b) SRPVC Process as PK Control, IGBT Gate drive resistor R g ＝4Ω。
FIG. 6 shows a 600V bus voltage, turn-off transient experimental waveform at different load currents; wherein (a) the CGD method, not v PK Control, IGBT Gate drive resistor R g =8.5 Ω; (b) SRPVC Process as PK The control is that the computer controls the computer to run,IGBT grid driving resistor R g ＝4Ω。
FIG. 7 shows a bus voltage of 600V, different from I L Next, comparing the turn-off transient performances of the CGD and the SRPVC; wherein, (a) terminal voltage peak comparison; b) Turn-off delay comparison; (c) turn-off loss comparison.
FIG. 8 is the turn-off transient di C And a/dt stage detection circuit.
Fig. 9 is a driving voltage generating circuit.
Fig. 10 shows peak voltage v PK A sampling circuit.
Detailed Description
The present invention provides a gate driving method for accurately controlling the peak voltage of an IGBT to improve the switching characteristics, and the present invention is further described in detail with reference to the accompanying drawings and embodiments.
Fig. 2 is a control block diagram of the terminal voltage peak value according to the driving method, and the self-adjusting gate driving method for accurately controlling the IGBT peak voltage shown in the drawing specifically includes the following steps:
1. the peak value of the voltage of the IGBT turn-off transient terminal at each time is accurately collected through a peak voltage detection and digitization circuit,
2. digitalizing the peak value of the turn-off transient terminal voltage to obtain the peak value voltage v PK The digital quantity with the determined proportional relation is sampled through the step 1 and the step 2, so that the use of high-speed components can be avoided, and the cost for realizing the sampling circuit is reduced while the accurate sampling is realized;
3. outputting the digital quantity to a Field Programmable Gate Array (FPGA) chip (Field Programmable Gate Array, hereinafter referred to as FPGA) on a driving board;
4, the FPGA chip compares the digital quantity with a reference value V ref Performing Proportional-Integral PI operation on the corresponding digital value to obtain corresponding driving voltage value v PK ；
5. The digital quantity and the reference value V are processed by the FPGA chip ref The corresponding digital quantity is used for proportional-integral PI operation to generate the turn-off transient di obtained by the PI regulator C Driving the voltage in the phase of/dt and in the turn-off transient di C The/dt stage is applied to the IGBT gate; di requiring detection of turn-off transient C A/dt stage to enable a delay stage of the IGBT turn-off transient, d v CE Stage d t and di C Decoupling control is realized in three stages of the/dt stage, so that v is accurately controlled PK Meanwhile, the turn-off delay and turn-off loss can be kept low;
6. according to PWM switching command signal and sampling signal di C Dt identifies the current IGBT stage, and thus the turn-off transient di C Applying control in a/dt stage; for turn-off transient di C The control applied during the/dt stage may be di C Applying a high drive voltage v during the phase/dt G,ifH To obtain a small terminal voltage peak value v PK,L Or by applying a small value of the drive voltage v G,ifL To obtain a large terminal voltage peak value v PK,H (ii) a Or at delay and dv CE The lowest driving voltage V is always applied in the stage of/dt EE So as to obtain the lowest turn-off delay and turn-off loss, and realize the optimization of the turn-off delay and the turn-off loss.
In particular, the driving method shown in FIG. 2 for v pk Working principle of applying self-adjusting control: firstly, a peak voltage detection and digitization circuit is used for accurately sampling the voltage peak value of the IGBT terminal voltage of each turn-off transient state, and then the voltage peak value is digitized to obtain the actual peak voltage v PK And finally, outputting the digital quantity to a Field Programmable Gate Array (FPGA) on a driving board. The FPGA chip combines the digital quantity with a reference value V ref And carrying out Proportional-Integral (PI) operation on the corresponding digital quantity to obtain a corresponding driving voltage value. In order to be able to switch off the IGBT in three phases (delay phase, dv) CE Stage d t,/di C At the/dt stage) to achieve decoupling control, thereby accurately controlling v PK At the same time, it is necessary to detect di at the turn-off transient C Whether the turn-off delay and turn-off loss can be kept low in the/dt stage; thus, the method also requires switching the command signal and the sampling signal di according to the PWM C Dt identifies the current IGBT stage, and thus the turn-off transient di C Control applied in the/dt stageAnd (5) preparing. The final part of the control method is to generate the drive voltage value obtained by the PI regulator and to switch off the transient di C The/dt stage is applied to the IGBT gate. V in FIG. 2 G,if I.e. the calculated and generated turn-off transient di C The/dt stage drive voltage.
The control process of the present invention works in a basic mode of switching cycle by switching cycle, self-regulation, since it is directed at v PK Sampling and controlling are carried out, so that the peak voltage is accurately controlled and is adaptive to working condition change. The precision of the control method is higher than that of all the existing v PK The control method has high precision.
Examples
Fig. 3 is a schematic time-domain waveform of the voltage peak at the control terminal of the SRPVC in the driving method, wherein (a) the turn-off transient is divided into 4 stages; (b) shows the working process of the SRPVC method in practical application;
the 4 stages from left to right indicated by the arrows in FIG. 3 are delay stages, d v CE Stage d t, di C A/dt stage and an off-state stage. Concretely provides SRPVC method pair v PK Time domain waveform schematic diagram for self-adjusting control and theoretical control effect. In FIG. 3 (a), note that the SRPVC process is paired with v PK The performance of the IGBT device in the delay and dv/dt stages is not affected, and the lowest driving voltage V can be always applied in the delay and dv/dt stages in the graph of fig. 3 (a) EE To obtain the lowest turn-off delay and turn-off loss. SRPVC Process Pair v PK The accuracy of the control and the adaptability to different commutation conditions are important. FIG. 3 (b) shows the operation of the SRPVC process in practical applications. As shown in FIG. 3 (b), the SRPVC method should apply a large driving voltage v at the 1 st turn-off transient due to unclear commutation conditions (load current, bus voltage, stray inductance of the commutation loop, IGBT type, etc.) G,if,1 This results in a lower peak safe voltage v PK,1 . The SRPVC method would then sample the actual v at each turn-off transient PK Value of v obtained PK Digital quantity and peak reference value V ref The digital quantity of (c) is subtracted. As introduced above, they yield poor results through the FPGAPI regulator for generating the next turn-off transient di C Drive voltage at/dt stage. The adjusting process is always in a working state, and the adaptability of the SRPVC method to various current conversion working conditions is ensured. In fig. 3 (b), at the I-th turn-off transient, the load current has been changed from I at the beginning L,1 Increase to I L,i And accordingly, to implement v PK ＝V ref The SRPVC process has also been described for di C The drive voltage of the/dt stage starts from the first v G,if,1 Is reduced to v G,if,i . Thus, in fig. 3 (b), the SRPVC method achieves a reference terminal voltage peak, i.e., v, at the i-th turn-off transient PK,i ＝V ref . Similar to FIG. 3 (a), FIG. 3 (b) will also delay and dv/dt stage v G Limited to the lowest driving voltage value V EE Thereby realizing the optimization of turn-off delay and loss.
FIG. 4 is a comparison of the instant turn-off performance of the IGBT under the SRPVC driving method and the Conventional driving method (CGD), in which V is greater than V is applied to the SRPVC method (a) in FIG. 4 EE Drive voltage v of G,if Implementing v identical to CGD PK ＝V ref . At the same time, the SRPVC process is at delay and dv CE Minimum driving voltage V is applied in the stage of/dt EE Due to the drive resistance R of the SRPVC g Smaller than CGD, the turn-off delay and loss of SRPVC at high load currents is significantly lower than the CGD method.
In fig. 4, (b) compares the turn-off performance of the CGD and SRPVC methods at small load currents. When I is L As becomes smaller, since the miller level falls, as shown in fig. 4 (b), the turn-off delay becomes larger in both driving methods, and the terminal voltage rising speed | dv CE The/dt | will decrease. But due to the drive resistance R of the SRPVC method g Smaller and therefore | dv under SRPVC control CE The/dt | is always larger than the CGD, while the turn-off delay and loss are always smaller than the CGD.
In combination with the above analysis of FIG. 4, the SRPVC method of the present invention can achieve the v-pair at different load currents PK While achieving lower IGBT turn-off performance (i.e., lower turn-off delay and turn-off loss) than existing approaches.
The control effect of SRPVC is further demonstrated by giving experimental waveforms as follows:
1) Accurate control of SRPVC v PK Experimental waveform of (2)
Off transient experimental waveforms for a plurality of consecutive pulses as shown in fig. 5; the different horizontal lines in the diagram represent v for each turn-off transient PK (ii) a Specifically, under 600V/300A, the switching-off transient experimental waveforms of the SRPVC driving method and the CGD method are given; wherein the reference value V of the terminal voltage peak value ref =900V, (a) CGD method, do not V PK Control, R g =4 Ω; (b) SRPVC Process as PK Control, R g ＝4Ω；
As can be seen from FIG. 5 (a), when the CGD method is used, v is seen for the 1 st turn-off transient PK,1 ＝880V<V ref . Since there is no pair v PK After that, in accordance with the load current I L Is constantly increasing, v PK And is also increasing and is turning off the transient v at the last 10 th turn-off PK,10 =1000V, much greater than V ref 。
As can be seen from FIG. 5 (b), SRPVC process pair v PK Applying a self-regulating control test waveform, v for pulse 1 PK,1 ＝860V<V ref . Note this initial v PK Less than the initial v in FIG. 5 (a) PK This is to safely turn off to prevent the voltage peak just above V ref Di at the initial turn-off transient C Higher v applied during the/dt phase G,if,1 . FIG. 5 (b) initial v G,if,1 0V, much greater than the initial V in (a) G,if,1 ＝V EE Then the initial v in (b) PK Smaller than (a). Under self-adjusting control, in order to make v PK Closer to V ref V of the 2 nd transient in (b) G,if V is greater than 1 st G,if Smaller, with the aim of accelerating i C Lowering the speed to increase v appropriately PK . Thereafter, as the load current increases, in order to control v PK Does not exceed and is as close as possible to V ref Driving voltage v G,if Will be increased gradually to slow down i C The rate of descent. In the last off-transient, v G,if About to achieveWith +4V, under self-regulation control, the device is under rated load current, and V can be converted as shown in (b) PK Control to V ref . In addition, the sum dv CE V of the/dt stage G Is kept at the lowest V EE To obtain minimal turn-off delay and loss.
2) SRPVC control v PK Meanwhile, the IGBT turn-off performance is improved compared with the CGD method
The principle of comparing the turn-off performance is that under the rated current of 300A, the CGD and SRPVC methods select a certain driving resistance value R g So that their terminal voltage peak v PK All reach V ref . Then respectively selecting a driving resistor R in the CGD and SRPVC methods g Next, experiments under various load currents are performed to verify the turn-off performance.
Reference value V of terminal voltage peak value here ref Taken as 900V. The CGD method is carried out under the condition of 600V/300A commutation at R g And the peak value of the off transient terminal voltage can be obtained at 900V when the voltage is 8.5 omega. While, according to the above analysis, the SRPVC method is in the case of v PK When self-adjusting control is applied, the small R can be g Next, optimization of turn-off performance (reduction of turn-off delay, turn-off loss) is expected. The SRPVC method can select smaller R g ＝4Ω。
As shown in fig. 6, at a bus voltage of 600V and different load currents, the transient experimental waveform is turned off; wherein, (a) CGD method, not v PK Control, R g =8.5 Ω; (b) SRPVC Process as PK Control of R g =4 Ω; under the driving resistance value, the CGD and SRPVC methods are used to make the turn-off transient experiment under various load currents,
as shown in FIG. 6 (a), v under the CGD method at the maximum current, i.e., the rated 300A load current PK ＝V ref =900V. With decreasing load current, the turn-off delay then rises slightly, | dv CE /d t|、|di C D t falling, terminal voltage peak v PK And also becomes smaller.
The turn-off transient waveform under the SRPVC method is shown in FIG. 6 (b), due to the smaller driving resistance R g Albeit itTurn-off delay, | dv CE /d t|、|di C The trend of/dt | change with load current is the same as the CGD method, but the magnitude of change is much smaller. Furthermore, comparing FIGS. 6 (a), (b), as analyzed above, the SRPVC process utilizes a smaller R g Thus, lower turn-off delay and higher | dv can be achieved CE Dt |, which results in lower turn-off losses. As shown in FIG. 6 (b), at v PK Under the self-regulation control, the SRPVC method automatically applies larger driving voltage v under larger load current (250A, 300A) G,if (0V, + 4V) control V PK Is equal to V ref (ii) a At lower load currents, even if the lowest drive voltage v is applied G,if ＝V EE Terminal voltage peak value v PK Is still less than V ref 。
The turn-off transient characteristics obtained by the CGD and SRPVC methods, including terminal voltage peak, turn-off delay, turn-off loss, were summarized and compared at different load currents as shown in fig. 6. The turn-off characteristics of the CGD and SRPVC methods at 50A to 300A load currents are shown as (a) a comparison of terminal voltage peak values in fig. 7; (b) Turn-off delay comparison and (c) turn-off loss comparison. As can be seen from FIG. 7, at a bus voltage of 600V, I is different L Next, comparing the turn-off transient performance of the SRPVC method with that of the CGD method, the peak value v of the IGBT terminal voltage PK Is always less than or equal to V ref . At the same time, since the SRPVC method employs the delay and dv for the turn-off transient as described above CE And (3) optimized control of the/dt stage, wherein compared with the existing CGD method, the turn-off delay and the loss are reduced by 53% and 28%, respectively.
FIG. 8 shows the turn-off transient di C A/dt stage detection circuit, wherein E is the power ground of the IGBT and the potential v E The expression is shown as formula (3), wherein L E Is the kelvin inductance value between the drive ground E and the power ground E of the IGBT. At the turn-off transient di C The/dt phase, as the tube current decreases, according to equation (3), v E Is at a positive potential. By diode blocking, resistive voltage division and buffers, di C The/dt stage will produce a positive v sig A signal. v. of sig Is connected to the FPGA chip on the driving board, thereby making the FPGA can know the current state of the IGBT.
Figure BDA0003143057500000101
FIG. 9 shows a driving voltage generating circuit, by which the SRPVC method requires accurate control of v PK The FPGA outputs Digital signals to a high-speed Digital-to-Analog Converter (DAC), the DAC amplifies the output voltage and current through an Operational Amplifier (OP) and a push-pull, and finally generates a required driving voltage v G . Output digital quantity CODE and v of FPGA G Is represented by formula (4), wherein k is 1 Is a coefficient, V bias For bias voltages, M is the number of parallel digital bits output by the FPGA of FIG. 9. According to the formula (4), the FPGA can generate various driving voltage values with high numerical resolution by outputting different digital values.
Figure BDA0003143057500000102
3. Peak value v of terminal voltage PK A sampling circuit as shown in fig. 10. In fig. 10, the IGBT terminal voltage v CE Firstly, obtaining signal level voltage v through resistance-capacitance voltage division CE,div Then, the peak value is detected and maintained through a peak value detection circuit consisting of two operational amplifiers to obtain v smp,PK . The peak value can then be converted to a value acceptable to the FPGA through an Analog-to-Digital Converter (ADC) PK A proportional digital quantity. v. of smp,PK And terminal voltage v PK Has the relationship of formula (5), wherein k V Is the resistance-capacitance voltage division ratio in fig. 10. And then v can be obtained PK Proportional value k between digital quantity output to FPGA by ADC PK As shown in formula (6), wherein k ADC Is the gain of the ADC input to the output. Equation (6) reflects the sampled digital quantity and the actual peak value v PK There is a simple proportional relationship between them, so v can be easily adjusted PK And (5) controlling.
According to the illustration of FIG. 2, to realize v PK The FPGA chip on the driving board can accurately control the digital quantity and the reference value V ref And carrying out Proportional-Integral (PI) operation on the corresponding digital quantity to obtain a corresponding driving voltage value. V ref Corresponding digital quantity N PK,ref Can be calculated according to equation (7).
v smp,PK ＝v PK k V (5)
k PK ＝k V k ADC (6)
N PK,ref ＝V ref k PK (7)。

Claims (4)

1. A grid driving method for accurately controlling IGBT peak voltage and improving switching characteristics is characterized by comprising the following steps:
step 1, accurately collecting the analog magnitude of the voltage peak value of the IGBT turn-off transient state terminal at each time through a peak voltage detection and digitization circuit;
step 2, digitalizing the peak value of the voltage at the turn-off transient state by an Analog-to-Digital Converter (ADC) to obtain the voltage v equal to the actual peak value PK A digital quantity proportional to the determined relationship;
step 3, outputting the digital quantity to a Field Programmable Gate Array (FPGA) chip (Field Programmable Gate Array, hereinafter referred to as FPGA) on a driving board;
step 4, the FPGA chip combines the digital quantity with the reference value V ref The corresponding digital quantity is subtracted, and then the Proportional-Integral PI operation is carried out to obtain the corresponding driving voltage value v G ；
Step 5, the digital quantity and the reference value V are processed by the FPGA chip in step 4 ref The corresponding digital quantity is used for proportional-integral PI operation to generate the turn-off transient di obtained by the PI regulator C Driving voltage during the/dt phase and di during the turn-off transient C The/dt stage is applied to the IGBT gate;
step 6, switching the command signal and the sampling signal di according to the PWM C Dt identifies the current IGBT stage, and thus the turn-off transient di C Control is applied at the/dt stage.
2. The gate driving method for accurately controlling peak voltage of IGBT to improve switching characteristics as claimed in claim 1, wherein said detecting di of turn-off transient C Dt stage to enable a delay stage for IGBT turn-off transients, dv CE Dt stage and di C The decoupling control is realized in three stages of the/dt stage, so that the v is accurately controlled PK Meanwhile, the turn-off delay and turn-off loss can be kept low.
3. The gate driving method for accurately controlling peak voltage of IGBT to improve switching characteristics as claimed in claim 1, wherein step 6 is performed on the turn-off transient di C Control may be applied during the/dt phase C Application of a high drive voltage v during the dt-phase G,ifH To obtain a small terminal voltage peak value v PK,L Or by applying a small value of the drive voltage v G,ifL To obtain a large terminal voltage peak value v PK,H (ii) a Or in the delay and dv CE The dt stage always applies the lowest driving voltage V EE So as to obtain the lowest turn-off delay and turn-off loss and realize the optimization of turn-off delay and loss.
4. The gate driving method for accurately controlling the peak voltage of the IGBT to improve the switching characteristics as claimed in claim 1, wherein the driving voltage value v is PK Under the self-regulation control, the device will convert v into V under the rated load current PK Control to V ref (ii) a In addition, the sum dv CE V of the/dt stage G Is kept at the lowest V EE To achieve minimal turn-off delay and loss.
CN202110746404.5A 2021-07-01 2021-07-01 Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics Active CN113411076B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110746404.5A CN113411076B (en) 2021-07-01 2021-07-01 Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110746404.5A CN113411076B (en) 2021-07-01 2021-07-01 Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics

Publications (2)

Publication Number Publication Date
CN113411076A CN113411076A (en) 2021-09-17
CN113411076B true CN113411076B (en) 2022-11-11

Family

ID=77681056

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110746404.5A Active CN113411076B (en) 2021-07-01 2021-07-01 Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics

Country Status (1)

Country Link
CN (1) CN113411076B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116207997B (en) * 2023-03-22 2024-03-08 国网智能电网研究院有限公司 Method and system for controlling turn-off of main branch full control valve of controllable commutation converter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104201871A (en) * 2014-08-26 2014-12-10 河海大学 FPGA (Field Programmable Gate Array) based high-voltage series connection (Insulated Gate Bipolar Transistor) gate driving unit and method
CN112910449A (en) * 2021-01-15 2021-06-04 青岛海信日立空调系统有限公司 Control circuit and air conditioner of IGBT turn-off voltage spike

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104201871A (en) * 2014-08-26 2014-12-10 河海大学 FPGA (Field Programmable Gate Array) based high-voltage series connection (Insulated Gate Bipolar Transistor) gate driving unit and method
CN112910449A (en) * 2021-01-15 2021-06-04 青岛海信日立空调系统有限公司 Control circuit and air conditioner of IGBT turn-off voltage spike

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
中高压大功率IGBT数字有源门极开环分级驱动技术;胡亮灯等;《电工技术学报》;20180319(第10期);全文 *
基于开关瞬态过程分析的母排杂散电感提取方法研究;冯高辉等;《中国电机工程学报》;20141225(第36期);全文 *

Also Published As

Publication number Publication date
CN113411076A (en) 2021-09-17

Similar Documents

Publication Publication Date Title
Zhang et al. Advanced active gate drive for switching performance improvement and overvoltage protection of high-power IGBTs
Fink et al. Advanced gate drive unit with closed-loop $ di_ {{C}}/dt $ control
Lobsiger et al. Closed-loop IGBT gate drive featuring highly dynamic di/dt and dv/dt control
Dang et al. Digital adaptive driving strategies for high-voltage IGBTs
US11709186B2 (en) Methods and circuitry for analyzing voltages
US11075627B2 (en) Methods and circuitry for driving a device
CN105932864B (en) A kind of intelligentized IGBT constant current driving device
Ling et al. A self-regulating gate driver for high-power IGBTs
Paredes et al. A new active gate driver for improving the switching performance of SiC MOSFET
CN109842279B (en) SiC MOSFET open-loop active driving circuit
CN113411076B (en) Gate driving method for accurately controlling IGBT peak voltage and improving switching characteristics
CN105743474B (en) Control to reverse-conducting IGBT
JP2009118650A (en) Power converter
US20180062510A1 (en) Methods and circuitry for sampling a signal
CN112821730A (en) Novel driving topology and driving method and crosstalk suppression method thereof
Alvarez et al. Sinusoidal current operation of delay-time compensation for parallel-connected IGBTs
Kuhn et al. Considerations for a digital gate unit in high power applications
Jiang et al. A new active gate driver for MOSFET to suppress turn-off spike and oscillation
Laumen et al. Closed-loop dv/dt control of SiC MOSFETs yielding minimal losses and machine degradation
Lobsiger Closed-loop igbt gate drive and current balancing concepts
CN113054972A (en) Silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) driving circuit for improving turn-on performance and control method
Ling et al. A novel digital active gate driver for high-power IGBT to reduce switching losses and stresses
Li et al. Optimal algorithm design based on a digitalized active voltage gate driver for IGBT turn-on transition
CN111697957B (en) Driving circuit applied to insulated gate bipolar transistor IGBT
Pan et al. Active variable gate drive for suppressing IGBT collector current overshoot

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant