CN113410361B - Light-emitting diode chip with composite protective layer and preparation method thereof - Google Patents

Light-emitting diode chip with composite protective layer and preparation method thereof Download PDF

Info

Publication number
CN113410361B
CN113410361B CN202110474799.8A CN202110474799A CN113410361B CN 113410361 B CN113410361 B CN 113410361B CN 202110474799 A CN202110474799 A CN 202110474799A CN 113410361 B CN113410361 B CN 113410361B
Authority
CN
China
Prior art keywords
layer
electrode
type
emitting diode
composite protective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110474799.8A
Other languages
Chinese (zh)
Other versions
CN113410361A (en
Inventor
兰叶
吴志浩
王江波
陶羽宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HC Semitek Zhejiang Co Ltd
Original Assignee
HC Semitek Zhejiang Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HC Semitek Zhejiang Co Ltd filed Critical HC Semitek Zhejiang Co Ltd
Priority to CN202110474799.8A priority Critical patent/CN113410361B/en
Publication of CN113410361A publication Critical patent/CN113410361A/en
Application granted granted Critical
Publication of CN113410361B publication Critical patent/CN113410361B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a light-emitting diode chip with a composite protective layer and a preparation method thereof, belonging to the field of light-emitting diode manufacture. The water-repellent film layer is laminated on the composite protective layer, and simultaneously, the water-repellent film layer also extends to the peripheral wall of the n electrode and the peripheral wall of the p electrode, so that the water-repellent film layer directly covers the first through hole and the second through hole of the composite protective layer, and the gaps between the n electrode and the p electrode isolate the gaps from the outside, so that water vapor is prevented from entering the inside of the light-emitting diode chip from the positions of the first through hole and the second through hole, the influence of the water vapor on the light-emitting diode chip can be reduced, and the service life of the light-emitting diode chip is prolonged. And the water repellent film layer is positioned on the surface of the composite protective layer, so that the possibility that water vapor enters the inside of the chip through the composite protective layer can be reduced, the service life of the composite protective layer can be prolonged to a certain extent, and the service life of the light-emitting diode chip can be prolonged.

Description

Light-emitting diode chip with composite protective layer and preparation method thereof
Technical Field
The present invention relates to the field of light emitting diode manufacturing, and in particular, to a light emitting diode chip with a composite protective layer and a method for manufacturing the same.
Background
A light emitting diode is a semiconductor electronic device capable of emitting light. As a novel efficient, environment-friendly and green solid-state lighting source, the solid-state lighting source is rapidly and widely applied to traffic lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlights, display screens and the like, and the improvement of the luminous efficiency of the light-emitting diode chip is a continuously pursued goal of the light-emitting diode.
The light-emitting diode chip is a basic structure for preparing a light-emitting diode, and comprises a support substrate, an n-type layer, a multiple quantum well layer, a p-type layer and a protective layer which are sequentially laminated on the support substrate, and an n electrode and a p electrode. The protective layer is provided with two through holes respectively corresponding to the n electrode and the p electrode, and the n electrode and the p electrode are respectively inserted into the two through holes and are respectively communicated with the n-type layer and the p-type layer.
After the LED chips are cut and formed, the LED chips are further required to be sorted by a sorting machine, and the ejector pins of the equipment are directly pricked on the front surface of the LED chips during sorting. The impact force of the thimble is relatively large, and the contacted material of the protective layer is easy to damage, even the protective layer is cracked. Part of water vapor or impurities may enter the inside of the light emitting diode chip from cracks on the protective layer, affecting the service life of the light emitting diode chip.
Disclosure of Invention
The embodiment of the disclosure provides a light-emitting diode chip with a composite protective layer and a preparation method thereof, which can reduce the probability of water vapor entering the inside of the light-emitting diode chip so as to prolong the service life of a finally obtained light-emitting diode. The technical scheme is as follows:
the embodiment of the disclosure provides a light emitting diode chip with a composite protective layer, which comprises a supporting substrate, an n-type layer, a multi-quantum well layer, a p-type layer, an n-electrode, a p-electrode and the composite protective layer,
the n-type layer, the multiple quantum well layer and the p-type layer are sequentially laminated on the supporting substrate along the growth direction of the n-type layer, the p-type layer is provided with a groove extending to the surface of the n-type layer, the composite protective layer covers the surface of the p-type layer, the n-electrode is positioned on the surface of the n-type layer exposed by the groove and fixed with the surface of the n-type layer exposed by the groove, the p-electrode is positioned on the surface of the p-type layer far away from the supporting substrate and fixed with the surface of the p-type layer far away from the supporting substrate,
the composite protective layer covers the surfaces of the p-type layer and the n-type layer, a first through hole sleeved on the n electrode is arranged on the composite protective layer, a second through hole sleeved on the p electrode is arranged on the composite protective layer,
the composite protective layer comprises a silicon oxide sub-layer, a borosilicate glass sub-layer and a silicon nitride sub-layer which are sequentially laminated along the growth direction of the n-type layer.
Optionally, the concentration of boron doped in the borosilicate glass sub-layer decreases in the growth direction of the n-type layer.
Optionally, the ratio of the thickness of the borosilicate glass sub-layer to the thickness of the silicon nitride sub-layer is 1.5:1 to 2.5:1.
Optionally, the borosilicate glass sub-layer has a thickness of 0.5um to 1.5um, and the silicon nitride sub-layer has a thickness of 0.2um to 0.4um.
Optionally, the light emitting diode chip further comprises a glass silicon layer laminated on the silicon nitride sub-layer.
Optionally, the thickness of the glass silicon layer is 1.8 um-2.2 um.
Optionally, the light emitting diode chip further comprises a transparent bonding layer, the transparent bonding layer is positioned between the support substrate and the n-type layer, and the material of the transparent bonding layer comprises SiO 2 、ZnO、SiN、ITO、In 2 O 3 、SnO 2 、TiO 2 、ZrO 2 And at least one of polyimide.
The embodiment of the disclosure provides a preparation method of a light emitting diode chip with a composite protective layer, which comprises the following steps:
providing a growth substrate and a support substrate;
sequentially growing an n-type layer, a multi-quantum well layer and a p-type layer on the growth substrate to obtain an epitaxial layer;
transferring the epitaxial layer to the support substrate;
forming a groove extending to the surface of the n-type layer on the p-type layer;
growing an n electrode on the surface of the n-type layer exposed by the groove, and growing a p electrode on the surface of the p-type layer away from the supporting substrate;
and forming a composite protective layer on the surfaces of the p-type layer and the n-type layer, which are exposed by the grooves, wherein the composite protective layer is provided with a first through hole sleeved on the n-electrode, and the composite protective layer is provided with a second through hole sleeved on the p-electrode.
Optionally, the preparation method further comprises:
forming a semi-cured glass silicon film on the composite protective layer;
sequentially splitting and sorting the light emitting diode chips;
and completely curing the semi-cured glass silicon film to form a glass silicon layer.
Optionally, the fully curing the semi-cured glass silicon film forms a glass silicon layer, including:
and irradiating the semi-cured glass silicon film for 0.15-0.25 s by laser so as to completely cure the glass silicon film to form a glass silicon layer.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
the conventional silicon oxide protective layer is changed into a composite protective layer, and the composite protective layer comprises a silicon oxide sub-layer, a borosilicate glass sub-layer and a silicon nitride sub-layer which are sequentially laminated along the growth direction of the n-type layer. The silicon oxide sub-layer can realize effective protection of the inside of the light emitting diode chip. The borosilicate glass sub-layer on the silicon oxide sub-layer has certain flexibility, can better release impact force, and reduces the possibility of cracks in the silicon oxide sub-layer and the composite protective layer. The compactness of the silicon nitride sub-layer on the borosilicate glass sub-layer is better, and the thimble of the sorting machine can be well blocked. The silicon nitride sub-layer is positioned at the outermost side, so that the initial impact of the thimble can be relieved, and the toughness of the borosilicate glass sub-layer can release the impact of the thimble. The influence of the thimble on the final silicon oxide sublayer is greatly weakened, the integrity of the finally obtained composite protective layer is ensured, and the inside of the light-emitting diode chip is well protected.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of another light emitting diode chip according to an embodiment of the disclosure;
fig. 3 is a flowchart of a light emitting diode chip with a composite protective layer and a method for manufacturing the same according to an embodiment of the present disclosure;
fig. 4 is a flowchart of another light emitting diode chip with a composite protective layer and a method for manufacturing the same according to an embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present disclosure will be described in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present disclosure, and referring to fig. 1, the embodiment of the present disclosure provides a light emitting diode chip, which includes a support substrate 1, an n-type layer 2, a multiple quantum well layer 3, a p-type layer 4, an n-electrode 5, a p-electrode 6, and a composite protection layer 7.
The n-type layer 2, the multiple quantum well layer 3 and the p-type layer 4 are sequentially laminated on the supporting substrate 1 along the growth direction of the n-type layer 2, the p-type layer 4 is provided with a groove S extending to the surface of the n-type layer 2, the composite protective layer 7 covers the surface of the p-type layer 4, the n electrode 5 is positioned on the surface of the n-type layer 2 exposed by the groove S and fixed with the surface of the n-type layer 2 exposed by the groove S, and the p electrode 6 is positioned on the surface of the p-type layer 4 away from the supporting substrate 1 and fixed with the surface of the p-type layer 4 away from the supporting substrate 1.
The composite protective layer 7 covers the surfaces of the p-type layer 4 and the n-type layer 2, the composite protective layer 7 is provided with a first through hole 7a sleeved on the n electrode 5, and the composite protective layer 7 is provided with a second through hole 7b sleeved on the p electrode 6. The composite protective layer 7 includes a silicon oxide sub-layer 701, a borosilicate glass sub-layer 702, and a silicon nitride sub-layer 703, which are sequentially stacked in the growth direction of the n-type layer 2.
The conventional silicon oxide protective layer is changed to the composite protective layer 7, and the composite protective layer 7 includes a silicon oxide sub-layer 701, a borosilicate glass sub-layer 702, and a silicon nitride sub-layer 703, which are sequentially stacked in the growth direction of the n-type layer 2. The silicon oxide sub-layer 701 can realize effective protection of the inside of the light emitting diode chip. The borosilicate glass sub-layer 702 on the silicon oxide sub-layer 701 has certain flexibility, can better release impact force, and reduces the possibility of cracks in the silicon oxide sub-layer 701 and the composite protective layer 7. The compactness of the silicon nitride sub-layer 703 on the borosilicate glass sub-layer 702 is better, and the ejector pins of the classifier can be well blocked. The silicon nitride sub-layer 703 is located at the outermost side, so as to relieve the initial impact of the thimble, and the toughness of the borosilicate glass sub-layer 702 can release the impact of the thimble. The influence of the thimble on the final silicon oxide sublayer 701 is greatly weakened, so that the finally obtained composite protective layer 7 is ensured to be more complete, and a good protective effect is achieved on the inside of the light-emitting diode chip.
The thickness of the composite protective layer 7 is illustratively 2.8um to 4.8um.
When the thickness of the composite protective layer 7 is within the above range, the internal structure of the light emitting diode chip can be effectively protected without excessively increasing the manufacturing cost of the light emitting diode chip.
Alternatively, the silicon oxide sub-layer 701 may have a thickness of 0.3um to 0.7um.
The thickness of the silicon oxide sub-layer 701 is within the above range, so that the inside of the light emitting diode chip can be effectively protected, the thickness of the silicon oxide sub-layer 701 is reasonable, and the preparation cost of the light emitting diode chip is low.
Optionally, the ratio of the thickness of borosilicate glass sub-layer 702 to the thickness of silicon nitride sub-layer 703 is 1.5:1 to 2.5:1.
When the ratio of the thickness of the borosilicate glass sub-layer 702 to the thickness of the silicon nitride sub-layer 703 is within the above range, the influence caused by the ejector pins can be effectively blocked, the impact caused by the ejector pins can be released, and the finally obtained composite protective layer 7 can be ensured to effectively protect the inside of the light emitting diode chip.
Illustratively, borosilicate glass sub-layer 702 has a thickness of 0.5um to 1.5um and silicon nitride sub-layer 703 has a thickness of 0.2um to 0.4um.
The thickness of the borosilicate glass sub-layer 702 and the thickness of the silicon nitride sub-layer 703 are respectively in the above ranges, so that the borosilicate glass sub-layer is suitable for protecting light emitting diode chips with most thickness specifications, and the manufacturing cost of the light emitting diode chips is not excessively increased.
Optionally, the concentration of doped boron in borosilicate glass sub-layer 702 decreases in the growth direction of n-type layer 2.
The concentration of boron doped in borosilicate glass sub-layer 702 affects the overall hardness of borosilicate glass sub-layer 702, and the higher concentration of boron doped on the side of borosilicate glass sub-layer 702 near multi-quantum well layer 3, the higher flexibility of borosilicate glass sub-layer 702, can achieve good contact with silicon oxide sub-layer 701, and can release impact more effectively. The boron doped on the side of the borosilicate glass sub-layer 702, which is close to the silicon nitride sub-layer 703, has lower boron concentration, so that the borosilicate glass sub-layer 702 has higher hardness, can effectively resist the impact from the thimble, and can play a good role in protection.
Illustratively, the boron doped in borosilicate glass sub-layer 702 has a concentration of 8% to 20%.
When the concentration of the doped boron in the borosilicate glass sub-layer 702 is within the above range, the flexibility of the borosilicate glass sub-layer 702 is reasonable, so that the borosilicate glass sub-layer can effectively resist impact, can release a certain impact, and can more effectively protect the light-emitting diode chip.
Fig. 2 is a schematic structural diagram of another light emitting diode chip according to an embodiment of the disclosure, and referring to fig. 2, it can be appreciated that in another implementation manner of the disclosure, the light emitting diode chip may include a support substrate 1, a transparent adhesive layer 8, an n-AlGaInP current spreading layer 9, an n-type layer 2, a multiple quantum well layer 3, a p-type layer 4, a p-type GaP ohmic contact layer 10, a glass silicon layer 11, an n-electrode 5, a p-electrode 6, a bragg mirror 12, and a composite protection layer 7.
An n-AlGaInP current spreading layer 9, an n-type layer 2, a multiple quantum well layer 3, a p-type layer 4, and a p-type GaP ohmic contact layer 10 are sequentially laminated on a support substrate 1 along the growth direction of the n-type layer 2.
The p-type layer 4 is provided with a groove S extending to the surface of the n-type layer 2, the composite protective layer 7 covers the surface of the p-type layer 4, and the n-electrode 5 is positioned on the surface of the n-type layer 2 exposed by the groove S and fixed with the surface of the n-type layer 2 exposed by the groove S. The p electrode 6 is located on the surface of the p-type GaP ohmic contact layer 10 remote from the support substrate 1, and is fixed to the surface of the p-type GaP ohmic contact layer 10 remote from the support substrate 1.
The composite protective layer 7 covers the surfaces of the p-type layer 4 and the n-type layer 2, the composite protective layer 7 is provided with a first through hole 7a sleeved on the n electrode 5, and the composite protective layer 7 is provided with a second through hole 7b sleeved on the p electrode 6. The glass-silicon layer 11 covers the composite protective layer 7 and likewise leaves two holes corresponding to the n-electrode 5 and the p-electrode 6, respectively.
It should be noted that the structure of the composite protective layer 7 shown in fig. 2 is the same as that of the composite protective layer 7 shown in fig. 1, and thus a detailed description thereof is omitted herein.
Alternatively, the support substrate 1 may be a sapphire support substrate 1. Easy manufacture and acquisition and better light transmittance.
Illustratively, a transparent bonding layer 8 is positioned between the support substrate 1 and the n-AlGaInP current spreading layer 9, the material of the transparent bonding layer 8 comprising SiO 2 、ZnO、SiN、ITO、In 2 O 3 、SnO 2 、TiO 2 、ZrO 2 And at least one of polyimide.
The addition of the transparent bonding layer 8 can relieve lattice mismatch between the epitaxial structure and the supporting substrate 1, is favorable for realizing transfer and bonding of the epitaxial structure, can play a role in releasing heat to a certain extent, and ensures that the quality of the finally obtained light-emitting diode chip is better. The transparent bonding layer 8 is prepared by adopting at least one of the materials, so that the transparent bonding layer 8 with better quality can be obtained, and good connection with other materials can be realized.
In the case where the led chip does not include the n-AlGaInP current spreading layer 9, the transparent adhesive layer 8 is located between the support substrate 1 and the n-type layer 2.
Optionally, the thickness of the transparent adhesive layer 8 is 2.8um to 3.2um.
When the thickness of the transparent adhesive layer 8 is within the above range, the transparent adhesive layer 8 can be applied to light-emitting diode chips of most thickness specifications, and the quality of the transparent adhesive layer 8 itself is good.
Alternatively, the thickness of the n-type AlGaInP current spreading layer 9 is 3-3.5 um. The quality of the obtained light-emitting diode chip is better.
Alternatively, the n-type layer 2 may be an n-type AlInP confining layer having a thickness of 200 to 300nm. The quality of the obtained light-emitting diode chip is better.
Alternatively, the multiple quantum well layer 3 is provided to include a plurality of periodically alternately grown AlGaInP well layers and AlGaInP barrier layers, the AlGaInP well layers being different from the composition of Al in the AlGaInP barrier layers.
Illustratively, the overall thickness of the multiple quantum well layer 3 may be 160 to 200nm.
Alternatively, the p-type layer 4 may be a p-type AlInP confining layer having a thickness of 200 to 300nm. The quality of the obtained light-emitting diode chip is better.
Alternatively, the thickness of the p-type GaP ohmic contact layer 10 is 500to 1000nm.
The thickness of the p-type ohmic contact layer 10 can meet the requirement of preparing the p-type electrode 6 on the p-type ohmic contact layer 10, and the overall quality of the p-type ohmic contact layer 10 with the thickness within the range is good, so that the stable preparation and connection of the p-type electrode 6 can be ensured, and the luminous efficiency of the finally obtained light-emitting diode can be ensured.
Optionally, the light emitting diode chip further comprises a glass-silicon layer 11, the glass-silicon layer 11 being laminated on the silicon nitride sub-layer 703.
The glass silicon layer 11 can further protect the composite protective layer 7, so as to reduce the possibility of damaging the composite protective layer 7 and improve the protection capability of the inside of the light emitting diode chip. The glass silicon layer 11 has better light transmittance, insulativity and chemical stability, and can improve the protection capability of the light-emitting diode chip and simultaneously can not greatly influence the light-emitting rate of the light-emitting diode.
Note that, the material of the glass-silicon layer 11 is SOG (silicon on glass), and SOG refers to a silicon material on glass.
Alternatively, the thickness of the glass silicon layer 11 is 1.8um to 2.2um.
When the thickness of the glass silicon layer 11 is within the above range, the protection capability of the light emitting diode chip can be effectively improved, and the manufacturing cost of the light emitting diode chip can not be excessively increased.
Illustratively, the material of the p-electrode 6 may include a Cr metal layer and an Au metal layer sequentially stacked, and the thicknesses of the Cr metal layer and the Au metal layer are 20 to 50nm, 3000 to 4500nm, respectively. The quality of the p-electrode 6 can be ensured to be good.
Illustratively, the n-electrode 5 is formed by sequentially stacking a supporting Au metal layer, an AuGeNi metal layer and a second Au metal layer, wherein the thicknesses of the supporting Au metal layer, the AuGeNi metal layer and the second Au metal layer are 10 to 30, 120 to 200 and 160 to 300nm, respectively. The quality of the n-electrode 5 can be ensured to be good.
In other implementations provided by the present disclosure, the material of the electrodes may also include one or more of Cr, au, ge, ni, which is not limited by the present disclosure.
It should be noted that, the p-electrode 6 and the n-electrode 5 may each include a primary electrode and a pad, the primary electrode is located in a through hole formed between the bragg mirror 12 and the composite protective layer 7, the pad is located on the p-type layer 4 and connected to the primary electrode, and the orthographic projection of the pad on the surface of the support substrate 1 is greater than the orthographic projection of the primary electrode on the surface of the support substrate 1.
The electrode adopts the structure described in the upper position, so that the space occupied by the primary electrode can be reduced, the light absorption and blocking effect in the light-emitting diode chip is ensured to be small, and most of light rays can be reflected to the light-emitting surface by the Bragg reflector 12.
The epitaxial wafer structure shown in fig. 2 is formed by adding an n-AlGaInP current spreading layer 9 between the support substrate 1 and the n-type layer 2, compared to the epitaxial wafer structure shown in fig. 1. A p-type GaP ohmic contact layer 10, a bragg mirror 12 and a glass silicon layer 11 are also grown on the p-type layer 4. The quality and luminous efficiency of the epitaxial wafer obtained as a whole are better. And the chip provided in fig. 2 is a flip chip, but in other implementations provided by the present disclosure, the chip may also be a front-mounted chip.
It should be noted that, in other implementations provided in the present disclosure, the light emitting diode chip may also include other hierarchies, which is not limited in this disclosure. In practice, in other implementations provided by the present disclosure, the main material of the light emitting diode chip may be aluminum gallium arsenide or gallium nitride, which is not limited herein.
Fig. 3 is a flowchart of a light emitting diode chip with a composite protective layer and a method for manufacturing the same according to an embodiment of the present disclosure, where, as shown in fig. 3, the light emitting diode chip with a composite protective layer and the method for manufacturing the same include:
s101: a growth substrate and a support substrate are provided.
S102: and sequentially growing an n-type layer, a multi-quantum well layer and a p-type layer on the growth substrate to obtain an epitaxial layer.
S103: the epitaxial layer is transferred to a support substrate.
S104: a recess is formed on the p-type layer extending to a surface of the n-type layer.
S105: an n-electrode is grown on the surface of the n-type layer exposed by the recess, and a p-electrode is grown on the surface of the p-type layer remote from the support substrate.
S106: and forming a composite protective layer on the surfaces of the p-type layer and the n-type layer, which are exposed by the grooves, wherein the composite protective layer is provided with a first through hole sleeved on the n-electrode, and the composite protective layer is provided with a second through hole sleeved on the p-electrode.
The technical effects of the preparation method shown in fig. 3 may correspond to those of the led chip shown in fig. 1, and thus the technical effects of fig. 3 are not described herein.
The led chip structure after the step S106 is performed can be seen in fig. 1.
Fig. 4 is a flowchart of another light emitting diode chip with a composite protective layer and a method for manufacturing the same according to an embodiment of the present disclosure, as shown in fig. 4, the light emitting diode chip with a composite protective layer and the method for manufacturing the same include:
s201: a growth substrate and a support substrate are provided.
Wherein the support substrate may be a sapphire support substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: the surface of the support substrate is treated for 6-10 min under the hydrogen atmosphere.
Illustratively, the temperature of the reaction chamber may be 1000-1200 ℃ and the pressure of the reaction chamber may be 200-500 Torr when treating the surface of the support substrate.
S202: and sequentially growing a GaInP layer, a GaAs layer, an n-type AlGaInP current expansion layer, an n-type AlInP limiting layer, a multiple quantum well layer, a p-type AlInP limiting layer and a p-type GaP ohmic contact layer on the growth substrate to obtain an epitaxial layer laminated on the growth substrate.
Firstly, a GaInP layer and a GaAs layer are grown on a growth substrate, and then other epitaxial structures are continuously grown on the GaAs layer, so that the obtained epitaxial layer has good overall quality, and the transfer and the subsequent preparation of the epitaxial layer are facilitated.
It should be noted that all epitaxial structures grown on the substrate are collectively referred to as an epitaxial layer, and in the embodiments provided by the present disclosure, the epitaxial wafer includes a support substrate and an epitaxial layer on the support substrate.
For ease of understanding, in the implementation provided in the present disclosure, the growth conditions of the GaInP layer, gaAs layer, n-type AlGaInP current spreading layer, n-type AlInP limiting layer, multiple quantum well layer, p-type AlInP limiting layer, and p-type GaP ohmic contact layer to obtain the epitaxial layer deposited on the growth substrate may be as follows:
illustratively, the growth conditions of the GaInP layer include: the growth temperature is 650-670 ℃, the thickness is 150-300nm, the V/III is 20-30, and the growth rate is 0.5-0.8nm/s.
Alternatively, the growth conditions of the GaAs buffer layer include: the growth temperature is 650-670 ℃, the thickness is 150-300nm, the V/III is 20-30, and the growth rate is 0.5-0.8nm/s.
Optionally, the growth conditions of the n-type AlGaInP current spreading layer include: the growth temperature is 670-680 ℃, the thickness is 3-3.5um, the V/III is 40-50, the growth rate is 1.2-1.7nm/s, and the carrier concentration is 1-2 e18.
Alternatively, the growth conditions of the n-type AlInP confining layer include: the growth temperature is 670-680 ℃, the thickness is 250-350nm, the V/III is 40-50, the growth rate is 1.2-1.7nm/s, and the carrier concentration is 1-2 e18.
Optionally, the growth conditions of the AlGaInP well layer and the AlGaInP barrier layer in the multiple quantum well layer include: the growth temperature is 650-660 ℃, the thickness is 20-22nm, the V/III is 40-50, and the growth rate is 1-2nm/s. The multi-quantum well layer with better quality can be obtained.
Alternatively, the growth conditions of the p-type AlInP confining layer include: the growth temperature is 670-680 ℃, the thickness is 350-450nm, the V/III is 40-50, the growth rate is 1.2-1.7nm/s, and the carrier concentration is 1-2 e18.
Optionally, the growth conditions of the p-type GaP ohmic contact layer include: the growth temperature is 670-680 ℃, the thickness is 350-450nm, the V/III is 40-50, the growth rate is 1.2-1.7nm/s, and the carrier concentration is 1-2 e18.
Illustratively, the growth temperature of the p-type GaP ohmic contact layer decreases as the growth time of the p-type GaP ohmic contact layer increases until the p-type GaP ohmic contact layer is formed.
The growth temperature of the p-type GaP ohmic contact layer is reduced, the surface quality of the p-type GaP ohmic contact layer is slightly reduced, the surface of the p-type GaP ohmic contact layer is naturally roughened, and the total reflection condition can be reduced.
S203: and stripping the epitaxial layer and the growth substrate and removing the GaInP layer and the GaAs layer in the epitaxial layer.
Optionally, after the epitaxial layer and the growth substrate are stripped, the GaInP layer and the GaAs layer in the epitaxial layer are removed, so that the subsequent transfer and treatment of the epitaxial layer can be facilitated, and the influence of the GaInP layer and the GaAs layer on the light emitting effect of the light emitting diode chip is avoided.
Step S203 may include: adhering the p-type GaP ohmic contact layer in the epitaxial layer with the transition substrate through photoresist; thermally decomposing the growth substrate and the GaInP layer; and taking the transition substrate as a support, and removing the GaInP layer and the GaAs layer by a wet method. The epitaxial layer with better quality can be conveniently obtained, and the preparation of the light-emitting diode chip is convenient.
Alternatively, the transition substrate may be a sapphire substrate or a substrate of other materials.
S204: a transparent adhesive layer is grown on the support substrate.
Optionally, the material of the transparent bonding layer is silicon oxide, and the growth conditions of the transparent bonding layer include: the growth temperature was 200 degrees. A transparent adhesive layer of good quality can be obtained.
Illustratively, the transparent bonding layer grows in a mixed gas environment of laughing gas and ammonia gas, wherein the volume ratio of laughing gas to ammonia gas is 20:1. A transparent adhesive layer of good quality can be obtained.
S205: the epitaxial layer is transferred to a support substrate and the n-type AlGaInP current spreading layer in the epitaxial layer is in direct contact with the transparent bonding layer.
Step S205 may include: bonding and connecting the n-type AlGaInP current expansion layer with the transparent conductive layer on the support substrate; and removing the transition substrate on the other side of the epitaxial layer. Good connection between the epitaxial layer and the support substrate is facilitated.
Alternatively, the n-type AlGaInP current spreading layer is bonded to the transparent adhesive layer on the support substrate by applying pressure. Good connection between the n-type AlGaInP current spreading layer and the transparent adhesive layer on the support substrate can be ensured.
S206: a groove extending to the n-type AlInP confinement layer is formed on the p-type GaP ohmic contact layer.
Step S206 includes: coating photoresist on a part of the p-type GaP ohmic contact layer; after the photoresist is exposed and developed, grooves are etched in the portions of the p-type GaP ohmic contact layer, which are not covered by the photoresist, and extend to the n-type AlInP limiting layer.
S207: and forming a p electrode on the p-type GaP ohmic contact layer, and forming an n electrode on the surface of the n-type AlInP limiting layer exposed by the groove.
The p electrode occupies only a part of the surface of the p-type GaP ohmic contact layer, and the n electrode occupies only a part of the exposed surface of the n-type AlInP confining layer.
Alternatively, both the p-electrode and the n-electrode may be obtained by evaporation.
S208: and sequentially forming a Bragg reflector and a composite protective layer on the p-type GaP ohmic contact layer.
Alternatively, the Bragg reflector comprises an AlGaAs/AlAs superlattice structure.
The growth temperature of the bragg mirror is, for example, 600 to 800 degrees. The quality of the obtained Bragg reflector is good.
When the bragg reflector grows specifically, two sub-layer materials of the bragg reflector need to be alternately introduced into the reaction cavity so as to finally obtain the bragg reflector.
It should be noted that holes corresponding to the n electrode and the p electrode need to be left on the bragg reflector, and the holes can be prepared through a photolithography process.
S209: forming a semi-cured glass silicon film on the composite protective layer; sequentially splitting and sorting the light-emitting diode chips; the semi-cured glass silicon film is fully cured to form a glass silicon layer.
The semi-cured glass silicon film is formed on the composite protective layer, then splitting and sorting are carried out, the semi-cured glass silicon film has certain fluidity, has better bearing capacity on the impact of the ejector pin, has repairable possibility after sorting, and can ensure the quality of the finally obtained light-emitting diode chip.
Illustratively, the forming of the semi-cured glass silicon film comprises: spin coating on the composite protective layer to obtain a glass silicon solution; and heating the glass silicon solution for 0.5-1.5 h at the temperature of 100-200 ℃. A semi-cured glass silicon film can be obtained.
Optionally, fully curing the semi-cured glass silicon film to form a glass silicon layer, comprising:
and irradiating the semi-cured glass silicon film for 0.15-0.25 s by laser so as to completely cure the glass silicon film to form a glass silicon layer. The structure of the finally obtained glass silicon film can be ensured to be stable.
Illustratively, step S209 further includes: after forming the semi-cured glass silicon film, the thickness of the support substrate is thinned before sequentially splitting and sorting the light emitting diode chips. The light absorption condition of the supporting substrate can be reduced, and the light extraction efficiency is improved.
In one implementation provided by the present disclosure, the thickness of the support substrate after thinning may be 80um.
The structure of the led chip after the execution of step S209 can be seen in fig. 2.
It should be noted that, in the embodiment of the present disclosure, the light emitting diode is implemented by using a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition ) deviceA method for growing a tube. Adopts high-purity H 2 (Hydrogen) or high purity N 2 (Nitrogen) or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 As N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, silane (SiH 4) as N-type dopant, trimethylaluminum (TMAL) as aluminum source, magnesium-cyclopentadienyl (CP 2 Mg) as P-type dopant.
While the present disclosure has been described above by way of example, and not by way of limitation, any person skilled in the art will recognize that many modifications, adaptations, and variations of the present disclosure can be made to the present embodiments without departing from the scope of the present disclosure.

Claims (10)

1. A light emitting diode is characterized in that the light emitting diode comprises a supporting substrate, an epitaxial layer, an n electrode, a p electrode and a composite protective layer,
the epitaxial layer is positioned on the supporting substrate, the n electrode and the p electrode are both positioned on the surface of the epitaxial layer, the composite protective layer covers the surface of the epitaxial layer, the composite protective layer is provided with a first through hole sleeved on the n electrode, the composite protective layer is provided with a second through hole sleeved on the p electrode,
the composite protective layer comprises a silicon oxide sub-layer, a borosilicate glass sub-layer and a silicon nitride sub-layer which are sequentially laminated along the growth direction of the epitaxial layer, and the concentration of boron doped in the borosilicate glass sub-layer is reduced in the growth direction of the n-type layer.
2. The light emitting diode of claim 1, wherein the epitaxial layer comprises: the n-type layer, the multiple quantum well layer and the p-type layer are sequentially laminated on the supporting substrate along the growth direction of the n-type layer, the p-type layer is provided with grooves extending to the surface of the n-type layer, the composite protective layer covers the surface of the p-type layer, the n-electrode is positioned on the surface of the n-type layer exposed by the grooves and fixed with the surface of the n-type layer exposed by the grooves, and the p-electrode is positioned on the surface of the p-type layer far away from the supporting substrate and fixed with the surface of the p-type layer far away from the supporting substrate.
3. The led of claim 1, wherein the ratio of the thickness of the borosilicate glass sub-layer to the thickness of the silicon nitride sub-layer is 1.5:1 to 2.5:1.
4. A light emitting diode according to any one of claims 1 to 3 wherein the borosilicate glass sub-layer has a thickness of 0.5um to 1.5um and the silicon nitride sub-layer has a thickness of 0.2um to 0.4um.
5. A light emitting diode according to any one of claims 1 to 3 further comprising a glass silicon layer laminated on the silicon nitride sub-layer.
6. The led of claim 5, wherein the glass-silicon layer has a thickness of 1.8um to 2.2um.
7. A light emitting diode according to any one of claims 1 to 3 further comprising a transparent adhesive layer between the support substrate and the n-type layer, the material of the transparent adhesive layer comprising SiO 2 、ZnO、SiN、ITO、In 2 O 3 、SnO 2 、TiO 2 、ZrO 2 And at least one of polyimide.
8. A method of manufacturing a light emitting diode, the method comprising:
providing a growth substrate and a support substrate;
sequentially growing an n-type layer, a multi-quantum well layer and a p-type layer on the growth substrate to obtain an epitaxial layer;
transferring the epitaxial layer to the support substrate;
forming a groove extending to the surface of the n-type layer on the p-type layer;
growing an n electrode on the surface of the n-type layer exposed by the groove, and growing a p electrode on the surface of the p-type layer away from the supporting substrate;
and forming a composite protective layer on the surfaces of the p-type layer and the n-type layer exposed by the grooves, wherein a first through hole sleeved on the n-electrode is formed in the composite protective layer, a second through hole sleeved on the p-electrode is formed in the composite protective layer, the composite protective layer comprises a silicon oxide sub-layer, a borosilicate glass sub-layer and a silicon nitride sub-layer which are sequentially stacked along the growth direction of the epitaxial layer, and the concentration of doped boron in the borosilicate glass sub-layer is reduced in the growth direction of the n-type layer.
9. The method of manufacturing according to claim 8, further comprising:
forming a semi-cured glass silicon film on the composite protective layer;
sequentially splitting and sorting the light emitting diodes;
and completely curing the semi-cured glass silicon film to form a glass silicon layer.
10. The method of claim 9, wherein the fully curing the semi-cured glass-silicon film to form a glass-silicon layer comprises:
and irradiating the semi-cured glass silicon film for 0.15-0.25 s by laser so as to completely cure the glass silicon film to form a glass silicon layer.
CN202110474799.8A 2021-04-29 2021-04-29 Light-emitting diode chip with composite protective layer and preparation method thereof Active CN113410361B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110474799.8A CN113410361B (en) 2021-04-29 2021-04-29 Light-emitting diode chip with composite protective layer and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110474799.8A CN113410361B (en) 2021-04-29 2021-04-29 Light-emitting diode chip with composite protective layer and preparation method thereof

Publications (2)

Publication Number Publication Date
CN113410361A CN113410361A (en) 2021-09-17
CN113410361B true CN113410361B (en) 2023-06-09

Family

ID=77677754

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110474799.8A Active CN113410361B (en) 2021-04-29 2021-04-29 Light-emitting diode chip with composite protective layer and preparation method thereof

Country Status (1)

Country Link
CN (1) CN113410361B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108161A (en) * 2004-09-30 2006-04-20 Toyoda Gosei Co Ltd Semiconductor light-emitting device
CN101656283A (en) * 2008-08-22 2010-02-24 奇力光电科技股份有限公司 Light-emitting diode assembly and manufacturing method thereof
CN102468391A (en) * 2010-11-03 2012-05-23 佛山市奇明光电有限公司 Light-emitting diode structure, and manufacturing method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW469511B (en) * 1999-07-26 2001-12-21 Agency Ind Science Techn ZnO compound-based semiconductor light emitting element, and manufacturing process therefor
JP2005019981A (en) * 2003-06-05 2005-01-20 Matsushita Electric Ind Co Ltd Fluorescent material, semiconductor light-emitting element and method of fabricating these
US7166483B2 (en) * 2004-06-17 2007-01-23 Tekcore Co., Ltd. High brightness light-emitting device and manufacturing process of the light-emitting device
JP2011023703A (en) * 2009-06-17 2011-02-03 Sumitomo Electric Ind Ltd Epitaxial substrate, light-emitting element, light-emitting device, and method for producing epitaxial substrate
US8211722B2 (en) * 2009-07-20 2012-07-03 Lu Lien-Shine Flip-chip GaN LED fabrication method
CN110212071B (en) * 2019-05-22 2020-07-07 华灿光电（浙江）有限公司 Light emitting diode chip and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108161A (en) * 2004-09-30 2006-04-20 Toyoda Gosei Co Ltd Semiconductor light-emitting device
CN101656283A (en) * 2008-08-22 2010-02-24 奇力光电科技股份有限公司 Light-emitting diode assembly and manufacturing method thereof
CN102468391A (en) * 2010-11-03 2012-05-23 佛山市奇明光电有限公司 Light-emitting diode structure, and manufacturing method thereof

Also Published As

Publication number Publication date
CN113410361A (en) 2021-09-17

Similar Documents

Publication Publication Date Title
CN1172380C (en) High brightness luminescence device
US8735185B2 (en) Light emitting device and fabrication method thereof
CN101359710B (en) Manufacturing method of green light LED
KR100631414B1 (en) Semiconductor light emitting diode and method of manufacturing the same
JP6419077B2 (en) Wavelength conversion light emitting device
US20150280057A1 (en) Methods of forming planar contacts to pseudomorphic electronic and optoelectronic devices
US20070246700A1 (en) Light Emitting Device and Method of Manufacturing the Same
JP2001007393A (en) ALGaInN-BASED LED WITH EPITAXIAL LAYER
US20050017253A1 (en) Nitride-based compound semiconductor light-emitting device and method of fabricating the same
TWI455357B (en) Light emitting device and method of manufacturing the same
US8482034B2 (en) Light emitting device
KR101123010B1 (en) semi-conductor light emitting device and manufacturing method thereof
US8618563B2 (en) Light emitting device with vertically adjustable light emitting pattern
US20240120444A1 (en) Light emitting device and method for manufacturing the same
KR20130066308A (en) Light emitting device
WO2017157073A1 (en) Light-emitting diode and method for manufacturing same
CN112259652A (en) Micro-LED chip structure capable of reducing side wall defect recombination and preparation method
CN113410361B (en) Light-emitting diode chip with composite protective layer and preparation method thereof
TWI437731B (en) Semiconductor optoelectronic device with enhanced light extraction efficiency and fabricating method thereof
JP5379703B2 (en) Ultraviolet semiconductor light emitting device
CN113380931A (en) Red light emitting diode chip capable of improving luminous efficiency and preparation method thereof
KR20090121812A (en) Method of manufacturing an ultraviolet light emitting device
CN114899283A (en) Preparation method of red light diode chip for improving bonding quality
KR101046109B1 (en) Nitride semiconductor devices
KR20090003384A (en) Nitride light emitting device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant