CN113410097B - Matrix control circuit and method based on magnetic latching relay switch radio frequency front end - Google Patents
Matrix control circuit and method based on magnetic latching relay switch radio frequency front end Download PDFInfo
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- CN113410097B CN113410097B CN202110647423.2A CN202110647423A CN113410097B CN 113410097 B CN113410097 B CN 113410097B CN 202110647423 A CN202110647423 A CN 202110647423A CN 113410097 B CN113410097 B CN 113410097B
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- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/001—Functional circuits, e.g. logic, sequencing, interlocking circuits
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Abstract
The invention provides a matrix control circuit and a method based on a magnetic latching relay switch radio frequency front end, wherein the circuit comprises a cascaded combinational logic circuit and a switch control network; the combinational logic circuit decodes the alpha control signal and the beta control signal to generate N control signals and M control signals; the switch control network is an array control network formed by NxM switch coils, and a power switch control circuit and an OC signal generating circuit which are connected with the array control network; the power switch control circuit receives the N paths of control signals and outputs N paths of packet voltages to the array control network; the OC signal generating circuit receives the M control signals and outputs the M OC signals to the array control network; after N multiplied by M switch wire packets in the array control network receive the N route packet voltage and the M route OC signals, the N multiplied by M route control signals are output to the magnetic latching relay switch. The circuit has the advantages of simple structure, clear control logic and wide applicability.
Description
Technical Field
The invention relates to the technical field of control of radio frequency front-end products, in particular to a matrix type control circuit and a matrix type control method based on a magnetic latching relay switch radio frequency front end.
Background
The existing radio frequency front end generally integrates more switches inside, and is mainly used for internal radio frequency path selection and synthesis. The switches commonly used are electrical switches, the drive level of which is usually either the cmos level or the TTL level. In the high-reliability application fields of aerospace, satellite borne and the like, a switch used at the radio frequency front end is usually a mechanical switch or a magnetic latching relay switch, and the driving mode of the switch is usually an OC signal. With the continuous improvement of the functions of the radio frequency system, the functions of the radio frequency front end are more and more complex, the number of switches integrated inside is dozens of switches, and more switches are hundreds of switches. However, in application scenarios such as aerospace, satellite-borne, etc., the use of complex processing devices such as FPGAs, CPLDs, etc. is greatly limited due to the susceptibility to cosmic rays, and some occasions are even prohibited to ensure reliability. In this scenario, a discrete logic gate device combination driving circuit is mainly adopted to realize the switch driving and control of the radio frequency front end. The advantages and disadvantages of each driving mode are summarized as follows:
the FPGA, the CPLD and other complex processors are used for driving and controlling, the circuit integration level is high, the size is small, the weight is light, the programmable capability is strong, the fan-out capability of the driving port is strong, and the application flexibility is great. The defects are high cost, large power consumption, easy influence of cosmic rays in the application fields of spaceflight, spaceborne and the like and reduced reliability.
The discrete logic gate devices are combined with the driving circuit, so that the logic relation is complex, the circuit integration level is low, the scale is large, the size and the weight are large, the programmable capacity is not available, and the use flexibility is poor. The method has the advantages of high reliability and wide application in the fields of spaceflight and satellite borne.
Disclosure of Invention
The invention aims to provide a matrix control circuit and a matrix control method based on a magnetic latching relay switch radio-frequency front end, and aims to solve the problems that the radio-frequency front end cannot use complex processors such as an FPGA (field programmable gate array) and a CPLD (complex programmable logic device) under the condition of using a mechanical switch or a magnetic latching relay switch, the number of switches to be driven is extremely large, and the switch driving cannot be realized in a discrete IO (input/output) resource one-to-one mapping mode.
The invention provides a matrix control circuit based on a magnetic latching relay switch radio frequency front end, which comprises a cascaded combinational logic circuit and a switch control network;
the combinational logic circuit comprises two groups of decoding branches, and the decoding branches are used for respectively decoding alpha-path control signals and beta-path control signals to generate N-path control signals and M-path control signals;
the switch control network is an array control network formed by NxM switch coils, and a power switch control circuit with N paths of outputs and an OC signal generating circuit with M paths of outputs, which are connected with the array control network; the power switch control circuit is used for receiving N paths of control signals and outputting N paths of packet voltages to the array control network; the OC signal generating circuit is used for receiving the M control signals and outputting the M OC signals to the array control network; and the N multiplied by M switch wire packages in the array control network are used for outputting N multiplied by M control signals to the magnetic latching relay switch after receiving the N route package voltage and the M route OC signals.
Further, each group of decoding branches comprises a decoder, an inverter and a driver which are connected in sequence.
Further, the input of the decoder is an alpha path control signal and a Cs chip selection signal, or a beta path control signal and a Cs chip selection signal.
Wherein the relationship between α and N is: n is 2 α 。
Wherein the relation between beta and M is as follows: m-2 β 。
Wherein, alpha, beta and N, M are all positive integers.
The invention also provides a matrix type control method based on the magnetic latching relay switch radio frequency front end, which comprises the following steps:
step 2, the switch control network carries out the following processing on the N control signals and the M control signals:
(1) the power switch control circuit receives the N paths of control signals and outputs N paths of packet voltages to the array control network;
(2) the OC signal generating circuit receives the M control signals and outputs the M OC signals to the array control network;
(3) after N multiplied by M switch wire packages in the array control network receive N line package voltages and M line OC signals, N multiplied by M line control signals are output to the magnetic latching relay switch
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the matrix control circuit has simple structure, clear logical relation and easy realization;
2. the invention has less input control resource overhead and can realize longer index of output control resources;
3. the invention outputs in a time-sharing way, and has small power consumption;
4. the invention has no crystal or crystal oscillator, does not pollute radio frequency signals and has good electromagnetic compatibility.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and it is obvious for those skilled in the art that other related drawings can be obtained according to these drawings without inventive efforts.
Fig. 1 is a schematic diagram of a matrix control circuit based on a magnetic latching relay switch rf front end according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a combinational logic circuit according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a switch control network according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
As shown in fig. 1, the present embodiment provides a matrix control circuit based on a magnetic latching relay switch rf front end, which includes a cascaded combinational logic circuit and a switch control network;
as shown in FIG. 2, the combinational logic circuit includes two decoding branches for decoding the alpha control signal and the beta control signal to generate N control signals [ C ] 0 …C N-1 ]And M control signals [ R ] 0 …R M-1 ](ii) a Each group of decoding branches comprises a decoder, a phase inverter and a driver which are connected in sequence. Further, the input of the decoder is an alpha-path control signal [ C 0 …C N-1 ]And Cs chip select signal, or beta control signal [ R ] 0 …R M-1 ]And a Cs chip select signal. And:
the relationship between α and N is: n is 2 α ;
The relationship between β and M is: m2 β ;
α, β, N, M are all positive integers.
(2) As shown in fig. 3, the switch control network is an array control network formed by N × M switch coils, and a power switch control circuit having N outputs and an OC signal generation circuit having M outputs, which are connected to the array control network; the power switch control circuit is used for receiving N paths of control signals [ C ] 0 …C N-1 ]And outputs N-way packet voltage [ V ] to the array control network 0 …V N-1 ](ii) a The OC signal generating circuit is used for receiving M paths of control signals [ R ] 0 …R M-1 ]And outputs M OC signals [ R ] to the array control network 0 …R M-1 ](ii) a N M switch packets in the array control network for receiving N route packet voltages V 0 …V N-1 ]And M-way OC signal [ R ] 0 …R M-1 ]Then, the N M control signals are output to the magnetic latching relay switch. The nxm paths of control signals are expressed as follows:
that is, the state switching of the magnetic latching relay switch is realized by applying an excitation voltage (i.e., an N-line packet voltage) between the positive and negative electrodes of N × M switch packets.
Based on the matrix control circuit, the invention also realizes a matrix control method based on the magnetic latching relay switch radio frequency front end, which comprises the following steps: v 0 R 0
step 2, the switch control network carries out the following processing on the N control signals and the M control signals:
(1) the power switch control circuit receives the N paths of control signals and outputs N paths of packet voltages to the array control network;
(2) the OC signal generating circuit receives the M control signals and outputs the M OC signals to the array control network;
(3) after N multiplied by M switch wire packets in the array control network receive the N route packet voltage and the M route OC signals, the N multiplied by M route control signals are output to the magnetic latching relay switch.
For a certain example, in the development and development of a certain project product, the radio frequency front end control module is developed by adopting the method, 9 paths of input signals are realized, 95 paths of magnetic latching relay switches at the radio frequency front end are controlled in a time-sharing mode, the quality of radio frequency signals is not influenced, and the engineering application requirements are well met. Therefore, for the matrix control circuit and method based on the magnetic latching relay switch radio frequency front end, which are realized by the invention, the switch control network is cascaded by adopting the combinational logic circuit, so that the matrix control circuit and method have the following beneficial effects:
1. the matrix control circuit has simple structure, clear logical relation and easy realization;
2. the input control resource overhead is low, and the exponential multiplication of the output control resource can be realized;
3. the invention outputs in a time-sharing way and has low power consumption;
4. the invention has no crystal or crystal oscillator, does not pollute radio frequency signals and has good electromagnetic compatibility.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A matrix control circuit based on a magnetic latching relay switch radio frequency front end is characterized by comprising a cascaded combinational logic circuit and a switch control network;
the combinational logic circuit comprises two groups of decoding branches, and the decoding branches are used for respectively decoding alpha-path control signals and beta-path control signals to generate N-path control signals and M-path control signals;
the switch control network is an array control network formed by NxM switch coils, and a power switch control circuit with N paths of outputs and an OC signal generating circuit with M paths of outputs, which are connected with the array control network; the power switch control circuit is used for receiving N paths of control signals and outputting N paths of packet voltages to the array control network; the OC signal generating circuit is used for receiving the M control signals and outputting the M OC signals to the array control network; the N multiplied by M switch wire packages in the array control network are used for receiving N line package voltages and M circuits of OC signals and then outputting N multiplied by M circuits of control signals to the magnetic latching relay switch.
2. The magnetic latching relay switch radio frequency front end based matrix control circuit of claim 1, wherein each set of decoding branches comprises a decoder, an inverter and a driver connected in sequence.
3. The magnetic latching relay switch radio frequency front end based matrix control circuit of claim 2, wherein the input of the decoder is alpha path control signal and Cs chip select signal, or beta path control signal and Cs chip select signal.
4. According to the claims1, the matrix control circuit based on the magnetic latching relay switch radio frequency front end is characterized in that the relation between alpha and N is as follows: n is 2 α 。
5. The magnetic latching relay switch radio frequency front end based matrix control circuit of claim 1, wherein the relationship between β and M is: m2 β 。
6. The matrix control circuit based on magnetic latching relay switch radio frequency front end of claim 1, 4 or 5, characterized in that α, β, N, M are all positive integers.
7. A matrix control method based on a magnetic latching relay switch radio frequency front end is characterized by comprising the following steps:
step 1, a combinational logic circuit respectively decodes alpha control signals and beta control signals to generate N control signals and M control signals;
step 2, the switch control network carries out the following processing on the N control signals and the M control signals:
(1) the power switch control circuit receives the N paths of control signals and outputs N paths of packet voltages to the array control network;
(2) the OC signal generating circuit receives the M control signals and outputs the M OC signals to the array control network;
(3) after N multiplied by M switch wire packets in the array control network receive the N route packet voltage and the M route OC signals, the N multiplied by M route control signals are output to the magnetic latching relay switch.
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101093394A (en) * | 2007-07-11 | 2007-12-26 | 哈尔滨工程大学 | Remote controllable hardware configuration system based on network, and control method |
WO2010019441A1 (en) * | 2008-08-14 | 2010-02-18 | Nantero, Inc. | Nonvolatile nanotube programmable logic devices and field programmable gate array |
CN202084949U (en) * | 2011-06-23 | 2011-12-21 | 北京博瑞莱智能科技有限公司 | Multi-way synchronous capacitor coding fling-cut switch |
CN203084017U (en) * | 2012-11-27 | 2013-07-24 | 中国航空工业集团公司第六三一研究所 | Mode-configurable matrix switch |
CN105741872A (en) * | 2016-02-02 | 2016-07-06 | 北京时代民芯科技有限公司 | Reinforcement configuration memory array applicable to FPGA for space navigation and configuration method of reinforcement configuration memory array |
CN107505486A (en) * | 2017-09-07 | 2017-12-22 | 国营芜湖机械厂 | A kind of high pressure program controlled matrix switch |
CN110134083A (en) * | 2019-04-28 | 2019-08-16 | 北京卫星制造厂有限公司 | A kind of cubicle switchboard configuration aerospace intelligent power distribution control device and method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101430220A (en) * | 2008-12-18 | 2009-05-13 | 四川泛华航空仪表电器厂 | Controllable matrix program-controlled capacitance box |
US9379713B2 (en) * | 2014-01-17 | 2016-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and driving method thereof |
-
2021
- 2021-06-10 CN CN202110647423.2A patent/CN113410097B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101093394A (en) * | 2007-07-11 | 2007-12-26 | 哈尔滨工程大学 | Remote controllable hardware configuration system based on network, and control method |
WO2010019441A1 (en) * | 2008-08-14 | 2010-02-18 | Nantero, Inc. | Nonvolatile nanotube programmable logic devices and field programmable gate array |
CN202084949U (en) * | 2011-06-23 | 2011-12-21 | 北京博瑞莱智能科技有限公司 | Multi-way synchronous capacitor coding fling-cut switch |
CN203084017U (en) * | 2012-11-27 | 2013-07-24 | 中国航空工业集团公司第六三一研究所 | Mode-configurable matrix switch |
CN105741872A (en) * | 2016-02-02 | 2016-07-06 | 北京时代民芯科技有限公司 | Reinforcement configuration memory array applicable to FPGA for space navigation and configuration method of reinforcement configuration memory array |
CN107505486A (en) * | 2017-09-07 | 2017-12-22 | 国营芜湖机械厂 | A kind of high pressure program controlled matrix switch |
CN110134083A (en) * | 2019-04-28 | 2019-08-16 | 北京卫星制造厂有限公司 | A kind of cubicle switchboard configuration aerospace intelligent power distribution control device and method |
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