CN113409845A - Method and device for replacing nonvolatile memory and storage medium - Google Patents
Method and device for replacing nonvolatile memory and storage medium Download PDFInfo
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
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Abstract
The invention discloses a replacement method, a device and a storage medium of a nonvolatile memory, wherein the replacement method comprises the following steps: circularly performing programming-verifying operation on the target area according to the programming operation instruction; when the number of times that the target area does not pass the program-verify operation is larger than a first set value, performing a replacement operation on the target area according to the word line address; circularly carrying out erasing-verifying operation on the target area according to the erasing operation instruction; when the number of times that the target area does not pass the erasing-verifying operation is larger than a second set value, carrying out replacement operation on the word line address which does not pass the erasing-verifying operation in the target area; the programming-erasing operation is executed in the memory chip, the number of times of internal execution circulation is limited according to the preset first set value and the second set value, the number of times of communication between the testing machine and the memory chip can be reduced, the testing efficiency is improved, and the performance requirement on the testing machine is reduced.
Description
Technical Field
The present invention relates to the field of memory chip technologies, and in particular, to a method and an apparatus for replacing a nonvolatile memory, and a storage medium.
Background
A memory chip produced by a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) process has a special structure, as shown in fig. 1, memory cells in the memory chip are each composed of a switch tube (control tube for short) for control and a switch tube (data tube for short) for storage, and the electrical characteristics of the memory cells are controlled by an SWL (SEL-word line, word line control signal) and a WL (word line ), so that the output current of the memory cells is read out on the BL (bit line ) to realize data reading and writing.
At present, when a memory chip performs a program-erase operation and finds that a memory cell has an error, the memory chip usually completes the current operation and records the address of the defective memory cell, and then performs a replacement operation on the memory cell, because the replacement operation and the program-erase operation are performed separately, a tester is required to exchange information with the memory chip for many times, including that the tester sends an instruction to the memory chip, the memory chip returns a test result, the tester sends a replacement instruction and the memory chip returns a replacement operation result, and the like, the test efficiency is insufficient, and the performance requirement on the tester is high.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a replacement method, a device and a storage medium of a nonvolatile memory, wherein in the process of programming-erasing operation, the replacement operation of a word line address is judged and executed in a storage chip according to the verification result of iterative cycle, so that the test efficiency is improved, the requirement of a test machine is reduced, and the method and the device are also suitable for verifying and replacing a storage product per se in the using process of a user.
In a first aspect, an embodiment of the present invention provides a replacement method for a nonvolatile memory, where the memory includes a memory cell produced by a SONOS process, and the replacement method includes:
when a programming operation instruction is received, circularly performing programming-verifying operation on a target area according to the programming operation instruction;
when the number of times that the target area does not pass the programming-verifying operation continuously is larger than a first set value, performing replacement operation on the target area according to the word line address;
when an erasing operation instruction is received, circularly performing erasing-verifying operation on a target area according to the erasing operation instruction;
and when the number of times that the target area does not pass the erasing-verifying operation continuously is larger than a second set value, carrying out replacement operation on the word line address which does not pass the erasing-verifying operation in the target area.
The replacement method of the nonvolatile memory provided by the embodiment of the invention at least has the following beneficial effects: after receiving a program-erase operation instruction sent by a tester, a memory chip of the SONOS technology starts to circularly execute a program-verify operation and an erase-verify operation according to the program-erase operation instruction, wherein the program-verify operation is executed aiming at a memory unit, when a target area still fails to pass the program-verify operation after multiple circulations, the target area is replaced, the erase-verify operation is executed aiming at the memory area, when the target area still fails to pass the erase-verify operation after multiple circulations, a memory unit which does not pass the erase-verify operation in the target area is replaced, the program-erase operation is executed inside the memory chip and limits the number of times of internally executing circulations according to a preset first set value and a preset second set value, so that the number of times of communication between the tester and the memory chip can be reduced, the test efficiency is improved, and meanwhile, the test machine only needs to send simple test instructions, so the replacement method of the embodiment of the invention reduces the performance requirements on the test machine and can be suitable for test machines with different performances; on the other hand, the replacement operation of replacing according to the word line address is also completed by the memory chip in the memory chip, so that the replacement method of the embodiment of the invention can be applied in the test process, and the replacement method of the embodiment of the invention can be applied in the process of using the memory product by a user, thereby further prolonging the service life of the memory product of the SONOS process.
In some embodiments, the cycling a program-verify operation on a target area according to the program operation instruction includes:
performing a soft erase operation on the target area;
and circularly executing a program-verification operation on the target area, wherein the program-verification operation comprises writing test data and program verification.
In some embodiments, said performing a program-verify operation on said target area cycle comprises:
acquiring the count of a programming counter;
when the count of the programming counter is not larger than a first set value, performing one-time programming-verifying operation on the target area;
when the target area does not pass the programming verification, the counting of the programming counter is increased by one;
and iteratively executing a program-verify operation with the current count of the program counter and the target area until the target area passes program-verify or the count of the program counter is greater than the first set value.
In some embodiments, the performing a replacement operation on the target area by word line address includes:
acquiring a word line address of a replacement unit and a word line address of the target area;
and replacing the word line address of the target area with the word line address of the replacement unit.
In some embodiments, before obtaining the word line address of the replacement cell and the word line address of the target area, further comprising:
judging whether the target area is suitable for executing replacement operation;
if yes, searching and selecting an available word line in the replacement area, and if not, setting the programming failure flag bit of the target area to be valid.
In some embodiments, the replacing the word line address of the replacement cell includes a first control pipe word line address and a first data pipe word line address, the target area word line address includes a second control pipe word line address and a second data pipe word line address, and the replacing the target area word line address with the replacement cell word line address includes:
and exchanging the first control pipeline word line address and the second control pipeline word line address, and exchanging the first data pipeline word line address and the second data pipeline word line address.
In some embodiments, the performing an erase-verify operation on the target area in a loop according to the erase operation instruction includes:
performing a soft programming operation on the target area;
circularly executing an erasing-verifying operation on the target area, wherein the erasing-verifying operation comprises erasing programming data and erasing verification;
the word line addresses that do not pass the erase verification in each cycle are recorded for the next erase-verify operation cycle.
In some embodiments, said performing an erase-verify operation on said target area in a loop comprises:
acquiring the count of an erasing counter and a word line address which does not pass the erasing verification in the last circulation;
when the count of the erasing counter is not more than a second set value, performing erasing-verifying operation on the word line address which does not pass the erasing verification in the last circulation;
when at least one word line address does not pass the erasing verification, the counting of the erasing counter is increased by one, and the word line address which does not pass the erasing verification is updated;
and iteratively executing the erasing-checking operation by using the current count of the erasing counter and the word line address which does not pass the erasing check in the current cycle until all the word line addresses of the target area pass the erasing check or the count of the erasing counter is larger than the second set value.
In some embodiments, the performing a replacement operation on the word line address in the target region failing the erase-verify operation includes:
acquiring a word line address of a replacement unit and a word line address which does not pass an erasing-verifying operation in the target area;
and replacing the word line address which does not pass the erasing-verifying operation in the target area with the word line address of the replacement unit.
In some embodiments, before obtaining the word line address of the replacement cell and the word line address of the target region failing the erase-verify operation, further comprising:
determining the number of word line addresses suitable for executing replacement operation in the word line addresses which do not pass the erasing-verifying operation in the target area;
and searching and selecting the replacement units with the same number as the word line addresses.
In some embodiments, the replacing the word line address of the target region failing the erase-verify operation with the word line address of the replacement cell includes:
determining a third control pipe word line address and a third data pipe word line address in each word line address which does not pass the erasing-verifying operation in the target area;
determining a fourth control pipe word line address and a fourth data pipe word line address among the word line addresses of the replacement cell;
and exchanging the third control pipeline word line address and the fourth control pipeline word line address, and exchanging the third data pipeline word line address and the fourth data pipeline word line address.
In a second aspect, an embodiment of the present invention further provides a reference current determining apparatus, including at least one processor and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the alternative method of the first aspect.
In a third aspect, the embodiment of the present invention also provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to cause a computer to execute the replacement method according to the first aspect.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a schematic structural diagram of a memory fabricated by a SONOS process;
FIG. 2 is an overall flow chart of an alternative method provided by an embodiment of the present invention;
FIG. 3 is a flowchart of a method for program-verify cycling through a program operation according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for replacing a word line address in a program operation according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method provided by an embodiment of the present invention prior to performing an alternate operation;
FIG. 6 is a flowchart illustrating the overall operation of cycling between erase and verify operations in an erase operation according to an embodiment of the present invention;
FIG. 7 is a flowchart of a specific method for performing erase-verify cycles in an erase operation according to an embodiment of the present invention;
FIG. 8 is a flowchart of a method for replacing a word line address in an erase operation according to an embodiment of the present invention;
FIG. 9 is a flow chart of a method provided by an embodiment of the present invention prior to performing an alternate operation;
FIG. 10 is a flow chart of exchanging word line addresses of a control pipe and a data pipe in an erase operation according to an embodiment of the present invention;
FIG. 11 is an overall flow chart of the programming operation provided by the present example;
FIG. 12 is an overall flow chart of an erase operation provided by an example of the present invention;
fig. 13 is a schematic diagram of module connection of an alternative apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention provides a replacement method, a device and a storage medium of a nonvolatile memory, wherein the replacement method is executed in a memory chip in a nested manner, so that in the process of executing programming-erasing operation, memory units which do not pass programming verification and erasing verification are replaced by the memory chip per se according to word line addresses, thereby improving the test efficiency and reducing the performance requirement of a tester.
The embodiments of the present invention will be further explained with reference to the drawings.
Referring to fig. 2, an embodiment of the present invention provides a replacement method for a nonvolatile memory, where the memory includes memory cells produced by a SONOS process, and the replacement method includes, but is not limited to, the following steps S100, S200, S300, and S400.
Step S100, when a programming operation instruction is received, circularly performing programming-verifying operation on a target area according to the programming operation instruction;
step S200, when the times that the target area does not pass the programming-verifying operation continuously is larger than a first set value, carrying out replacement operation on the target area according to the word line address;
step S300, when an erasing operation instruction is received, circularly performing erasing-verifying operation on a target area according to the erasing operation instruction;
in step S400, when the number of times that the target area does not pass the erase-verify operation continuously is greater than a second set value, a replacement operation is performed on the word line address of the target area that does not pass the erase-verify operation.
The nonvolatile memory is widely applied to the current mainstream storage products, the nonvolatile memory is produced by a semiconductor process, a plurality of storage chips are divided by a wafer in the production process, and the storage chips are tested and assembled into the storage products after leaving the factory. Wherein, the SONOS process is one of the processes for producing a nonvolatile memory, and the structure of the memory produced based on the SONOS process is shown in fig. 1, each memory cell has a corresponding control transistor (usually an nmos transistor for selecting data addresses) and a data transistor (for storing data) corresponding to the control transistor, so that the word line address of the structure of the memory produced by the SONOS process has both the control transistor word line address SWL and the data transistor word line address WL, which are represented in the following manner in fig. 1: (SEL-WL0, WL0), (SEL-WL1, WL1), (SEL-WL2, WL2), … …, (SEL-WLn, WLn), where n is a natural number; obviously, the word line connection controls the gate of the MOS transistor, and a word line is connected with a plurality of MOS transistors to form a row address of the memory chip, so that the operation performed on one word line address actually operates on a plurality of MOS transistors, and in addition, the memory chip further has a column address, which is represented by a bit line BL, the bit line BL is connected with the source/drain injection regions of the data transistor at different word line addresses, and the source/drain injection regions of the control transistor at different word line addresses are connected to a source line (source line).
In the mass production test process of the memory chip, the mass production test is performed by contacting the memory chip with a tester, for example, by contacting a contact on the memory chip with a metal needle, the tester sends a test instruction to the memory chip and receives a result returned by the memory chip, thereby determining whether the memory chip passes the test. The above Test is generally called CP Test (Circuit testing Test), and in the CP Test process, the Test program of the tester plays an important role in controlling the whole Test flow, so that a tester with higher performance can often implement more complicated Test items. At present, for CP testing of a memory produced by a SONOS process, when a memory cell in a memory chip is found to have a problem, a tester often receives a test result of the memory chip first, then sends a replacement instruction to the memory chip, and then performs address replacement curing on an execution result of the replacement instruction, and a replacement operation corresponding to the replacement instruction is often divided into multiple instruction executions, so that the tester needs to spend more time in the test process, and the tester is required to accurately complete the replacement operation, so that the test process is slow, and the performance requirement on the tester is high.
Based on this, through the replacement method of the embodiment of the invention, the verification and replacement process is completed inside the memory chip, so that the performance requirement on the tester can be greatly reduced, and the test efficiency is improved. It can be understood that, since the replacement operation requires the use of replacement units, a certain number of replacement units need to be integrated into the memory chip for use; referring to fig. 1, a memory chip is divided into two parts, one part is a conventional memory area, the other part is a reserved replacement area, a replacement unit in the replacement area is not available in a user use process, but actually the structure of the replacement unit is the same as that of a common memory unit, so word line addresses can be replaced through a replacement operation, taking fig. 1 as an example, the word line addresses of the replacement unit are represented by WL _ dummy and SEL-WL _ dummy, and when the replacement operation is performed, the word line address corresponding to the memory unit with a problem is replaced by the word line address corresponding to the replacement unit with the word line address as a minimum unit.
In the CP testing process, the tester sends a program-erase operation command to the memory chip, where the command is divided into two parts, one part is a program operation command and corresponds to a program-verify operation, and the other part is an erase operation command and corresponds to an erase-verify operation, and the following description is divided into two parts.
And (3) programming operation:
generally, when a memory chip receives a programming operation instruction sent by a tester, a target area is programmed according to the programming operation instruction, test data is written, the written test data is read, and whether the read data is correct or not is judged.
In the embodiment of the invention, the replacement operation is added in the programming operation process, and the storage chip is responsible for judging and executing the replacement operation, so that the whole process of soft erase + programming + verification + replacement is realized, and the two steps of programming and verification can be iterated circularly. Specifically, the memory chip selects a target area according to a received programming operation instruction, performs a programming-verifying operation on the target area in a circulating manner, namely, performs one-time programming writing and programming verification on the target area in each circulation, judges whether the target area can pass the verification, and determines whether a replacing operation needs to be performed according to a verification result. The memory chip presets a first set value to be used as one of the bases for stopping circulation, and when the number of times that the target area cannot pass the programming verification is larger than the first set value, the target area is considered to be incapable of working normally and needs to be replaced. The replacement operation of the embodiment of the invention is performed on the word line, the row address of the target area is the word line address, and the word line address corresponding to the target area with failed programming verification is exchanged with the word line address corresponding to the reserved replacement unit for replacement.
The whole process of soft erase, programming, verification and replacement is executed in the memory chip, and the test machine does not need to additionally send instructions such as verification and replacement in response to the programming operation instruction sent by the test machine, so that the operation burden of the test machine is reduced.
Referring to fig. 3, the program-verify operation is cyclically performed on the target area in step S100, which specifically includes, but is not limited to, the following steps S110, S120, S130, and S140.
Step S110, acquiring the count of a programming counter;
step S120, when the count of the programming counter is not more than a first set value, performing one-time programming-verifying operation on the target area;
step S130, when the target area does not pass the programming verification, the counting of the programming counter is increased by one;
in step S140, a program-verify operation is iteratively performed with the current count of the program counter and the target area until the target area passes the program verify or the count of the program counter is greater than a first set value.
The number of cycles is counted by a program counter, and when a program-verify operation is performed each time and when the program-verify operation is not passed, the program counter is incremented by one until the technology of the program counter is greater than a first set value, the program-verify operation is not performed any more, and a replacement operation is performed instead. It is understood that, in the process of executing the program-verify operation in a loop, the target area is considered to be normally operated as long as the program-verify operation is passed once, and the loop is immediately ended, so that it can be known that if one target area needs to be replaced, it indicates that the target area has not passed the program-verify operation once all the time.
It is noted that the replaced cells also need to perform the program-verify operation: and when the replacement operation is finished, resetting the counting of the programming counter, taking the word line address corresponding to the replaced replacement unit as a target area, and circularly performing programming-verifying operation on the target area. Generally, the replacement cell is a normal memory cell by default, and therefore can pass the program verification normally, if the number of times that the replaced replacement cell can not pass the program verification is greater than the first set value, the word line address of the new replacement cell is selected again to perform the replacement operation according to the above method.
Based on the structure of the memory chip of the SONOS process, the replacement operation of the embodiment of the present invention is performed by word line, and specifically, referring to fig. 4, the replacement operation is performed on the target area by word line address in step S200, including but not limited to the following steps S210 and S220.
Step S210, obtaining the word line address of the replacement unit and the word line address of the target area;
in step S220, the word line address of the target area is replaced with the word line address of the replacement cell.
When a replacement operation is performed, it is necessary to determine a word line address of a replacement cell and a word line address of a target area, since the maximum area of a program operation command is page, which is generally less than or equal to one word line, the target area is equivalent to all memory cells on one word line, the actual process of replacement is to replace the replacement cell at a certain word line address in the replacement area to the corresponding memory cell in the target area, the conversion of memory cells in semiconductor memory, of course, does not involve operations on hardware, only addresses need to be configured, the replacement operation of the embodiment of the present invention is to replace the word line address of the target area with the word line address of the replacement cell, and the replacement information corresponding to the replacement operation is solidified to the parameter configuration area of the memory chip, so that the address information after replacement can be determined when the memory product is powered on every time.
It can be understood that before step S210, that is, before the word line address of the replacement cell and the word line address of the target area are acquired, a process of judging the feasibility of the replacement operation is further included, and referring to fig. 5, the process specifically includes step S201 and step S202:
step S201, judging whether the target area is suitable for executing replacement operation;
step S202, if yes, an available word line in the replacement area is searched and selected, and if not, the programming failure flag bit of the target area is set to be valid.
Determining whether the target area is suitable for performing the replacement operation may include determining whether the target area can be replaced, where some memory units are not regular memory areas, and these memory units may not be suitable for performing the replacement operation, but may need to report an error to a tester or a user; another aspect is to determine whether a replacement unit is available for performing a replacement operation, and if there is no spare replacement unit in the replacement area, the replacement operation cannot be performed, and an error is also required to be reported to a tester or a user. If the replacement operation can be executed, an available word line is selected from the replacement area, the word line address of the available word line is obtained, and therefore the replacement unit on the word line address is replaced to the target area.
According to the SONOS process structure, the word line address of the target area includes a first control pipe word line address and a first data pipe word line address, and the word line address of the replacement unit includes a second control pipe word line address and a second data pipe word line address, so that in the process of performing the replacement operation, the control pipe word line address and the data pipe word line address need to be replaced as a whole, that is, step S220 specifically includes:
and exchanging the first control pipeline word line address and the second control pipeline word line address, and exchanging the first data pipeline word line address and the second data pipeline word line address.
Due to the particularity of the memory cell structure in SONOS, when a replacement operation is performed, the whole word line needs to be replaced, and as can be seen from the description of the word line structure, the memory cell includes a control transistor and a data transistor, and therefore, the word line addresses include a control transistor word line address and a data transistor word line address, then a first control transistor word line address in the word line addresses of the target area needs to be exchanged with a second control transistor word line address in the word line addresses of the replacement cell, and a first data transistor word line address in the word line addresses of the target area needs to be exchanged with a second data transistor word line address in the word line addresses of the replacement cell, so that the whole replacement of the word line can be completed.
And (3) erasing operation:
generally, when a memory chip receives an erase operation instruction sent by a tester, an erase operation is performed on a target area according to the erase operation instruction, data of memory cells in the target area is reset to 1, then the reset data (current) is read, and whether the read data (current) is correct or not is judged, so that it is known that before the erase operation, soft programming needs to be performed on the target area first, and the purpose is to write data into the target area randomly, then erase the data to reset, and then see whether the erase operation is successful or not.
In the embodiment of the invention, the replacement operation is added in the erasing operation process, and the memory chip is responsible for judging and executing the replacement operation, so that the whole process of soft programming, erasing, verifying and replacing is realized, wherein the two steps of erasing and verifying can be iterated circularly, and the word line address which still does not pass the erasing and verifying is screened out in the circular iteration to enter the next iteration. Specifically, the memory chip selects a target area according to a received erasing operation instruction, performs erasing-verifying operation on the target area in a circulating manner, and selects a word line address which does not pass the erasing verification in the current circulating manner, namely, in each circulating manner, performs data erasing and erasing verification on the word line address which does not pass the erasing verification in the last circulating manner in the target area, and finally judges whether the word line address in the target area cannot pass the verifying manner, thereby determining whether to perform replacement operation. When the number of times that the target area cannot pass the erase verification is greater than the second set value, it is determined that the word line in the target area cannot normally work, and the word line needs to be replaced. Similarly, the replacement operation in the erase operation according to the embodiment of the present invention is performed on the word line, and the word line address in the target region where the erase verification fails is exchanged with the word line address corresponding to the replacement cell reserved for replacement.
The whole process of the soft programming, the programming and erasing, the verifying and the replacing is executed in the memory chip, and the erasing operation instruction sent by the tester is responded, so that the tester is not required to additionally send the verifying, replacing and other instructions, and the operation burden of the tester is reduced.
Referring to fig. 6, in step S300, the erase-verify operation is performed on the target area cyclically according to the erase operation command, including but not limited to the following steps S310, S320, and S330.
Step S310, performing soft programming operation on the target area;
step S320, circularly executing erasing-verifying operation on the target area, wherein the erasing-verifying operation comprises erasing programming data and erasing verification;
in step S330, the word line address that does not pass the erase verification in each cycle is recorded for the next erase-verify operation cycle.
And writing data into the target area through a soft programming operation so as to facilitate the subsequent erasing and erasing verification of the test. It is understood that the erase operation may be performed for a plurality of word line addresses, unlike the program operation performed for one word line address, and thus the target area may include a plurality of word line addresses in an embodiment of the present invention. When the target area is subjected to erasing-verifying operation for the first time, all word line addresses in the target area are erased, then the whole target area is subjected to erasing-verifying, whether some word lines in the target area do not pass the erasing-verifying operation or not is judged, the word line addresses which do not pass the erasing-verifying operation are recorded and are used as the next erasing-verifying operation cycle, therefore, the erasing-verifying operation cycle of the embodiment of the invention does not repeatedly erase the word lines which pass the erasing-verifying operation, the over-erasing state is avoided, and the abrasion of the storage unit in the erasing process is reduced.
In step S320, the erase-verify operation cycle is ended by counting the erase counter. Specifically, referring to fig. 7, the erase-verify operation is performed on the target area in step S320 in a loop, including, but not limited to, the following steps:
step S321, obtaining the count of the erase counter and the word line address that does not pass the erase verification in the last cycle;
step S322, when the count of the erasing counter is not larger than the second set value, performing an erasing-verifying operation on the word line address which does not pass the erasing verification in the last cycle;
step S323, when at least one word line address does not pass the erase verification, the count of the erase counter is increased by one, and the word line address which does not pass the erase verification is updated;
in step S324, the erase-verify operation is iteratively performed with the current count of the erase counter and the word line addresses that do not pass the erase verify in the current cycle until all the word line addresses of the target area pass the erase verify or the count of the erase counter is greater than a second set value.
It can be understood that, in order to avoid over-erasing the memory cells on the normally operating word line address, except for the first cycle, two elements, namely the technology of the erase counter and the word line address which does not pass the erase verification in the last cycle, are acquired at the beginning of each subsequent cycle, so that only the word line address which does not pass the erase verification in the current cycle can be subjected to the erase-verification operation. After each erasing-verifying operation is executed, if some word line addresses can not pass the erasing verification, the counting of the erasing counter is increased by one to enter the next circulation, if all the word line addresses of the target area pass the erasing verification, the erasing operation of the current target area is directly finished, therefore, different from the programming operation process, the erasing operation can be finished only by judging that all the word line addresses of the current area pass the verifying only once, but can be finished only by judging that all the word line addresses of the current area pass the verifying; of course, since the erase operation may be performed on target areas of different sizes, the target area may be a page, sector, block, or even a chip, that is, the target area may be partitioned into ranges greater than or equal to one word line address, and therefore, if the target area is a page, that is, the target area has only one word line address, the loop may be ended only by passing the erase verification once.
It is noted that the replaced replacement cell also needs to perform the erase-verify operation: and when the replacement operation is finished, resetting the counting of the programming counter, taking the word line address corresponding to the replaced replacement unit as a target area, and circularly performing erasing-verifying operation on the target area. Generally, the replacement unit is a normal memory unit by default, and therefore can pass the erase verification normally, if the number of times that the replaced replacement unit can not pass the erase verification is greater than the second set value, the word line address of the new replacement unit is selected again to perform the replacement operation according to the above method.
Based on the structure of the memory chip of the SONOS process, the replacement operation of the embodiment of the present invention is performed by word line, and specifically, referring to fig. 8, the replacement operation is performed on the target area by word line address in step S400, including but not limited to the following steps S410 and S420.
Step S410, obtaining the word line address of the replacement unit and the word line address which does not pass the erasing-verifying operation in the target area;
in step S420, the word line address in the target region that failed the erase-verify operation is replaced with the word line address of the replacement cell.
When a replacement operation is performed, the word line address of the replacement unit and the word line address of the target area need to be determined, since the erase operation instruction may be directed to different areas, and may be greater than or equal to one word line, for convenience of description later, taking more than two word line addresses that do not pass the erase verification in the target area as an example, then the actual process of the replacement is to replace the plurality of word line addresses that do not pass the erase verification in the target area with the plurality of word line addresses in the replacement area, and the number of word line addresses used for replacement in the replacement area is equal to the number of addresses that do not pass the erase verification in the target area. Similarly, the replacement in the semiconductor memory is completed by the configuration address, so the replacement operation of the embodiment of the present invention is to replace the word line address of the target area with the word line address of the replacement unit, and the replacement information corresponding to the replacement operation is fixed to the parameter configuration area of the memory chip, so that the address information after the replacement can be determined every time the memory product is powered on.
It is to be understood that, referring to fig. 9, before step S410, that is, before obtaining the word line address of the replacement cell and the word line address of the target region that fails the erase-verify operation, the following steps are further included:
step S401, determining the number of word line addresses suitable for executing replacement operation in the word line addresses which do not pass the erasing-verifying operation in the target area;
in step S402, the replacement cells with the same number as the word line addresses are searched and selected.
The above step S401 includes determining whether the target area is suitable for performing the replacement operation, and also includes determining whether the target area can be replaced, and determining whether the replacement unit can be used for performing the replacement operation; when the replacement operation is determined to be executable, selecting a corresponding number of word lines in the replacement area, and acquiring word line addresses of the word lines, so as to replace the replacement units on the word line addresses to corresponding word line addresses in the target area; if the replacement operation cannot be executed, in addition to reporting an error to a tester or a user, the erasure failure flag bit of the target area needs to be set to be valid, so as to prevent subsequent reading and writing of the target area from affecting the stability of the storage product.
According to the structure of the memory of the SONOS process, the word line address corresponding to each memory cell includes a control pipe word line address and a data pipe word line address, and therefore, referring to fig. 10, the word line address that fails the erase-verify operation in the target region is replaced with the word line address of the replacement cell in the step S420, which specifically includes, but is not limited to, the following steps S421, S422, and S423.
Step S421, determining a third control pipe word line address and a third data pipe word line address in each word line address which does not pass the erasing-verifying operation in the target area;
step S422, determining a fourth control pipe word line address and a fourth data pipe word line address in the word line addresses of the replacement unit;
step S423 exchanges the third control pipe word line address and the fourth control pipe word line address, and exchanges the third data pipe word line address and the fourth data pipe word line address.
Similar to the replacement mode of the programming operation process, the replacement operation in the erasing operation process also respectively replaces a fourth control tube and a fourth data tube of the word line address in the replacement area with a third control tube and a third data tube of the word line address which needs to be replaced in the target area according to the rule that the control tubes correspond to the control tubes and the data tubes correspond to the data tubes; it is to be understood that since the replaced word line address in the target area may be plural, the number of the third control pipe and the third data pipe, and the number of the fourth control pipe and the fourth data pipe referred to above may be plural.
It should be noted that although the above description of the program operation and the erase operation refers to operations performed during the CP test, in fact, since the program for executing the replacement method according to the embodiment of the present invention is embedded inside the memory chip, the replacement method according to the embodiment of the present invention may be executed inside the memory product during the use of the memory product by a user, and for the memory cells whose performance is degraded along with the normal use, the memory chip may perform internal replacement to repair the memory cells with problems, so as to prolong the life of the memory product.
It can be known from the above description of the program operation and the erase operation that the program operation and the erase operation of the embodiment of the present invention add the check and replacement steps compared with the conventional program operation and erase operation, so that the whole processes of soft erase-program-check-replacement and soft program-erase-check-replacement are all integrated and completed inside the memory chip, and the replacement is performed according to the word line address according to the check result without frequent communication between the tester and the memory chip, that is, the tester only needs to send the program-erase operation instruction to the memory chip to be tested, and does not need to additionally send the check and replacement instructions according to the program and erase conditions, thereby greatly reducing the workload and performance requirements of the tester, and meanwhile, in the check process, the set values of loop iteration and loop end are added to control the execution time of the program-erase operation instruction, ensuring that replacement can be done efficiently. On the other hand, because the memory chip internally executes the replacement method, the embodiment of the invention can be applied to the CP test stage and can also be applied to the process of using the memory product by a user, so that the service life of the memory product is prolonged.
The following describes an embodiment of the present invention with a practical example:
the replacement method of this example is applied to a nonvolatile memory, which includes a storage unit produced by a SONOS process, and is executed by a control module in the nonvolatile memory, where the control module may be a controller connecting a plurality of memory chips, or a controller in a single memory chip, so as to execute the replacement method on each word line address in the memory chip, and the replacement method is described in two aspects as follows:
(1) programming operation, refer to fig. 11:
step S510, performing soft erasing operation on the target area;
step S520, programming the target area, and writing test data;
step S530, programming verification is carried out on the target area, and whether the data of the target area can pass the verification is judged;
step S540, if the target area can pass the verification, ending the programming operation of the target area, and if the target area cannot pass the verification, judging whether the counting of the programming counter exceeds a first set value;
step S550, if the count of the programming counter exceeds the first set value, determining whether the target area can perform the replacement operation, if the count of the programming counter does not exceed the first set value, incrementing the count of the programming counter by one, adjusting the setting parameter of the programming operation, and returning to step S520;
step S560, if the target area is judged to be capable of executing the replacement operation, selecting an available word line address in the replacement area, exchanging the available word line address with the word line address of the target area, if the target area is judged not to be capable of executing the replacement operation, setting the programming failure flag bit to be valid, and ending the programming operation on the target area;
in step S570, for the replaced word line address, the program counter is reset and the setting parameters of the program operation are adjusted, and the process returns to step S520.
In step S570, after determining that the replaced word line address passes the verification, writing the replacement information into the parameter configuration area of the memory chip, so that the replacement information is read out every time the memory chip is powered on.
(2) Erase operation, see fig. 12:
step S610, performing soft programming operation on the target area;
step S620, carrying out first erasing and erasing verification on the target area, if word line addresses which do not pass the verification exist, recording the word line addresses which do not pass the verification, setting the count of an erasing counter to be 1, and if all the word line addresses pass the erasing verification, finishing the erasing operation of the target area;
step S630, carrying out erasure verification on the word line address which does not pass the verification, and judging whether the word line address can pass the verification;
step 640, if all word line addresses of the target area can pass the erase verification, ending the erase operation on the target area, if the target area cannot pass the verification, updating and recording the word line addresses which do not pass the verification, and judging whether the count of the erase counter exceeds a second set value;
step S650, if the count of the erasure counter exceeds a second set value, determining whether the word line address which fails to pass the verification can execute the replacement operation, if the count of the erasure counter does not exceed the second set value, adding one to the erasure counter, adjusting the setting parameter of the erasure operation, and returning to step S630;
step S660, if the target area can be judged to execute the replacement operation, selecting the available word line addresses with the same number as the word line addresses which do not pass the verification in the replacement area, exchanging the available word line addresses with the word line addresses which do not pass the verification one by one, and if the target area can not execute the replacement operation, setting the erasure failure flag bit to be valid, and finishing the erasure operation of the target area;
in step S670, for the replaced word line address, the erase counter is reset and the setting parameters of the erase operation are adjusted, and the process returns to step S630.
In step S670, after it is determined that the replaced word line address passes the verification, the replacement information is written into the parameter configuration area of the memory chip, so that the replacement information is read out every time the memory chip is powered on.
The embodiment of the invention also provides a reference current determining device, which comprises at least one processor and a memory which is in communication connection with the at least one processor; the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the aforementioned alternative method.
Referring to fig. 13, it is exemplified that the control processor 1001 and the memory 1002 in the device 1000 may be connected by a bus. The memory 1002, which is a non-transitory computer-readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer-executable programs. Further, the memory 1002 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk memory, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1002 may optionally include memory located remotely from the control processor 1001, which may be connected to the device 1000 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Those skilled in the art will appreciate that the arrangement of devices illustrated in fig. 13 is not intended to be limiting of the apparatus 1000 and may include more or fewer components than those illustrated, or some components may be combined, or a different arrangement of components.
Also provided in an embodiment of the present invention is a computer-readable storage medium storing computer-executable instructions, which are executed by one or more control processors, for example, by one control processor 1001 in fig. 13, and which may cause the one or more control processors to perform an alternative method in the above-described method embodiment, for example, performing method steps S100 to S400 in fig. 2, method steps S110 to S140 in fig. 3, method steps S210 to S220 in fig. 4, method steps S201 to S202 in fig. 5, method steps S310 to S330 in fig. 6, method steps S321 to S324 in fig. 7, method steps S410 to S420 in fig. 8, method steps S401 to S402 in fig. 9, and method steps S421 to S423 in fig. 10, which are described above.
The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.
Claims (13)
1. A replacement method for a non-volatile memory, the memory comprising memory cells produced by a SONOS process, the replacement method comprising:
when a programming operation instruction is received, circularly performing programming-verifying operation on a target area according to the programming operation instruction;
when the number of times that the target area does not pass the programming-verifying operation continuously is larger than a first set value, performing replacement operation on the target area according to the word line address;
when an erasing operation instruction is received, circularly performing erasing-verifying operation on a target area according to the erasing operation instruction;
and when the number of times that the target area does not pass the erasing-verifying operation continuously is larger than a second set value, carrying out replacement operation on the word line address which does not pass the erasing-verifying operation in the target area.
2. The replacement method of claim 1, wherein the cycling a target area for program-verify operations according to the program operation instructions comprises:
performing a soft erase operation on the target area;
and circularly executing a program-verification operation on the target area, wherein the program-verification operation comprises writing test data and program verification.
3. The replacement method of claim 2, wherein said performing a program-verify operation on said target area cycle comprises:
acquiring the count of a programming counter;
when the count of the programming counter is not larger than a first set value, performing one-time programming-verifying operation on the target area;
when the target area does not pass the programming verification, the counting of the programming counter is increased by one;
and iteratively executing a program-verify operation with the current count of the program counter and the target area until the target area passes program-verify or the count of the program counter is greater than the first set value.
4. The replacement method according to claim 1, wherein the performing the replacement operation on the target area by the word line address includes:
acquiring a word line address of a replacement unit and a word line address of the target area;
and replacing the word line address of the target area with the word line address of the replacement unit.
5. The replacement method according to claim 4, further comprising, before obtaining the word line address of the replacement cell and the word line address of the target area:
judging whether the target area is suitable for executing replacement operation;
if yes, searching and selecting an available word line in the replacement area, and if not, setting the programming failure flag bit of the target area to be valid.
6. The replacement method of claim 4, wherein the word line address of the target area comprises a first control pipe word line address and a first data pipe word line address, wherein the word line address of the replacement cell comprises a second control pipe word line address and a second data pipe word line address, and wherein replacing the word line address of the target area with the word line address of the replacement cell comprises:
and exchanging the first control pipeline word line address and the second control pipeline word line address, and exchanging the first data pipeline word line address and the second data pipeline word line address.
7. The replacement method of claim 1, wherein the performing an erase-verify operation on the target area in a loop according to the erase operation instruction comprises:
performing a soft programming operation on the target area;
circularly executing an erasing-verifying operation on the target area, wherein the erasing-verifying operation comprises erasing programming data and erasing verification;
the word line addresses that do not pass the erase verification in each cycle are recorded for the next erase-verify operation cycle.
8. The replacement method of claim 7, wherein said performing an erase-verify operation on said target area in a loop comprises:
acquiring the count of an erasing counter and a word line address which does not pass the erasing verification in the last circulation;
when the count of the erasing counter is not more than a second set value, performing erasing-verifying operation on the word line address which does not pass the erasing verification in the last circulation;
when at least one word line address does not pass the erasing verification, the counting of the erasing counter is increased by one, and the word line address which does not pass the erasing verification is updated;
and iteratively executing the erasing-checking operation by using the current count of the erasing counter and the word line address which does not pass the erasing check in the current cycle until all the word line addresses of the target area pass the erasing check or the count of the erasing counter is larger than the second set value.
9. The replacement method according to claim 1, wherein the performing of the replacement operation on the word line address failing the erase-verify operation in the target area comprises:
acquiring a word line address of a replacement unit and a word line address which does not pass an erasing-verifying operation in the target area;
and replacing the word line address which does not pass the erasing-verifying operation in the target area with the word line address of the replacement unit.
10. The replacement method according to claim 9, further comprising, before obtaining the word line address of the replacement cell and the word line address of the target region failing the erase-verify operation:
determining the number of word line addresses suitable for executing replacement operation in the word line addresses which do not pass the erasing-verifying operation in the target area;
and searching and selecting the replacement units with the same number as the word line addresses.
11. The replacement method according to claim 9, wherein the replacing the word line address failing the erase-verify operation in the target region with the word line address of the replacement cell comprises:
determining a third control pipe word line address and a third data pipe word line address in each word line address which does not pass the erasing-verifying operation in the target area;
determining a fourth control pipe word line address and a fourth data pipe word line address among the word line addresses of the replacement cell;
and exchanging the third control pipeline word line address and the fourth control pipeline word line address, and exchanging the third data pipeline word line address and the fourth data pipeline word line address.
12. A reference current determination apparatus comprising at least one processor and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the alternative method of any one of claims 1 to 11.
13. A computer-readable storage medium having stored thereon computer-executable instructions for causing a computer to perform the alternative method of any of claims 1 to 11.
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