CN107731252B - Nonvolatile memory device and memory device including the same - Google Patents

Nonvolatile memory device and memory device including the same Download PDF

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CN107731252B
CN107731252B CN201710674694.0A CN201710674694A CN107731252B CN 107731252 B CN107731252 B CN 107731252B CN 201710674694 A CN201710674694 A CN 201710674694A CN 107731252 B CN107731252 B CN 107731252B
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programming
string
select transistor
voltage
transistor
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CN107731252A (en
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南尚完
朴商仁
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) Pre-programming, i.e., sequentially selecting a plurality of memory blocks and increasing the threshold voltage of the string select transistor or the ground select transistor of the selected memory block, and (2) after the pre-programming is completed, main programming, i.e., sequentially selecting the plurality of memory blocks, programming the string select transistor or the ground select transistor of the selected memory block, and performing verification by using a verification voltage.

Description

Nonvolatile memory device and memory device including the same
Cross reference to related applications
The present application claims priority from korean patent application No.10-2016-0101997 filed 8/10 in 2016 to the korean intellectual property agency in accordance with 35u.s.c. ≡119, which is hereby incorporated by reference in its entirety.
Technical Field
Embodiments of the present disclosure relate to semiconductor circuits, and more particularly, to a nonvolatile memory device and a memory device including the same.
Background
Storage devices refer to devices that store data under the control of host devices, such as computers, smartphones, and smartpads. Storage devices include devices that store data on magnetic disks, such as Hard Disk Drives (HDDs), or devices that store data on semiconductor memory, particularly non-volatile memory such as Solid State Drives (SSDs) or memory cards.
Nonvolatile memory includes Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable and Programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like.
With the development of semiconductor manufacturing technology, the integration level of memory devices and the capacity thereof are continuously improved. The high integration of memory devices makes it possible to reduce the cost required to manufacture the memory devices. However, the high integration of memory devices results in scaling and structural changes of memory devices, and thus various new problems arise. Since these problems cause damage to data stored in the storage device, the reliability of the storage device may be reduced. There is a need for a method and apparatus that can improve the reliability of a storage device.
Disclosure of Invention
Embodiments of the present disclosure provide a nonvolatile memory device with improved reliability and a memory device including the same.
According to one aspect of the disclosure, a nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The memory cell array includes a plurality of memory blocks (memory blocks), each including a plurality of cell strings, each cell string having a ground selection transistor, a plurality of memory cells, and a string selection transistor. The row decoder circuit is connected to the ground select transistor, memory cell, and string select transistor of each memory block through ground select lines, word lines, and string select lines. The page buffer circuit is connected to the string selection transistors of the cell strings of each memory block through a plurality of bit lines. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform a pre-program, i.e., sequentially selecting the plurality of memory blocks and increasing a threshold voltage of the string selection transistor or the ground selection transistor of the selected memory block, and to perform a main program, i.e., sequentially selecting the plurality of memory blocks, programming the string selection transistor or the ground selection transistor of the selected memory block, and performing verification by using a verification voltage, after the pre-program is completed.
According to another aspect of the disclosure, a storage device includes a non-volatile memory device and a controller that controls the non-volatile memory device. The non-volatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The memory cell array includes a plurality of memory blocks (memory blocks), each including a plurality of cell strings, each cell string having a ground selection transistor, a plurality of memory cells, and a string selection transistor. The row decoder circuit is connected to the ground select transistor, memory cell, and string select transistor of each memory block through ground select lines, word lines, and string select lines. The page buffer circuit is connected to the string selection transistors of the cell strings of each memory block through a plurality of bit lines. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform a pre-program, i.e., sequentially selecting the plurality of memory blocks and increasing a threshold voltage of the string selection transistor or the ground selection transistor of the selected memory block, and to perform a main program, i.e., sequentially selecting the plurality of memory blocks, programming the string selection transistor or the ground selection transistor of the selected memory block, and performing verification by using a verification voltage, after the pre-program is completed.
According to another aspect of the present disclosure, a nonvolatile memory device includes a memory cell array having a plurality of cell strings, each of the cell strings having a selection transistor that selects the cell string for a program, read, or erase operation, and a plurality of memory cells that store data for later retrieval (retrieval). The row decoder circuit addresses the select transistors of each of the cell strings through separate select lines and, for each of the cell strings, addresses each of the memory cells of the cell string through separate word lines. Each of the word lines addresses a single memory cell within each of the cell strings. The page buffer circuit addresses each of the cell strings through a bit line. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform a pre-program operation, i.e., to increase the threshold voltage of each of the select transistors addressed by the bit lines, before performing a program verify operation on any of the select transistors addressed by the bit lines.
Drawings
The above and other objects and features will become apparent from the following description with reference to the following drawings in which like reference numerals refer to like parts throughout the various views unless otherwise specified, and in which:
FIG. 1 is a block diagram illustrating a non-volatile memory device according to an embodiment of the present disclosure;
FIG. 2 illustrates an example of a memory block according to an embodiment of the present disclosure;
FIG. 3 illustrates a problem (issue) that arises when programming string select transistors of a memory block connected to a bit line;
FIG. 4 is a flowchart illustrating a method of operation of a non-volatile memory device according to an embodiment of the present disclosure;
FIG. 5 is a flowchart illustrating an example of pre-programming according to an embodiment of the present disclosure;
FIG. 6 illustrates another example of pre-programming according to an embodiment of the present disclosure;
FIG. 7 illustrates an example of pre-programming according to another embodiment of the present disclosure;
FIG. 8 illustrates an example of pre-programming according to another embodiment of the present disclosure;
FIG. 9 illustrates an example of pre-programming according to another embodiment of the present disclosure;
FIG. 10 shows an option table of options for programming a select transistor and a scheme table of combined options;
FIG. 11 is a block diagram illustrating a storage device according to an embodiment of the present disclosure;
FIG. 12 is a flowchart illustrating an example of a memory device adjusting program options of a select transistor according to an embodiment of the present disclosure; and
Fig. 13 is a flowchart illustrating an example of a memory device determining whether to execute a program option of a selection transistor according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be clearly and in detail described with reference to the accompanying drawings so that those skilled in the art can implement the embodiments of the present invention.
Fig. 1 is a block diagram illustrating a non-volatile memory device 110 according to an embodiment of the present disclosure. Referring to fig. 1, the nonvolatile memory device 110 includes a memory cell array 111, a row decoder circuit 112, a page buffer circuit 113, a data input/output circuit 114, a pass-fail (PFC) check circuit 115, and a control logic circuit 116.
The memory cell array 111 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected to the row decoder circuit 112 through at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL. Each of the memory blocks BLK1 to BLKz may be connected to the page buffer circuit 113 through a plurality of bit lines BL. The memory blocks BLK1 to BLKz may be commonly connected to the bit line BL. The memory cells of the memory blocks BLK1 to BLKz may have the same structure.
In an embodiment, each of the memory blocks BLK1 to BLKz may correspond to a unit of an erase operation. The memory cells of the memory cell array 111 may be erased for each memory block. Memory cells belonging to a memory block may be erased at the same time. As another example, each of the memory blocks BLK1 to BLKz may be divided into a plurality of sub-blocks. Each sub-block may correspond to a unit of an erase operation.
The row decoder circuit 112 may be connected to the memory cell array 111 through a plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of string selection lines SSL. The row decoder circuit 112 is controlled by control logic circuit 116. The row decoder circuit 112 may decode an address received from the controller 120 through the input/output channel (refer to fig. 12), and may control application of voltages to the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded address.
For example, during a programming operation, the row decoder circuit 112 may apply a program voltage (program voltage) to selected word lines of a memory block selected by an address, and a pass voltage (pass voltage) may be applied to each unselected word line of the selected memory block. During a read operation, row decoder circuit 112 may apply a select read voltage (selection read voltage) to a selected word line of a memory block selected by an address and a non-select read voltage (non-selection read voltage) to each unselected word line of the selected memory block. During an erase operation, the row decoder circuit 112 may apply an erase voltage (e.g., a ground voltage or a low voltage having a level similar to that of the ground voltage) to the word lines of the memory block selected by the address.
The page buffer circuit 113 is connected to the memory cell array 111 through a bit line BL. The page buffer circuit 113 is connected to the data input/output circuit 114 through a plurality of data lines DL. The page buffer circuit 113 is controlled by the control logic circuit 116.
During a programming operation, the page buffer circuit 113 may store data to be programmed in the memory cells. The page buffer circuit 113 may apply a voltage to the bit line BL based on the stored data. For example, the page buffer circuit 113 may function as a write driver. During a read operation or a verify read operation, the page buffer circuit 113 may sense a voltage on the bit line BL and may store the sensed result. For example, the page buffer circuit 113 may function as a sense amplifier.
The data input/output circuit 114 is connected to the page buffer circuit 113 through a data line DL. The data input/output circuit 114 may output data read by the page buffer circuit 113 to the controller 120 through an input/output channel, and may transmit data received from the controller 120 to the page buffer circuit 113 through the input/output channel.
After verifying the read operation, the pass-fail check circuit 115 may receive the sensing result from the page buffer circuit 113. The pass-fail check circuit PFC may determine a program pass or a program fail based on the received sensing result. For example, during a program verify read operation, the page buffer circuit 113 may count the number of conductive cells (on-cells) that are turned on. When the number of on cells is not less than the threshold, the pass-fail check circuit 115 may determine that the programming operation was unsuccessful (i.e., the programming failed). When the number of pass-fail check circuit 115 is less than the threshold, the pass-fail check circuit 115 may determine that the program operation was successful (that is, the program passed). For example, during an erase verify read operation, the page buffer circuit 113 may count the number of off-cells (off-cells) that are turned off. When the number of on cells is not less than the threshold value, the pass-fail check circuit 115 may determine that the erase operation is unsuccessful (i.e., the erase fails). When the number of off cells is less than the threshold, the pass-fail check circuit 115 may determine that the erase operation was successful (that is, the erase passed). The pass or fail determination may be sent to the control logic 116.
The control logic 116 may receive commands from the controller 120 through input/output channels and may receive control signals from the controller 120 through control channels. The control logic circuit 116 may receive commands through the input/output channels in response to control signals, may route addresses received through the input/output channels to the row decoder circuit 112, and may route data received through the input/output channels to the data input/output circuit 114. The control logic 116 may decode the received command and may control the nonvolatile memory device 110 based on the decoded command.
The control logic circuit 116 includes a Select Transistor Management Block (STMB) 117. The selection transistor management block 117 may manage the selection transistors of the memory blocks BLK1 to BLKz, that is, the threshold voltages of the string selection transistor and the ground selection transistor. For example, the selection transistor management block 117 may perform a program operation for increasing the threshold voltage of the selection transistor. The selection transistor management block 117 may perform a programming operation on the selection transistor through pre-programming and main programming. Also, the selection transistor management block 117 may perform a read operation on the selection transistor to determine whether the threshold voltage of the selection transistor is higher or lower than the read level.
Fig. 2 illustrates an example of a memory block BLKa according to an embodiment of the present disclosure. Referring to fig. 1 and 2, a plurality of cell strings CS may be arranged in rows and columns on a substrate SUB. The cell strings CS may be commonly connected to a common source line (common source line) CSL formed on (or in) the substrate SUB. In fig. 2, the position of the substrate SUB is illustrated to help understand the structure of the memory block BLKa. An embodiment is illustrated in fig. 2, in which a common source line CSL is connected to the lower end of the cell string CS. It is sufficient that the common source line CSL is electrically connected to the lower end of the cell string CS, but embodiments of the present disclosure may not be limited to the case where the common source line CSL is physically arranged at the lower end of the cell string CS. An embodiment is illustrated in fig. 2, in which the cell strings CS are arranged in a 4x4 matrix. However, the number of cell strings CS in the memory block BLKa may be increased or decreased.
The cell strings of each row may be connected to a corresponding one of the first to fourth ground selection lines GSL1 to GSL4 and a corresponding one of the first to fourth string selection lines SSL1 to SSL 4. The cell string of each column may be connected to a corresponding one of the first to fourth bit lines BL1 to BL 4. For ease of explanation, the cell strings connected to the second and third ground selection lines GSL2 and GSL3 or the second and third string selection lines SSL2 and SSL3 are depicted as light colors.
Each cell string CS may include at least one ground selection transistor GST connected to a corresponding ground selection line, a first dummy memory cell DMC1 connected to a first dummy word line DWL1, a plurality of memory cells MC respectively connected to a plurality of word lines WL1 to WL8, a second dummy memory cell DMC2 connected to a second dummy word line DWL2, and a string selection transistor SST respectively connected to a string selection line SSL. In each cell string CS, the ground selection transistor GST, the first dummy memory cell DMC1, the memory cell MC, the second dummy memory cell DMC2, and the string selection transistor SST may be connected to each other in series in a direction perpendicular to the substrate SUB, and may be sequentially stacked (stack) in the direction perpendicular to the substrate SUB.
In an embodiment, as shown in fig. 2, in each cell string CS, one or more dummy memory cells may be arranged between the ground selection transistor GST and the memory cell MC. In each cell string CS, one or more dummy memory cells may be arranged between the string selection transistor SST and the memory cell MC. In each cell string CS, one or more dummy memory cells may be arranged between the memory cells MC. The dummy memory cell may have the same structure as the memory cell MC, and may not be programmed (e.g., program is inhibited) or may be programmed differently from the memory cell MC. For example, when a memory cell is programmed to form two or more threshold voltage distributions, a dummy memory cell may be programmed to form one threshold voltage distribution range or to form a plurality of threshold voltage distributions, the number of which is smaller than the number of threshold voltage distributions of the memory cell MC.
The memory cells of the cell string CS arranged at the same height (or order) from the substrate SUB or the ground selection transistor GST may be electrically connected to each other. The memory cells of the cell string CS arranged at different heights (or sequences) from the substrate SUB or the ground selection transistor GST may be electrically separated from each other. The embodiment is illustrated in fig. 2 as memory cells of the same height being connected to the same word line. However, memory cells of the same height may be directly connected to each other in a plane in which the memory cells are formed, or may be indirectly connected to each other through another layer, such as a metal layer.
The memory block BLKa may be provided as a three-dimensional (3D) memory array. The 3D memory array is integrally formed in one or more physical levels of an array of memory cells MC having active areas disposed over a silicon substrate and circuitry associated with the operation of these memory cells MC. Circuitry associated with the operation of memory cell MC may be located on or within this substrate. The term "monolithic" means that the layers of each level of the array are placed directly on the layers of each underlying (unrerling) level of the 3D memory array.
In embodiments of the present disclosure, a 3D memory array includes vertical NAND strings (or cell strings) that are vertically oriented such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trap (charge trap) layer. Each vertical NAND string may also include at least one select transistor placed over memory cell MC. At least one selection transistor may have the same structure as the memory cell MC and may be formed in correspondence with the memory cell MC.
The following patent documents, which are incorporated by reference herein in their entirety, describe suitable configurations for three-dimensional memory arrays configured in multiple levels with word lines and/or bit lines shared between the levels: U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235 and U.S. Pat. publication No. 2011/023648.
Fig. 3 illustrates a problem that occurs when programming the string selection transistor SST of the memory block BLKa connected to the bit line. In an embodiment, a cell string of the memory block BLKa connected to the second bit line BL2 is shown in fig. 3. In the embodiment, it is assumed that the string selection transistors SST adjacent to the bit line BL2 are connected to the string selection lines SSL1b to SSL4b, and the string selection transistors SST adjacent to the dummy memory cells DMC2 are connected to the string selection lines SSL1a to SSL4a. In an embodiment, the program operation may be sequentially performed for each selection transistor (string selection transistor or ground selection transistor) connected to each selection line (string selection line or ground selection line) of each memory block. For example, it is assumed that a program operation is performed on the string selection transistor SST connected to the string selection line SSL1b of the memory block BLKa.
In an embodiment, the programming operation of the string selection transistor SST may include one or more program loops (program loops). Each program loop may include a program period and a program verify period. The string select transistor SST may be programmed by Fowler-Nordheim (F-N) tunneling (tunneling) or hot electron injection during the programming cycle. For example, the threshold voltage of the string selection transistor may be increased by applying a voltage having a voltage difference causing F-N tunneling to the control gate and channel of the string selection transistor SST. As another example, the threshold voltage of the string selection transistor may be increased by applying a voltage having a voltage difference that causes generation of hot electrons to the drain and source of the string selection transistor SST and applying a voltage that causes injection of hot electrons to the control gate of the string selection transistor SST.
In the program verification period, a positive voltage may be applied to the bit line BL2, a verification voltage may be applied to the control gate of the string selection transistor SST as the program operation target t_pgm through the string selection line SSL1b, and an on voltage may be applied to the word lines WL1 to WL8, the dummy word lines DWL1 and DWL2, the ground selection line GSL, and the string selection lines SSL1a, SSL2a, SSL3a, and SSL4a, respectively, which are connected to the string selection transistors SST not as the program operation target t_pgm. The off voltage is applied to the string selection lines SSL2b to SSL4b connected to string selection transistors located at the same height as the string selection transistors corresponding to the program operation target t_pgm and not the program operation target t_pgm. The turn-on voltage may be a voltage that turns on the corresponding memory cell, the corresponding dummy memory cell, or the corresponding select transistor. The off-voltage may be a ground voltage or a negative voltage.
According to the above condition, the string selection transistor (e.g., the first selection transistor) whose threshold voltage is lower than the verification voltage of the string selection transistor corresponding to the program operation target t_pgm is turned on, and the string selection transistor (e.g., the second selection transistor) whose threshold voltage is higher than the verification voltage of the string selection transistor corresponding to the program operation target t_pgm is turned off. The voltages respectively corresponding to the bit lines of the first selection transistors are discharged (discharge) to the common source line CSL, and the voltages respectively corresponding to the bit lines of the second selection transistors are not discharged to the common source line CSL. That is, it may be determined whether the threshold voltage of the string selection transistor corresponding to the program operation target t_pgm reaches the verifying voltage according to the voltage variation in the bit lines BL1 to BL 4.
When a program operation is performed on the string selection transistor connected to the string selection line SSL1b, the string selection transistor that is located at the same height as the string selection transistor corresponding to the program operation target t_pgm and is not the program operation target t_pgm may not have undergone the program operation yet. That is, after the program operation is performed on the string selection transistors connected to the string selection lines SSL1b, the program operation may be performed on the string selection transistors SST connected to the string selection lines SSL2b to SSL4 b. In this case, the threshold voltages of the string selection transistors SST connected to the string selection lines SSL2b to SSL4b may not have been adjusted, for example, may be lower than the off voltage. More specifically, in manufacturing the memory cell array 111 having the 3D structure as shown in fig. 2, it is very difficult to adjust the threshold voltage of the selection transistor within a desired range. For example, typically, adjusting the threshold voltage of a transistor during fabrication may be accomplished by adjusting the doping concentration of P-type or N-type impurities. However, due to the nature of the process of fabricating the 3D structure memory cell array 111 shown in fig. 2, at least some of the select transistors are located where it is difficult to dope with P-type or N-type impurities. Thus, the threshold voltages of the at least some select transistors may not be adjusted and may be lower than the off voltage.
When the threshold voltage of the string selection transistors SST connected to the string selection lines SSL2b to SSL4b is lower than the off voltage, the string selection transistors SST connected to the string selection lines SSL2b to SSL4b are turned on in the program verification period. Accordingly, the voltage of the bit line BL2 is leaked (or released) to the common source line CSL (refer to "LC") through the string selection transistors SST connected to the string selection lines SSL2b to SSL4 b. That is, since the threshold voltage of the string selection transistor SST corresponding to the program operation target t_pgm is generally lower than the verification voltage, the operation of the program verification period may not be normally performed.
The above-described problem may also occur when the program operation is performed on the other string selection transistor SST or the ground selection transistor GST in the memory block BLKa. Also, the above-described problem is not limited to one memory block. Since the memory blocks BLK1 to BLKz (refer to fig. 1) share bit lines, the above-described problem may occur in all the memory blocks BLK1 to BLKz. For example, each of the memory blocks BLK1 to BLKz may have the same structure as that shown in fig. 2 and 3. The bit lines BL1 to BL4 are commonly connected to the memory blocks BLK1 to BLKz. Accordingly, when a program operation is performed on the select transistor of the memory block BLK1, an off voltage is supplied to the remaining memory blocks BLK2 to BLKz. The off-voltage may be a ground voltage or a negative voltage. If the select transistors of the remaining memory blocks BLK2 to BLKz have not been programmed, the voltages of the bit lines BL1 to BL4 may be released through the memory blocks BLK2 to BLKz when a program operation is performed on the select transistors of the memory block BLK 1.
To solve the above-described problems, the nonvolatile memory device 110 according to the embodiment of the present disclosure programs the selection transistor through pre-programming and main programming. Each of the pre-programming and the main programming is performed for each matrix of the memory blocks BLK1 to BLKz sharing one set of bit lines BL1 to BL4 or for each set of bit lines BL1 to BL 4. The pre-programming is performed on all memory blocks BLK1 to BLKz sharing the set of bit lines BL1 to BL 4. The pre-programming is performed to increase the threshold voltage of the select transistor to the extent that the select transistor is turned off by the off voltage. The main programming is performed after the pre-programming is completed. The main programming is performed on all memory blocks BLK1 to BLKz sharing the set of bit lines BL1 to BL 4. Main programming is performed to adjust the threshold voltage of the selection transistor to a target level or higher.
In an embodiment, two or more pads (mat) may be provided in the memory cell array 111. Each pad may include a plurality of memory blocks. The memory blocks of each pad share bit lines, and the memory blocks of different pads do not share bit lines. For example, the memory blocks of the first pad may share a first bit line group, or may share a second bit line group that does not overlap with the first bit line group of the memory blocks of the second pad. When two or more pads are provided, the programming operations of the selection transistors of different pads may be performed independently of each other. For example, the pre-programming and the main programming may be performed in the second pad, regardless of whether the pre-programming or the main programming is performed on the select transistors of the first pad. In each pad, the main programming may be performed after the pre-programming is performed.
Fig. 4 is a flowchart illustrating a method of operation of the non-volatile memory device 110 according to an embodiment of the present disclosure. Referring to fig. 1 and 4, in operation S110, pre-programming is performed to increase the threshold voltages Vth of the selection transistors of all the memory blocks BLK1 to BLKz sharing a bit line. If the pre-programming is performed, the threshold voltages of the selection transistors (string selection transistors or ground selection transistors) of the memory blocks BLK1 to BLKz may be increased to such an extent as to be turned off by the off voltage. After the pre-programming is completed for each of the memory blocks BLK1 to BLKz, main programming is performed in operations S120 to S190.
In operation S120, one of the memory blocks BLK1 to BLKz is selected. In operation S130, a selection transistor as a programming target in the selected memory block is selected. For example, a selection transistor (string selection transistor or ground selection transistor) connected to one selection line (string selection line or ground selection line) in a selected memory block may be selected as a programming target. As another example, selection transistors connected to two or more selection lines may be simultaneously selected as a programming target. As another example, all string select transistors or all ground select transistors of a selected memory block may be simultaneously selected as programming targets.
In operation S140, the control logic circuit 116 controls the row decoder circuit 112 and the page buffer circuit 113 to program the select transistors of the selected memory block and verifies the programmed select transistors by using the target verification voltage. For example, when the programming target corresponds to two or more select lines, the select transistors of the two or more select lines may be programmed simultaneously. The select transistors of the two or more select lines may be verified for each select line, or the select transistors of the two or more select lines may be verified simultaneously.
For example, the voltage parameter of the string select transistor may be different from the voltage parameter of the ground select transistor. For example, the voltage parameters may include: a program start voltage to be applied to a select transistor of a program target in a first program loop; an increment of the programming voltage at the programming cycle iteration; a verification voltage to be applied to a select transistor of a programming target in verification; and the maximum number of programming cycles, etc.
In operation S150, it is determined whether the selection transistor is successfully programmed (passed) according to the verification result. For example, if the number of selection transistors whose threshold voltage is lower than the verification voltage of the memory cell of the program target (i.e., the number of on cells) is not greater than the reference value, it is determined that programming passes, and the process proceeds to operation S160. If the number of on cells is greater than the reference value, the process proceeds to operation S180.
In operation S160, it is determined whether the programmed and verified select transistor is the last select transistor of the selected memory block. If the programmed and verified select transistor is the last select transistor of the selected memory block, the process proceeds to operation S170. If the selected transistor being programmed and verified is not the last select transistor of the selected memory block, other select transistors of the memory block selected in operation S130 are selected as programming targets.
In operation S170, it is determined whether the selected memory block is the last memory block among the memory blocks BLK1 to BLKz. If the selected memory block is not the last memory block, a next memory block is selected in operation S120. If the selected memory block is the last memory block, programming of the select transistor is ended.
If it is determined in operation S150 that programming fails, the process proceeds to operation S180. In operation S180, it is determined whether the program loop is a maximum loop. The maximum loop indicates the limit to which the programming loop is repeated and may be set at the time of manufacturing the nonvolatile memory device 110 or by an external device. If the program loop is not the maximum loop, the program voltage is increased, and the process proceeds to operation S140, in which the same select transistor is programmed and verified. If the program loop is the maximum loop, in operation S190, a program failure is determined and a failure process is performed. For example, the failure procedure may include: the selected memory block is classified as a bad block (bad block). Then, operation S170 is performed.
In an embodiment, in a selected memory block, the main programming of the ground select transistor (or string select transistor) may be performed after the main programming of the string select transistor (or ground select transistor) is completed. As another embodiment, in a plurality of memory blocks, the main programming of the ground select transistor (or string select transistor) may be performed after the main programming of the string select transistor (or ground select transistor) is completed. In this case, after operations S120 to S190 are performed on the string selection transistor (or the ground selection transistor), operations S120 to S190 are performed on the ground selection transistor (or the string selection transistor).
Fig. 5 is a flowchart illustrating an example of pre-programming according to an embodiment of the present disclosure. Referring to fig. 1 and 5, one of memory blocks BLK1 to BLKz is selected in operation S210. In operation S220, a selection transistor as a programming target in the selected memory block is selected. For example, a selection transistor (string selection transistor or ground selection transistor) connected to one selection line (string selection line or ground selection line) in the selected memory block may be selected as a programming target. As another example, selection transistors connected to two or more selection lines may be simultaneously selected as a programming target. As another example, all string select transistors or all ground select transistors of a selected memory block may be simultaneously selected as programming targets.
In operation S230, the control logic circuit 116 controls the row decoder circuit 112 and the page buffer circuit 113 to program the select transistors of the selected memory block. The select transistor can be programmed without verification. For example, a select transistor (string select transistor or ground select transistor) in a selected memory block that is connected to one select line (string select line or ground select line) may be programmed. As another example, select transistors connected to two or more select lines may be programmed simultaneously. As another example, the string select transistors or ground select transistors of a selected memory block may be programmed simultaneously. For example, the voltage parameter of the string select transistor may be different from the voltage parameter of the ground select transistor.
In operation S240, it is determined whether the program loop is a maximum loop. The maximum loop indicates the limit to which the programming loop is repeated and may be set at the time of manufacturing the nonvolatile memory device 110 or by an external device. The preprogrammed maximum loop may be less than the main programmed maximum loop. If the program loop is not the maximum loop, the program voltage is increased, and the process proceeds to operation S230, in which the same select transistor is programmed. If the programming cycle is the maximum cycle, the process proceeds to operation S250.
In operation S250, it is determined whether the programmed select transistor is the last select transistor of the selected memory block. If the programmed select transistor is the last select transistor of the selected memory block, the process proceeds to operation S260. If the programmed select transistor is not the last select transistor of the selected memory block, other select transistors of the memory block selected in operation S220 are selected as programming targets.
In operation S260, it is determined whether the selected memory block is the last memory block among the memory blocks BLK1 to BLKz. If the selected memory block is not the last memory block, another memory block is selected in operation S210. If the selected memory block is the last memory block, programming of the select transistor is ended.
In an embodiment, in a selected memory block, the pre-programming of the ground select transistor (or string select transistor) may be performed after the pre-programming of the string select transistor (or ground select transistor) is completed. As another embodiment, in a plurality of memory blocks, the pre-programming of the ground select transistor (or string select transistor) may be performed after the pre-programming of the string select transistor (or ground select transistor) is completed. In this case, after operations S210 to S260 are performed on the string selection transistor (or the ground selection transistor), operations S210 to S260 are performed on the ground selection transistor (or the string selection transistor).
As described with reference to fig. 5, the pre-programming includes: the programming voltage is applied to the select transistor of the programming operation target at a given frequency (e.g., maximum cycle) without verification. The threshold voltage of the selection transistor corresponding to the program target can be adjusted to be higher than the off voltage by applying the program voltage at a given frequency.
For example, the pre-programmed program start voltage may be lower than the program start voltage of the main program. The increment of the pre-programmed programming voltage may be greater than the increment of the main programmed programming voltage.
Fig. 6 illustrates another example of pre-programming according to an embodiment of the present disclosure. Operations S310, S320, and S340 to S370 of fig. 6 are performed identically to operations S210, S220, and S240 to S270 of fig. 5, and thus a description thereof is omitted.
In operation S330, the control logic circuit 116 controls the row decoder circuit 112 and the page buffer circuit 113 to program the select transistor selected as a program target in the selected memory block, and verifies the programmed select transistor by using a verification voltage. For example, a select transistor (string select transistor or ground select transistor) in a selected memory block that is connected to one select line (string select line or ground select line) may be programmed and verified. As another example, select transistors connected to two or more select lines may be verified simultaneously or sequentially after being programmed simultaneously. As another example, the string select transistors or ground select transistors of a selected memory block may be programmed simultaneously. For example, the voltage parameter of the string select transistor may be different from the voltage parameter of the ground select transistor.
As described with reference to fig. 5, verification may be performed in a pre-program. The select transistor that passes verification may be program inhibited in the next program cycle. For example, the select transistor that passes verification may be program inhibited by applying a program inhibit voltage to the corresponding bit line. Even if verification of the select transistor corresponding to the program target is unsuccessful (verification failure), that is, even if there is a select transistor whose threshold voltage is lower than the verification voltage, if the program loop is the maximum loop, the pre-programming can be ended. For example, the pre-programming may be identified as normally completed without a failed process.
For example, the pre-programmed verify voltage may be lower than the main programmed verify voltage.
Fig. 7 illustrates an example of pre-programming according to another embodiment of the present disclosure. Referring to fig. 1, 5 and 7, operations S410 to S435 are the same as operations S210 to S260 of fig. 5. Also, operations S460 to S485 are the same as operations S210 to S260 of fig. 5. That is, in the embodiment of fig. 7, the pre-programming may include two or more programming operations. Each programming operation includes: the programming cycle is repeated at maximum cycle without verification, as described with reference to FIG. 5. The program start voltage of the first program operation (operation S410 to operation S435) may be lower than the program start voltage of the second program operation (operation S460 to operation S465). The increment of the program voltage of the first program operation (operation S410 to operation S435) may be greater than the increment of the program voltage of the second program operation (operation S460 to operation S465). The maximum loop of the first program operation (operation S410 to operation S435) may be equal to or less than the maximum loop of the second program operation (operation S460 to operation S465).
Fig. 8 illustrates an example of pre-programming according to another embodiment of the present disclosure. Referring to fig. 1, 6 and 8, operations S510 to S540 are the same as operations S310 to S370 of fig. 6. Also, operations S560 to S590 are the same as operations S310 to S370 of fig. 6. That is, in the embodiment of fig. 8, the pre-programming may include two or more programming operations. As described with reference to fig. 6, each program operation includes repeating a program loop in a maximum loop in which a select transistor corresponding to a program target is programmed and verified. The program start voltage and the verify voltage of the first program operation (operation S510 to operation S540) may be lower than those of the second program operation (operation S560 to operation S590). The increment of the program voltage of the first program operation (operation S510 to operation S540) may be greater than the increment of the program voltage of the second program operation (operation S560 to operation S590). The maximum loop of the first program operation (operation S510 to operation S540) may be equal to or less than the maximum loop of the second program operation (operation S560 to operation S590).
Fig. 9 illustrates an example of pre-programming according to another embodiment of the present disclosure. Referring to fig. 1, 5, 6 and 9, operations S610 to S635 are the same as operations S210 to S260 of fig. 5. Also, operations S660 to S690 are the same as operations S310 to S370 of fig. 6. That is, in the embodiment of fig. 9, the pre-programming may include two or more programming operations. At least one of the two or more programming operations includes: the programming cycle is repeated at maximum cycle without verification, as described with reference to FIG. 5. As described with reference to fig. 6, at least another one of the two or more programming operations includes: the programming cycle is repeated at a maximum cycle in which the select transistor corresponding to the programming target is programmed and verified. The program start voltage of the first program operation (operations S610 to S635) may be lower than the program start voltage of the second program operation (operations S660 to S690). The increment of the program voltage of the first program operation (operations S610 to S635) may be greater than the increment of the program voltage of the second program operation (operations S660 to S690). The maximum loop of the first program operation (operations S610 to S635) may be equal to or less than the maximum loop of the second program operation (operations S660 to S690).
In fig. 9, the pre-programming is described as performing the programming operation of fig. 6 after performing the programming operation of fig. 5. However, the pre-programming may be modified or changed to perform the programming operation of FIG. 5 after performing the programming operation of FIG. 6.
Fig. 10 shows an option table OT for programming options of the selection transistor and a scheme table ST in which the options are combined. Referring to fig. 1 and 10, the option table OT includes a first option "a", a second option "B", a third option "C", and a fourth option "D". The first option "a" includes the pre-programming of the string select transistors SST of the memory blocks BLK1 to BLKz. The second option "B" includes the pre-programming of the ground selection transistors GST of the memory blocks BLK1 to BLKz. The third option "C" includes the main programming of the string select transistors SST of the memory blocks BLK1 to BLKz. The fourth option "D" includes the main programming of the ground selection transistors GST of the memory blocks BLK1 to BLKz.
Referring to the scheme table ST, the nonvolatile memory device 110 may perform a program operation of the selection transistor based on the first to fifth schemes. In a first scheme, the nonvolatile memory device 110 may perform pre-programming once for the selection transistor and may perform main programming once for the selection transistor. The nonvolatile memory device 110 may perform the first option "a" and the second option "B" without being in sequence. The nonvolatile memory device 110 may execute the first option "a" and the second option "B" regardless of the order thereof. That is, the nonvolatile memory device 110 may perform the main programming (e.g., option "C" followed by option "D" and vice versa) after the pre-programming of the select transistor is completed.
In the second scheme, the nonvolatile memory device 110 may sequentially perform the pre-programming (first option "a") and the main programming (third option "C") of the string selection transistor SST, and may sequentially perform the pre-programming (second option "B") and the main programming (fourth option "D") of the ground selection transistor GST. Alternatively, the nonvolatile memory device 110 may sequentially perform the pre-programming (the second option "B") and the main programming (the fourth option "D") of the ground selection transistor GST, and may sequentially perform the pre-programming (the first option "a") and the main programming (the third option "C") of the string selection transistor SST.
In a third scheme, the nonvolatile memory device 110 may perform pre-programming on the selection transistor twice, and may perform main programming on the selection transistor once. The nonvolatile memory device 110 may perform the first option "a" and the second option "B" without being in sequence. After executing the first option "a" and the second option "B", the nonvolatile memory device 110 may execute the first option "a" and the second option "B" again regardless of the order thereof. After the first option "a" and the second option "B" are performed again, the nonvolatile memory device 110 may perform the third option "C" and the fourth option "D" regardless of the order thereof. That is, the nonvolatile memory device 110 may perform the second pre-programming after performing the first pre-programming of the selection transistor, and may perform the main programming after performing the second pre-programming.
In the fourth scheme, the nonvolatile memory device 110 may perform the pre-programming of the ground selection transistor GST (the second option "B") twice after performing the pre-programming of the string selection transistor SST (the first option "a") twice. Alternatively, the nonvolatile memory device 110 may perform the pre-programming of the string selection transistor SST (the first option "a") twice after performing the pre-programming of the ground selection transistor GST (the second option "B") twice. The nonvolatile memory device 110 may then perform the main programming of the select transistor (third option "C" and fourth option "D") regardless of its order.
In the fifth aspect, the nonvolatile memory device 110 may perform the pre-programming (the second option "B") and the main programming (the fourth option "D") of the ground selection transistor GST after the pre-programming (the first option "a") and the main programming (the third option "C") of the string selection transistor SST are completed. Alternatively, the nonvolatile memory device 110 may perform the pre-programming (first option "a") and the main programming (third option "C") of the string selection transistor SST after the pre-programming (second option "B") and the main programming (fourth option "D") of the ground selection transistor GST are completed.
In short, after the pre-programming of the selection transistors located at the same height (refer to fig. 2) in the memory blocks BLK1 to BLKz is completed, the main programming is performed. When the pre-programming includes two or more program operations, a second pre-programming is performed after the first pre-programming of the select transistors located at the same height in the memory blocks BLK1 to BLKz is completed. In the above condition, the first option "a", the second option "B", the third option "C", and the fourth option "D" may be variously combined, not limited to the combination of the scheme table ST.
The select transistor programming method described with reference to fig. 1 through 10 may generally be performed in a test step after the nonvolatile memory device 110 is manufactured. However, the select transistor programming method described with reference to fig. 1 through 10 may be performed under the control of an external device (e.g., the controller of fig. 11) after the nonvolatile memory device 110 is manufactured and tested.
Fig. 11 is a block diagram illustrating a storage device 100 according to an embodiment of the present disclosure. Referring to fig. 11, the storage device 100 includes a nonvolatile memory device 110, a controller 120, and a buffer memory 130.
The nonvolatile memory device 110 may perform write operations, read operations, and erase operations under the control of the controller 120. The nonvolatile memory device 110 may receive a write command, an address, and data from the controller 120, and may write the data to a memory space corresponding to the address. The nonvolatile memory device 110 may receive a read command and an address from the controller 120, may read data from a memory space corresponding to the address, and may output the read data to the controller 120. The nonvolatile memory device 110 may receive an erase command and an address from the controller 120 and may erase data of a memory space corresponding to the address.
For example, the nonvolatile memory device 110 may have the same structure and manner as described with reference to fig. 1 to 10. For example, the nonvolatile memory device 110 may include a selection transistor management block 117, and the selection transistors may be programmed in pad units under the control of the selection transistor management block 117.
The controller 120 may access the nonvolatile memory device 110 and the buffer memory 130. The controller 120 may perform a write operation, a read operation, and an erase operation in response to a request of an external host device (not shown). The controller 120 may write data requested to be written to the nonvolatile memory device 110, and may read data requested to be read from the nonvolatile memory device 110 to output the read data to an external host device.
The controller 120 may manage the storage device 100 by using the buffer memory 130. For example, the controller 120 may temporarily store data to be written to the nonvolatile memory device 110 or data read from the nonvolatile memory device 110 in the buffer memory 130. The controller 120 may load metadata required to manage the nonvolatile memory device 110 on the buffer memory 130.
The controller 120 includes a Select Transistor Management Unit (STMU) 121. The select transistor managing unit 121 may adjust various options or parameters used when the non-volatile memory device 110 programs the select transistor.
In an embodiment, the controller 120 may adjust the patterns of the memory blocks BLK1 to BLKz based on the wear or degradation degree of the memory blocks BLK1 to BLKz. When the controller 120 adjusts the modes of the memory blocks BLK1 to BLKz, the controller 120 may request the nonvolatile memory device 110 to adjust the threshold voltages of the selection transistors so as to correspond to the adjusted modes. For example, if the threshold voltage of the select transistor of each memory block needs to be increased due to a mode change, the controller 120 may request the nonvolatile memory device 110 to increase the threshold voltage of the select transistor through an additional program operation. If the threshold voltage of the select transistor of each memory block needs to be lowered due to a mode change, the controller 120 may request the nonvolatile memory device 110 to lower the threshold voltage of the select transistor through an erase operation and then increase the threshold voltage of the select transistor through a program operation. The erase verify voltage used in erasing the select transistor may be equal to or higher than the erase verify voltage used in erasing the memory cell. For example, the range of threshold voltages of the erased select transistors may be equal to or higher than the range of threshold voltages of the erased memory cells.
Fig. 12 is a flowchart illustrating an example of the memory device 100 adjusting programming options of a select transistor according to an embodiment of the present disclosure. Referring to fig. 1, 11 and 12, the controller 120, more particularly, the selection transistor management unit 121 may receive block information in operation S710. For example, the block information may be information having an influence on the threshold voltage of the selection transistor or information influenced by the threshold voltage of the selection transistor. The block information may be received from an external host device or may be determined according to an internal policy (policy) of the controller 120. The block information may include information regarding whether each of the memory blocks BLK1 to BLKz operates in any of the following modes: single-level cell (SLC) mode, multi-level cell (MLC) mode, triple-level cell (TLC) mode, quad-level cell (QLC) mode, and a level mode higher than the QLC mode.
In operation S720, the selection transistor management unit 121 may select the target threshold voltage Vth for each memory block based on the block information. For example, when each memory block operates in a higher-level mode, a higher target threshold voltage may be selected. When each memory block is operating in a lower level mode, a lower target threshold voltage may be selected.
In operation S730, the selection transistor management unit 121 may adjust a program parameter of each memory block based on a target threshold voltage of each memory block. For example, when the target threshold voltage of each memory block becomes high, the program start voltage or verify voltage of the pre-program or main program associated with the select transistor may be adjusted high. When the target threshold voltage of each memory block becomes low, the program start voltage or verify voltage of the pre-program or main program associated with the select transistor may be adjusted down.
In operation S740, the selection transistor management unit 121 may transmit the adjusted program parameters to the nonvolatile memory device 110, more specifically, the selection transistor management block 117.
In operation S750, the selection transistor management unit 121 may control the nonvolatile memory device 110 to program the selection transistor in the method described with reference to fig. 4.
In the illustrated embodiment, the controller 120 sends programming parameters that are adjusted according to the target threshold voltage to the nonvolatile memory device 110. However, the controller 120 may transmit information about the target threshold voltage of each memory block to the nonvolatile memory device 110. The nonvolatile memory device 110 may adjust a program parameter of each memory block based on information of a target threshold voltage of each memory block, and may perform pre-programming and main programming of the selection transistor based on the adjusted parameter. As another example, the controller 120 may send block information to the non-volatile memory device 110. The nonvolatile memory device 110 may select a target threshold voltage of each memory block based on the block information, may adjust a program parameter of each memory block based on the target threshold voltage of each memory block, and may perform pre-programming and main programming of the selection transistor based on the adjusted parameter.
Fig. 13 is a flowchart illustrating an example in which the memory device 110 determines whether to perform a programming option of a select transistor according to an embodiment of the present disclosure. Referring to fig. 1, 11 and 13, in operation S910, the controller 120, more particularly, the selection transistor management unit 121 may control the nonvolatile memory device 110 to check the threshold voltage Vth of the selection transistor.
In an embodiment, environmental noise or interference generated in the erase operation, the program operation, and the read operation performed in the memory blocks BLK1 to BLKz may cause the threshold voltage of the selection transistor to go high or low. The selection transistor may be turned off at an on time or may be turned on at an off time if the threshold voltage of the selection transistor is out of a normal range. Accordingly, the selection transistor managing unit 121 may control the nonvolatile memory device 110 to check the threshold voltage of the selection transistor periodically, at an idle time, or when a program, read, or erase error is generated.
For example, the nonvolatile memory device 110 may perform a read operation by using one read level (read level). That is, the selection transistor managing unit 121 may determine whether the threshold voltage of the selection transistor is lower than the read level or higher than the read level. The nonvolatile memory device 110 may perform a read operation by using two read levels. That is, the selection transistor managing unit 121 may determine whether the threshold voltage of the selection transistor belongs to or leaves the range defined by the two read levels. For example, the selection transistor management unit 121 may randomly select one or more of the memory blocks BLK1 to BLKz, or may select a memory block in which an error is generated among the memory blocks BLK1 to BLKz. The selection transistor managing unit 121 may control the nonvolatile memory device 110 to check threshold voltages of all or some of the selection transistors of the selected memory block.
In operation S920, the selection transistor management unit 121 may determine whether the threshold voltage of the checked selection transistor is within the target range. For example, when the threshold voltage of the checked selection transistor is lower than the read level, when the threshold voltage of the checked selection transistor is higher than the read level, or when the threshold voltage of the checked selection transistor is within a range defined by the read level, the selection transistor management unit 121 may determine that the threshold voltage of the checked selection transistor is within a target range. If the threshold voltage of the selected transistor under inspection is within the target range, the process ends.
If the threshold voltage of the checked selection transistor is not within the target range, the process proceeds to operation S930. In operation S930, the controller 120 may control the nonvolatile memory device 110 to program the selection transistor in the method described with reference to fig. 4.
According to embodiments of the present disclosure, the threshold voltage of the selection transistor may be concentrated within a target range. Accordingly, it is possible to provide a nonvolatile memory device having improved reliability and a storage device including the nonvolatile memory device.
Although the present disclosure has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure. Accordingly, it should be understood that the above embodiments are not limiting, but rather illustrative.

Claims (20)

1. A non-volatile memory device, comprising:
a memory cell array including a plurality of memory blocks, each memory block including a plurality of cell strings, each cell string including a ground selection transistor, a plurality of memory cells, and a string selection transistor;
a row decoder circuit connected to the ground select transistor, the memory cell, and the string select transistor of each memory block through a ground select line, a word line, and a string select line;
a page buffer circuit connected to the string selection transistors of the cell strings of each memory block through a plurality of bit lines; and
control logic configured to control the row decoder circuit and the page buffer circuit: (1) Performing pre-programming of programming the string select transistor or the ground select transistor of the selected memory block while sequentially selecting each of the plurality of memory blocks, and (2) performing main programming of programming the string select transistor or the ground select transistor of the selected memory block while sequentially selecting each of the plurality of memory blocks after completing the pre-programming, and performing verification of programming of the string select transistor or the ground select transistor of the selected memory block by using a first verification voltage.
2. The non-volatile memory device of claim 1, wherein during the main programming, two or more string selection transistors among the string selection transistors or two or more ground selection transistors among the ground selection transistors are programmed simultaneously in the selected memory block.
3. The non-volatile memory device of claim 1, wherein during the pre-programming, the string select transistor or the ground select transistor of the selected memory block are programmed simultaneously without verifying that programming is achieved by applying a verification voltage to the string select transistor or ground select transistor of the selected memory block.
4. The non-volatile memory device of claim 1, wherein the string select transistor or the ground select transistor of the selected memory block is reprogrammed a particular number of times during the pre-programming.
5. The non-volatile memory device of claim 1, wherein during the pre-programming, the string select transistor or the ground select transistor of the selected memory block is programmed and subsequently verified using a second verify voltage.
6. The non-volatile memory device of claim 5, wherein:
if the verification result using the second verification voltage indicates pass, the pre-programming ends, and
even if the verification result using the second verification voltage indicates failure, if the string selection transistor or the ground selection transistor of the selected memory block is repeatedly programmed a certain number of times, the pre-programming ends.
7. The non-volatile memory device of claim 1, wherein:
the pre-programming and the main programming repeatedly program the string select transistor or the ground select transistor of the selected memory block while increasing a program voltage step by step,
the pre-programmed program start voltage is lower than the main programmed program start voltage, an
The pre-programmed programming voltage is increased by an amount greater than the main programmed programming voltage.
8. The non-volatile memory device of claim 7, wherein:
during the pre-programming and the main programming, the string select transistor or the ground select transistor of the selected memory block is programmed and then verified, and
the pre-programmed verify voltage is lower than the main programmed verify voltage.
9. The non-volatile memory device of claim 1, wherein:
the pre-programming Cheng Baokuo first and second pre-programming,
the first pre-program programs the string select transistor or the ground select transistor of the selected memory block without verification or while verification is performed by using a second verification voltage, an
After the first pre-programming of the plurality of memory blocks is completed, the second pre-programming programs the string select transistors or the ground select transistors of the selected memory block without verification or while verification is performed by using a third verification voltage.
10. The non-volatile memory device of claim 9, wherein:
the first pre-program and the second pre-program repeatedly program the string select transistor or the ground select transistor of the selected memory block while increasing a program voltage step by step,
the first preprogrammed programming start voltage is lower than the second preprogrammed programming start voltage,
the first pre-programmed programming voltage has an increment greater than the second pre-programmed programming voltage, an
The second verify voltage is lower than the third verify voltage.
11. The non-volatile memory device of claim 1, wherein after the pre-programming of the string select transistors and the ground select transistors of the plurality of memory blocks is completed, the control logic circuit controls the row decoder circuit and the page buffer circuit to perform the main programming of string select transistors and ground select transistors of the plurality of memory blocks.
12. The non-volatile memory device of claim 1, wherein after the pre-programming and the main programming of string select transistors of the plurality of memory blocks are completed, the control logic circuit controls the row decoder circuit and the page buffer circuit to perform the pre-programming and the main programming of ground select transistors of the plurality of memory blocks.
13. A storage device, comprising:
a nonvolatile memory device including a plurality of memory blocks, each memory block including a plurality of cell strings, each cell string including a ground selection transistor, a plurality of memory cells, and a string selection transistor; and
a controller configured to control the nonvolatile memory device, wherein
The non-volatile memory device: (1) Performing pre-programming of programming the string select transistor or the ground select transistor of the selected memory block while sequentially selecting each of the plurality of memory blocks, and (2) performing main programming of programming the string select transistor or the ground select transistor of the selected memory block while sequentially selecting each of the plurality of memory blocks after completing the pre-programming, and performing verification of programming of the string select transistor or the ground select transistor of the selected memory block by using a first verification voltage.
14. The memory device of claim 13, wherein the controller classifies the plurality of memory blocks into two or more types, adjusts a programming parameter of each memory block based on a classification result, transmits the programming parameter to the nonvolatile memory device, and controls the nonvolatile memory device to perform the pre-programming and the main programming based on the programming parameter.
15. The storage device of claim 13, wherein:
the controller controls the nonvolatile memory device to check threshold voltages of string select transistors or ground select transistors of all or some of the plurality of memory blocks, an
The controller controls the nonvolatile memory device to perform the pre-programming and the main programming for all or some of the plurality of memory blocks when at least some of the checked threshold voltages are below a target threshold voltage.
16. A non-volatile memory device, comprising:
a memory cell array comprising a plurality of cell strings, each of the cell strings comprising a select transistor that selects the cell string for a program, read, or erase operation and a plurality of memory cells that store data for later retrieval;
a row decoder circuit for addressing each of said memory cells of each of said cell strings by individually addressing said select transistors of each of said cell strings and, for each of said cell strings, by individually word lines, each of said word lines addressing a single memory cell within each of said cell strings;
a page buffer circuit addressing all of the cell strings through the same bit line; and
and a control logic circuit that controls the row decoder circuit and the page buffer circuit to perform a pre-program operation, i.e., to increase a threshold voltage of each of the select transistors addressed by the bit lines, before performing a program verify operation on any of the select transistors addressed by the bit lines.
17. The non-volatile memory device of claim 16, wherein the threshold voltage of each of the select transistors is increased beyond an off voltage of the select transistor.
18. The non-volatile memory device of claim 16, wherein each of the select transistors is a string select transistor that is turned on to provide a current path to the bit line for a cell string to which the string select transistor belongs, and is turned off to not provide the current path to the bit line for the cell string to which the string select transistor belongs.
19. The non-volatile memory device of claim 16, wherein each of the select transistors is a ground select transistor that is turned on to provide a current path to a reference potential for the cell string to which the ground select transistor belongs, and is turned off to not provide the current path to the reference potential for the cell string to which the ground select transistor belongs.
20. The non-volatile memory device of claim 16, wherein:
Each of the cell strings includes two select transistors,
a first of the two selection transistors is a string selection transistor that is turned on to provide a current path to the bit line for the cell string to which the string selection transistor belongs, and is turned off to not provide the current path to the bit line for the cell string to which the string selection transistor belongs,
a second one of the two selection transistors is a ground selection transistor that is turned on to provide a current path to a reference potential for the cell string to which the ground selection transistor belongs, and is turned off to not provide the current path to the reference potential for the cell string to which the ground selection transistor belongs, an
The pre-programming operation includes:
increasing a threshold voltage of each string selection transistor addressed by the bit line before performing a program verify operation on any of the string selection transistors addressed by the bit line, an
The threshold voltage of each ground select transistor addressed by the bit line is increased before performing a program verify operation on any of the ground select transistors addressed by the bit line.
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