CN113394179A - Electronic component with multilayer carrier structure - Google Patents
Electronic component with multilayer carrier structure Download PDFInfo
- Publication number
- CN113394179A CN113394179A CN202110525078.5A CN202110525078A CN113394179A CN 113394179 A CN113394179 A CN 113394179A CN 202110525078 A CN202110525078 A CN 202110525078A CN 113394179 A CN113394179 A CN 113394179A
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- CN
- China
- Prior art keywords
- chip
- layer
- lattice
- silver
- electronic component
- Prior art date
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052709 silver Inorganic materials 0.000 claims abstract description 12
- 239000004332 silver Substances 0.000 claims abstract description 12
- 239000011159 matrix material Substances 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000002844 melting Methods 0.000 claims description 10
- 230000008018 melting Effects 0.000 claims description 10
- 239000011135 tin Substances 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000001816 cooling Methods 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 239000011148 porous material Substances 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 3
- 230000005484 gravity Effects 0.000 claims description 2
- 239000012943 hotmelt Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000002861 polymer material Substances 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 abstract 2
- 239000011247 coating layer Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 3
- 238000009423 ventilation Methods 0.000 description 3
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 2
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
The invention discloses an electronic element with a multilayer slide structure, which is provided with a multilayer connection structure of a lead frame slide holder, a silver coating layer, a dot matrix layer and a chip; the lattice layer is a plurality of pit lattice structures which are arranged at intervals and have certain height, each pit has certain height, and the slide holder is not directly contacted with the chip. The multilayer structure of the invention ensures that the chip has good heat dissipation and the heat transfer and heat dissipation characteristics can be controlled.
Description
Technical Field
The invention relates to a chip packaging technology of a microelectronic device.
Background
The chip package is a housing for mounting a semiconductor integrated circuit chip, and has functions of mounting, fixing, sealing, protecting the chip, and enhancing the electrothermal performance. The chip package is a bridge for communicating the internal world of the chip with an external circuit, the chip is firstly connected with the lead frame, the connection point of the chip is connected to the pin of the lead frame by a lead, then the chip and the part of the pin are packaged in the shell, and the pin is connected with other devices by the lead on the printed board. The package plays an important role in CPU and other LSI integrated circuits, the pin number is increased, the pin pitch is reduced, the weight is reduced, the reliability is improved, and the use is more convenient.
Application No.: 2010101679613 discloses a dual lead frame multi-chip common package and its manufacturing method, comprising two lead frames; the chip comprises a plurality of chips, a first chip, a second chip and a third chip; the first chip is arranged on the first lead frame, the second chip and the third chip are arranged on the second lead frame together, and the third chip is a bypass capacitor; and the two connecting pieces are respectively a top connecting piece and a three-dimensional connecting piece, the top connecting piece is connected with the top contact area of the second chip and the external pin of the first lead frame, and the top connecting piece is simultaneously connected with the top contact area of the third chip. The present invention does not refer to the technology of forming a multi-layer structure by a single chip and a stage.
Application No.: 2020204249404 discloses a slide holder for chip detection, which comprises a plate body, the plate body is provided with the location boss, all is provided with clamp plate mechanism on the plate body that is located location boss both sides, and clamp plate mechanism includes first clamp plate and second clamp plate, and first clamp plate is articulated mutually with the plate body through first round pin axle, and the second clamp plate is articulated mutually with the plate body through second round pin axle. The utility model discloses a chip heat dissipation is good inadequately, and heat transfer cooling mode remains to improve.
Application No.: 2013105500841 discloses a plastic package lead frame with pockmarks, which is composed of a plurality of lead frame units in a single row, wherein the substrate is provided with a heat radiating fin and a bonding area, the bonding area is provided with 200 and 250 uniformly distributed pockmarks, and the pockmarks in the bonding area are polymer adhesives, which are helpful for heat radiation but do not have good up-and-down heat transfer effect; the arrangement and combination structure of the pockmarks is single, and the components of different parts of the pockmarks have no special design and special effect.
Disclosure of Invention
The invention content is as follows:
the electronic element with the multilayer slide structure has the advantages of fast heat transfer, good heat dissipation and strong designability of the chip.
The technical scheme is as follows:
the electronic element with the multilayer slide structure provided by the invention has a multilayer connection structure of a lead frame slide holder, a silver coating (or a structure for increasing the conductivity and the corrosion resistance), a dot matrix layer and a chip (the bottom of the chip can also be plated with silver, so that the conductivity is increased or the heat conduction and heat transfer effects are improved).
The lattice layer is a plurality of pit lattice structures which are arranged at intervals and have certain height, each pit has certain height, the lower end of the pit is ensured to be contacted with the chip carrying platform, the upper end of the pit is contacted with the chip, but the chip carrying platform is not directly contacted with the chip.
Moreover, a certain distance is reserved between the pits and bonding points (connection points of the chip and bonding wires or electrode connection points) of the chip (the bonding points of the chip are preferably arranged on the upper surface of the chip, the pits are only contacted with the bottom of the chip, the periphery of the bonding points is preferably provided with an insulating frame (formed by injection of a substrate material or later-stage epitaxy and sputtering technology) made of a high-purity silicon material or a non-conductive high polymer material, the peripheral height of the insulating frame is further preferably larger than the inner peripheral height, short circuit caused by the fact that a dot matrix layer material is turned upwards to contact the middle bonding part of the upper layer of the chip is avoided, meanwhile, a tight locking structure with the smooth surface and the inward concave inner surface of a plastic sealing layer is formed after packaging, and good insulation between the bonding points and the pits is guaranteed.
The function of the lattice layer: gaps are formed among the chip carrying table and the chip, the electric conduction and the heat conduction and the pits for air cooling and heat dissipation (ventilation in the horizontal direction and heat transfer in the plumb direction).
The material of the lattice layer has the following composition: 90-97% of tin, 1-3% of silver and 0.5-8% of copper, wherein the tin has better weldability and lower cost, the silver has good electric and thermal conductivity, and the copper has higher heat resistance.
The silver component in the pits in the middle part of the optimized lattice is more, the center of the chip generates more heat, the heat transfer is fast, and the chip is not easy to overheat and damage; the peripheral pockmarks have more tin components, low cost and easy welding repair welding.
Or, the density of the pits in the middle of the optimized dot matrix is low, so that transverse ventilation and heat dissipation are facilitated; the peripheral density degree is higher, and the reliability of the connection between the chip and the slide holder is enhanced.
The heat transfer and heat dissipation data of each part of the chip can be calculated, and electronic components with different heat resistance, heat transfer effects and heat dissipation structures can be designed accordingly.
The manufacturing process comprises the following steps:
firstly, screen printing solder with sieve pores on a slide holder, or injecting a high molecular adhesive by adopting a mould with the sieve pores; then, heating the dot matrix layer and cooling to solidify the solder or solidify the high molecular components (such as rosin, welding auxiliary soldering tin and other high molecular adhesives which are not purely adhesive) in the dot matrix layer by adopting proper process temperature, pressure (preferably negative pressure) and time; then, a chip is welded or bonded (rosin assisted bonding) on the lattice layer.
The re-welding or bonding of the chip is to use the material of the dot matrix layer as a connecting material, and the heating welding temperature is 20-30 ℃ higher than the process temperature after printing by heating (when the solder is printed and dried for the first time, the solder resist volatilizes, so that the soldering flux is lacked, and the melting point of the solder is improved); or the high polymer component is a hot-melt high polymer, and the heating melting temperature is 5-10 ℃ higher than the melting point of the adhesive (so as to avoid complete melting and pockmark lattice collapse).
Preferably, the melting time is controlled to be longer and the viscous flow property is controlled to be higher in the silk screen with the screen holes, so that the three metal components are settled according to the specific gravity, and the different position proportions of silver, copper and tin are ensured. The bottom layer has more silver and copper, high melting point and high welding temperature with the slide holder, and the welding is sufficient; the upper layer has more tin, low melting point and low temperature for welding with the chip, thereby avoiding the chip from being excessively heated and damaged.
Has the advantages that:
the chip with the multi-layer structure of the lattice layer structure has good ventilation effect and good heat dissipation, and different pockmark material components have different heat transfer characteristics, so that the heat transfer and dissipation are controllable, the service life of the chip is prolonged, and the chip is not easy to be damaged. And the connection of the pit layer, the slide holder and the chip is firm and reliable, and the phenomenon of unsoldering or infirm bonding is not easy to occur.
Drawings
FIG. 1 is a schematic top view of a portion of a slide according to the present invention;
FIG. 2 is a side view of FIG. 1;
fig. 3 is a schematic structural diagram of the pockmark.
In the figure, 1-slide holder; 2-lattice layer; 3-chip; 21-lower end of pockmark; 22-upper end of pockmark.
Detailed Description
The electronic component with the multilayer chip carrier structure shown in fig. 1 and fig. 2 has a multilayer connection structure of a lead frame chip carrier, a dot matrix layer and a chip; the lattice layer is a plurality of pockmark lattice structures which are arranged at intervals and have certain height; the bonding points of the chip are arranged on the upper surface of the chip, and the pits are only contacted with the bottom of the chip.
The product adopts the following manufacturing process in sequence:
firstly, screen printing solder with sieve pores on a slide holder; heating the lattice layer and cooling to solidify the solder or solidify the polymer by adopting proper process temperature, pressure and time; then, the chip is soldered on the lattice layer.
Claims (6)
1. An electronic component having a multilayer carrier sheet structure, comprising: the multi-layer connection structure comprises a lead frame slide holder, a dot matrix layer and a chip; the lattice layer is a plurality of pockmark lattice structures which are arranged at intervals and have certain height; the bonding point of the chip is arranged on the upper surface of the chip, and the pockmark is only contacted with the bottom of the chip; material composition of the lattice layer: 90-97% of tin, 1-3% of silver and 0.5-8% of copper.
2. An electronic device having a multilayer carrier sheet structure as claimed in claim 1, wherein: the periphery of the chip bonding point is provided with an insulating frame made of high-purity silicon material or non-conductive high polymer material.
3. The electronic component having a multilayer carrier sheet structure as claimed in claim 1, wherein: the silver component in the pits in the middle part of the lattice is redundant with the pits in the peripheral part, and the tin component in the peripheral pits is more than that in the middle part.
4. A manufacturing process of an electronic element is characterized in that: fabricating the electronic device with a multilayer carrier structure of claim 1 by the following sequential fabrication process:
firstly, screen printing solder with sieve pores on a slide holder, or injecting a high molecular adhesive by adopting a mould with the sieve pores; heating the lattice layer and cooling to solidify the solder or solidify the polymer by adopting proper process temperature, pressure and time; then, the chip is welded or adhered on the lattice layer.
5. The process for manufacturing an electronic component according to claim 4, wherein: the re-welding or bonding of the chip is to use the material of the dot matrix layer as a connecting material, and heating the connecting material to ensure that the heating welding temperature is 20-30 ℃ higher than the process temperature after printing; or the high-molecular adhesive is hot-melt high-molecular adhesive, and the heating and melting temperature is 5-10 ℃ higher than the melting point of the adhesive.
6. The process for manufacturing an electronic component according to claim 4, wherein: controlling the melting time and the viscosity to enable the three metal components to settle according to specific gravity, and ensuring different position proportions of silver, copper and tin; the bottom layer has more silver, the middle layer has more copper and the upper layer has more tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110525078.5A CN113394179B (en) | 2021-05-14 | 2021-05-14 | Electronic component with multilayer carrier structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110525078.5A CN113394179B (en) | 2021-05-14 | 2021-05-14 | Electronic component with multilayer carrier structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113394179A true CN113394179A (en) | 2021-09-14 |
| CN113394179B CN113394179B (en) | 2022-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110525078.5A Active CN113394179B (en) | 2021-05-14 | 2021-05-14 | Electronic component with multilayer carrier structure |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5299091A (en) * | 1991-03-20 | 1994-03-29 | Hitachi, Ltd. | Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same |
| KR100201379B1 (en) * | 1995-11-17 | 1999-06-15 | 김규현 | Semiconductor chip attaching method and structure using solderable |
| US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
| CN102842558A (en) * | 2012-08-21 | 2012-12-26 | 华天科技（西安）有限公司 | Wafer level chip scale package (WLCSP) multiple chip stackable packaging piece based on solder paste layers and packaging method thereof |
| CN110783304A (en) * | 2019-11-19 | 2020-02-11 | 广东气派科技有限公司 | Packaging welding structure for solving high reliability requirement of 5G GaN chip welding |
-
2021
- 2021-05-14 CN CN202110525078.5A patent/CN113394179B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5299091A (en) * | 1991-03-20 | 1994-03-29 | Hitachi, Ltd. | Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same |
| KR100201379B1 (en) * | 1995-11-17 | 1999-06-15 | 김규현 | Semiconductor chip attaching method and structure using solderable |
| US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
| CN102842558A (en) * | 2012-08-21 | 2012-12-26 | 华天科技（西安）有限公司 | Wafer level chip scale package (WLCSP) multiple chip stackable packaging piece based on solder paste layers and packaging method thereof |
| CN110783304A (en) * | 2019-11-19 | 2020-02-11 | 广东气派科技有限公司 | Packaging welding structure for solving high reliability requirement of 5G GaN chip welding |
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| Publication number | Publication date |
|---|---|
| CN113394179B (en) | 2022-05-17 |
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