CN113393879A - Nonvolatile memory and SRAM mixed storage integrated data fast loading structure - Google Patents

Nonvolatile memory and SRAM mixed storage integrated data fast loading structure Download PDF

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CN113393879A
CN113393879A CN202110461198.3A CN202110461198A CN113393879A CN 113393879 A CN113393879 A CN 113393879A CN 202110461198 A CN202110461198 A CN 202110461198A CN 113393879 A CN113393879 A CN 113393879A
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张和
康旺
赵巍胜
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Beihang University
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Abstract

The invention provides a nonvolatile memory and SRAM mixed storage integral data fast loading structure, comprising: an SRAM compute array and an MRAM array integrally packaged with the SRAM array; the MRAM array is used for storing weight data of the neural network; the SRAM array is used for realizing multiplication and addition calculation between input data and the weight value of the currently stored neural network and outputting a calculation result of the analog quantity; the SRAM array and the corresponding MRAM array are connected with the same joint address decoder; the write driving circuit of the SRAM array is directly connected with the read driving circuit of the corresponding MRAM array, so that data loading from the nonvolatile memory to the SRAM can be realized in a very short time, and the power consumption and the expense are low.

Description

Nonvolatile memory and SRAM mixed storage integrated data fast loading structure
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a nonvolatile memory and SRAM mixed storage integrated data fast loading structure.
Background
In the artificial intelligence era, the von neumann computing architecture with a processor and a memory chip separated from each other is high in power consumption and not suitable for the development trend of miniaturization due to frequent data transmission between the memory and the processor, and in order to solve the device size shrinking challenge and the bottleneck of the von neumann computing architecture, the memory computing (or memory computing integration, memory computing and the like) technology is widely concerned by people.
One important branch of the current mainstream technology is the cost-effective implementation using SRAM as the storage medium, mainly due to its mature CMOS process characteristics. However, in the SRAM-based integrated storage structure, the capacity of the SRAM and its non-volatility are limited, and the weights of most network structures cannot be placed in the array at one time, and the weight parameters stored in the array need to be loaded from the outside frequently. When the energy efficiency ratio is pushed to a higher order, the data loading power consumption brings about no small overhead.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a fast data loading structure with a nonvolatile memory and SRAM mixed storage body, which can at least partially solve the problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, a nonvolatile memory and SRAM mixed integral data fast loading structure is provided, including: an SRAM compute array and an MRAM array integrally packaged with the SRAM array;
the MRAM array is used for storing weight data of the neural network;
the SRAM array is used for realizing multiplication and addition calculation between input data and the weight value of the currently stored neural network and outputting a calculation result of the analog quantity;
the SRAM array and the corresponding MRAM array are connected with the same joint address decoder; the write driving circuit of the SRAM array is directly connected with the read driving circuit of the corresponding MRAM array.
Further, the joint address decoder includes: j-K decoder, i-N decoder and K N-path distributors;
the input end of the j-K decoder is used for receiving MRAM addresses in the loading block, and the output end of the j-K decoder is connected with K N-way distributors; the input end of the i-N decoder is used for receiving an SRAM address to be loaded, and the output end of the i-N decoder is connected with K N distributors; the output ends of the K N-path distributors are used as first output ends of the joint address decoder, are connected with the MRAM array, and output NxK output signals which are used as row selection signals of the MRAM array; and the output end of the i-N decoder is used as a second output end of the joint address decoder, is connected with the SRAM array, and outputs N output signals as row selection signals of the SRAM array.
Further, the fast loading structure of the nonvolatile memory and SRAM mixed storage integral data further comprises: the SRAM calculation array comprises an input conversion circuit used for converting a digital input signal into an analog signal, and an output conversion circuit used for converting a calculation result output by the SRAM calculation array into a digital signal;
the output end of the input conversion circuit is connected with the SRAM calculation array, and the output end of the SRAM calculation array is connected with the input end of the output conversion circuit.
Further, the input conversion circuit comprises at least one of a digital-to-analog converter, a pulse width modulator, a counter and a pulse truncation circuit.
Further, the output conversion circuit adopts an integrating counting type circuit or an ADC.
Further, the ADC is a flash ADC or sar ADC.
Further, the size of the MRAM array is greater than or equal to the size of the SRAM calculation array.
Further, the SRAM cells in the SRAM array are 8TSRAM structures.
Further, the SRAM cells in the SRAM array are in a 6TSRAM structure.
Further, the SRAM cells in the SRAM array are bulk charge transfer based cells.
The invention provides a nonvolatile memory and SRAM mixed storage integral data fast loading structure, which comprises: an SRAM compute array and an MRAM array integrally packaged with the SRAM array; the MRAM array is used for storing weight data of the neural network; the SRAM array is used for realizing multiplication and addition calculation between input data and the weight value of the currently stored neural network and outputting a calculation result of the analog quantity; the SRAM array and the corresponding MRAM array are connected with the same joint address decoder; the write driving circuit of the SRAM array is directly connected with the read driving circuit of the corresponding MRAM array. The MRAM array and the SRAM array are integrally packaged, the SRAM array and the corresponding MRAM array are connected with the same joint address decoder, and the writing drive circuit of the SRAM array is directly connected with the reading drive circuit of the corresponding MRAM array, so that data loading from a nonvolatile memory to the SRAM can be realized in a very short time, and the power consumption expense is reduced to the minimum due to no arrangement of an intermediate register and the like.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. In the drawings:
FIG. 1 is a conventional memory-integrated core architecture of the prior art;
FIG. 2 illustrates an existing SRAM compute array interacting with an external storage medium;
FIG. 3 illustrates a hybrid nonvolatile memory and SRAM structure in an embodiment of the present invention;
FIG. 4 shows a specific circuit connection manner of a nonvolatile memory and SRAM mixed integral data fast loading structure in an embodiment of the present invention;
FIG. 5 shows the working principle of the hybrid nonvolatile memory and SRAM bank data fast loading structure in the embodiment of the present invention;
FIG. 6 shows a circuit of an SRAM cell in an embodiment of the present invention;
FIG. 7 shows a circuit diagram of a charge transfer based storage unit in an embodiment of the invention;
fig. 8 shows a circuit diagram of a pulse chopping circuit in an embodiment of the invention;
fig. 9 shows a circuit diagram of an integrating-counting type circuit in an embodiment of the present invention.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The detailed features and advantages of the present invention are described in detail in the following embodiments, which are sufficient for anyone skilled in the art to understand the technical content of the present invention and to implement the present invention, and the related objects and advantages of the present invention can be easily understood by anyone skilled in the art from the disclosure, the claims and the drawings of the present specification. The following examples further illustrate aspects of the present invention in detail, but are not intended to limit the scope of the invention in any way.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
FIG. 1 is a conventional memory-integrated core architecture of the prior art; as shown in fig. 1, the SRAM is mainly used as a medium for data temporary storage, and multiplication is implemented by other peripheral transistors and externally input data. The external digital input signal needs to be converted into an analog signal value through the DAC, and the analog signal value is used as the input of the SRAM calculation array. The computing array is composed of a plurality of SRAM computing units. The array realizes multiplication and addition calculation and outputs the calculation result of the analog quantity. And finally, the ADC analog-to-digital conversion device converts the analog quantity into a digital signal as an output result.
FIG. 2 illustrates an existing SRAM compute array interacting with an external storage medium; as shown in fig. 2, the SRAM compute array typically stores weights for the neural network. However, due to the limitation of the size of the array and the limitation of the capacity of the SRAM, the weight of most network structures cannot be put into the array at one time. It is necessary to repeatedly load the network parameters of other parts from other storage media in the calculation process. The main data storage structure of the current SRAM bank is the connection to the off-chip large memory array using the SRAM compute array. The weight of the network is mainly stored in a large storage array outside the chip, and is loaded into the SRAM calculation array in batches to participate in calculation according to calculation requirements.
However, due to the fact that the transmission data volume is large, in the actual calculation process, the transmission power consumption ratio is gradually improved along with the improvement of the calculation efficiency. In order to alleviate the problem, the application provides a unit structure of hybrid packaging of the SRAM and the nonvolatile memory, which is characterized in that an SRAM calculation array and a nonvolatile memory array with larger capacity are packaged together, a common access address is used for controlling a decoder, and data loading from the nonvolatile memory to the SRAM can be realized in a very short time. Meanwhile, because no intermediate register and the like are arranged, the power consumption overhead is reduced to the minimum. FIG. 3 shows a hybrid structure of a nonvolatile memory and an SRAM in an embodiment of the invention.
As shown in fig. 3, for a storage-integration structure, a plurality of SRAM calculation arrays may be provided due to calculation requirements, and a corresponding MRAM array is integrated in a chip for each SRAM calculation array, and since the MRAM array needs to store weight data corresponding to a plurality of calculation cycles in the SRAM calculation array, such as weight data for a plurality of layers of a neural network, and the SRAM calculation array only needs to perform one or a part of the layer operations at a time, the scale of the MRAM array is greater than or equal to that of the SRAM calculation array, and the SRAM calculation array and the corresponding MRAM array are connected to the same joint address decoder for joint decoding.
Fig. 4 shows a specific circuit connection manner of a nonvolatile memory and SRAM mixed integral data fast loading structure in an embodiment of the present invention, and as shown in fig. 4, the nonvolatile memory and SRAM mixed integral data fast loading structure includes: an SRAM compute array and an MRAM array integrally packaged with the SRAM array;
the MRAM array is used for storing weight data of the neural network;
the SRAM array is used for realizing multiplication and addition calculation between input data and the weight value of the currently stored neural network and outputting a calculation result of the analog quantity;
the SRAM array and the corresponding MRAM array are connected with the same joint address decoder; the write driving circuit of the SRAM array is directly connected with the read driving circuit of the corresponding MRAM array.
Each column in the SRAM array corresponds to one write-in driving circuit, or multiple columns correspond to one write-in driving circuit, the number of the write-in driving circuits of the SRAM array is the same as that of the read-out driving circuits of the corresponding MRAM array, and the write-in driving circuits are connected in a one-to-one mode.
The joint address decoder generally has two sets of inputs, one set of input is the address to be loaded by the SRAM, the other set of input is the address of the MRAM, and the address output is connected with the SRAM and the DRAM.
In particular, there are complex read and write drivers in the array, and multi-bit to multi-bit loading operations from the MRAM array to the SRAM array can be achieved. The read drive of the MRAM is directly connected with the write drive of the SRAM, no redundant buffer is provided, and the SRAM is written while the read of the MRAM is finished. The SRAM array and the MRAM array share a hybrid row decoder, and an MRAM block composed of a plurality of rows is mapped to a certain row of the SRAM. That is, address 1 of the row decoder selects a certain row of the SRAM and a certain block row of the MRAM. A row in the MRAM block is then selected by address 2 as the load data. After the SRAM row address is traversed, the rapid data loading of the MRAM selected data to the SRAM can be realized.
By adopting the technical scheme, the hybrid packaging of the nonvolatile memory and the SRAM realizes the high-speed low-power-consumption data loading of data from the large-capacity nonvolatile memory to the SRAM calculation array.
In an alternative embodiment, referring to fig. 5, the joint address decoder comprises: j-K decoder, i-N decoder and K N-path distributors;
the input end of the j-K decoder is used for receiving MRAM addresses in the loading block, and the output end of the j-K decoder is connected with K N-way distributors; the input end of the i-N decoder is used for receiving an SRAM address to be loaded, and the output end of the i-N decoder is connected with K N distributors; the output ends of the K N-path distributors are used as first output ends of the joint address decoder, are connected with the MRAM array, and output NxK output signals which are used as row selection signals of the MRAM array; and the output end of the i-N decoder is used as a second output end of the joint address decoder, is connected with the SRAM array, and outputs N output signals as row selection signals of the SRAM array.
Specifically, with continued reference to FIG. 4, assume that address one i lines, address 2j lines. The joint address decoder comprises an i-N decoder and a j-K decoder, and N and K outputs are respectively generated. The N outputs are directly sent to the SRAM array as row selection signals. N, K signals are jointly sent to K N-way distributors, and N multiplied by K output signals are output in total and used as row selection signals of the MRAm array.
By adopting the technical scheme, the MRAM array with the capacity being several times that of the SRAM is added beside the SRAM, or the MRAM array is decomposed into a plurality of sub-arrays to be roughly fused with the SRAM array. The memory access interfaces of the two arrays are linked together, and one-time loading operation is realized within 1-2 clocks.
In an alternative embodiment, the nonvolatile memory and SRAM mixed integral data fast loading structure further comprises: the SRAM calculation array comprises an input conversion circuit used for converting a digital input signal into an analog signal, and an output conversion circuit used for converting a calculation result output by the SRAM calculation array into a digital signal;
the output end of the input conversion circuit is connected with the SRAM calculation array, and the output end of the SRAM calculation array is connected with the input end of the output conversion circuit.
By adopting the technical scheme, the storage and calculation are integrated, and the bottleneck of the Von Neumann architecture is solved.
In an alternative embodiment, in the integrated data fast loading architecture with nonvolatile memory mixed with SRAM, the input conversion circuit includes at least one of a digital-to-analog converter, a pulse width modulator, a counter, and a pulse truncation circuit.
By adopting the technical scheme, the conversion precision of the input data can be improved, and the integration of high-bit and high-precision storage and calculation is realized.
Referring to fig. 8, the pulse truncation circuit may be implemented by using an and gate, or the pulse truncation circuit may be implemented by using an and gate and two inverters, or implemented by using an and gate, a nor gate and 2 inverters. By adopting the pulse truncation circuit, the driving capability and the precision are improved.
In an alternative embodiment, the output conversion circuit employs an integrating-counting type circuit (circuit configuration see fig. 9) or ADC.
By adopting the technical scheme, the conversion precision of the output data can be improved, and the integration of high-bit high-precision storage and calculation is realized.
The circuit structure of the integrating and counting circuit shown in fig. 9 includes: buffer capacitor C1A first NMOS transistor N1NOR gate, second NMOS transistor N2And a third NOMS transistor N3Fourth NOMS transistor N4Capacitor C2And a plurality of inverters IV 0-IV 2.
The working process is shown as a dotted arrow, firstly a SET signal is given, for C1Charging to VrefTo C2Discharge to GND. The initialization of the circuit is completed. The SET signal is then deasserted.
After SET signal is removed, N2Open, electricity coming from CBL lineCharge injection into C1While C is1Upper charge transfer to C2The above. Here, N1Gate bias voltage VbIs to limit the pair C2The charging speed is maintained at a stable flow rate, so that C is not caused by sudden large charge accumulation on the CBL2The charging voltage fluctuates unreasonably. When C is present2The upper charge is accumulated until the voltage value is larger than VrefThrough a feedback circuit, N2Off, N4Open, start to pair C2The discharge is started. At this time, the charge inputted on the CBL will be temporarily stored in C1And (4) the following steps.
The loop delay formed by the inverter and the comparator ensures that the voltage at C2The voltage value drops to VrefAfter N4Will not shut down immediately but will turn on C during a delay2The discharge is sufficient.
After a delay, due to C2Voltage less than Vref，N4Reclosing, N2Open and start the next cycle of charge and discharge.
Through adopting above-mentioned technical scheme, the unit electric charge volume of discharging at every turn is more stable, has promoted the precision, reduces the error.
In an alternative embodiment, the ADC is a flash ADC or sar ADC.
In an alternative embodiment, the SRAM cell in the SRAM array is an 8TSRAM structure, see fig. 6, a typical 8TSRAM storage unit, where 6TSRAM stores 1bit weight data and controls the on/off of the right N2. The external input data acts on the grid of the N1, and the magnitude of the discharge current of the N1 is controlled through the input level amplitude. It can be seen from the figure that N2 and N1 together implement a multiplication operation of 6t sram data and external input, and the multiplication result is an amount of charge loss on BLC.
In another alternative embodiment, the SRAM cells in the SRAM array are in a 6t SRAM configuration.
In yet another alternative embodiment, the SRAM cells in the SRAM array are integral cells based on charge transfer, and the circuit structure shown in fig. 7 includes: 6T-SRAM, first PMOS transistor P1A second PMOS crystalBody pipe P2A third PMOS transistor P3Capacitor C0A first NMOS transistor N1. BLN is the complement of BL, the complementary bit line. 6TSRAM cell P1Only when Q is 0, P1And (4) opening. WLC and WLCN are complementary input signals. WLC goes low first then high when the input is 1, and WLCN is its opposite. In this process C0Will first pass through P1P2Charging, followed by P3Placing charge on BLC by subtracting WLCN voltage from charging level and subtracting P3The threshold voltage of (2). The above process is a single operation process, and the process can be repeated by controlling the WLC and the WCLN to realize the calculation of multiple bits. Furthermore, N1As a protection circuit for precision, eliminating P1P caused by repeated change of WLCN in OFF state3A slight charge leakage to the BLC.
By adopting the technical scheme, the precision of the storage and calculation integrated structure is high, the power consumption is low, and multi-bit input can be realized in a multi-pulse input mode.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but may be embodied or carried out by various modifications, equivalents and changes without departing from the spirit and scope of the invention.

Claims (10)

1. A fast loading structure of integrated data of nonvolatile memory and SRAM mixed storage is characterized by comprising: an SRAM compute array and an MRAM array integrally packaged with the SRAM array;
the MRAM array is used for storing weight data of the neural network;
the SRAM array is used for realizing multiplication and addition calculation between input data and the weight value of the currently stored neural network and outputting a calculation result of the analog quantity;
the SRAM array and the corresponding MRAM array are connected with the same joint address decoder; the write driving circuit of the SRAM array is directly connected with the read driving circuit of the corresponding MRAM array.
2. The non-volatile memory and SRAM hybrid memory bank data fastload architecture of claim 1, wherein the joint address decoder comprises: j-K decoder, i-N decoder and K N-path distributors;
the input end of the j-K decoder is used for receiving MRAM addresses in the loading block, and the output end of the j-K decoder is connected with K N-way distributors; the input end of the i-N decoder is used for receiving an SRAM address to be loaded, and the output end of the i-N decoder is connected with K N distributors; the output ends of the K N-path distributors are used as first output ends of the joint address decoder, are connected with the MRAM array, and output NxK output signals which are used as row selection signals of the MRAM array; and the output end of the i-N decoder is used as a second output end of the joint address decoder, is connected with the SRAM array, and outputs N output signals as row selection signals of the SRAM array.
3. The non-volatile memory and SRAM hybrid compute unified data load architecture of claim 1, further comprising: the SRAM calculation array comprises an input conversion circuit used for converting a digital input signal into an analog signal, and an output conversion circuit used for converting a calculation result output by the SRAM calculation array into a digital signal;
the output end of the input conversion circuit is connected with the SRAM calculation array, and the output end of the SRAM calculation array is connected with the input end of the output conversion circuit.
4. The non-volatile memory and SRAM hybrid compute unified data load architecture of claim 3, wherein said input conversion circuitry comprises at least one of digital-to-analog converter, pulse width modulator, counter, pulse truncation circuit.
5. The non-volatile memory and SRAM mixed bank data fastload architecture of claim 3, wherein said output conversion circuit employs an integrating-counting type circuit or ADC.
6. The non-volatile memory and SRAM mixed bank data fastload architecture of claim 5, wherein said ADC is a flash ADC or an sar ADC.
7. The non-volatile memory and SRAM hybrid memory bank data fastload architecture of any one of claims 1 to 6, wherein the size of said MRAM array is equal to or larger than the size of said SRAM compute array.
8. The non-volatile memory and SRAM hybrid memory bank data fast load architecture of any one of claims 1-6, wherein SRAM cells in said SRAM array are 8TSRAM architectures.
9. The non-volatile memory and SRAM hybrid memory bank data fast load architecture of any one of claims 1-6, wherein SRAM cells in said SRAM array are 6TSRAM architectures.
10. The hybrid nonvolatile memory and SRAM bank integral data fast loading architecture of any one of claims 1 to 6, wherein the SRAM cells in the SRAM array are integral charge transfer based elements.
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