CN113391903A

CN113391903A - Method and device for establishing schedulability model, electronic equipment and storage medium

Info

Publication number: CN113391903A
Application number: CN202110694629.0A
Authority: CN
Inventors: 张翔宇; 陈永录; 王密
Original assignee: Industrial and Commercial Bank of China Ltd ICBC
Current assignee: Industrial and Commercial Bank of China Ltd ICBC
Priority date: 2021-06-22
Filing date: 2021-06-22
Publication date: 2021-09-14

Abstract

The embodiment of the disclosure provides a method and a device for establishing a schedulability model, electronic equipment and a storage medium. Can be applied to the technical field of computers and financial services. The method comprises the following steps: determining a mapping relationship between model elements in the architectural analysis and design language model and system elements in the safety critical operating system; generating a mapping rule table according to the mapping relation, wherein the mapping rule table comprises a plurality of mapping relations; determining target model elements required for establishing a schedulability model from model elements of an architecture analysis and design language model recorded in a mapping rule table; determining schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element; and generating a schedulability model by utilizing a preset modeling method, a mapping rule table and schedulability attribute configuration information.

Description

Method and device for establishing schedulability model, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies and financial services technologies, and in particular, to a method for establishing a schedulability model, a schedulability model generation apparatus, an electronic device, a computer-readable storage medium, and a computer program product.

Background

In the fields of aerospace, industrial control, public transportation, financial service and the like, strict requirements are imposed on the schedulability, reliability and the like of the system. If the system functions are in error, large losses are caused to personnel and property, and the system is generally called a safety-critical system, and software in the safety-critical system is called safety-critical software. The good software quality can ensure the normal operation of the safety critical system and keep a low failure rate. For safety critical operating systems, due to the particularities of their operating environment, if problems occur, they can cause undue loss of personnel and property.

In implementing the disclosed concept, the inventors found that there are at least the following problems in the related art: unified Modeling Language (UML) is difficult to describe key characteristics such as performance and schedulability of a system.

Disclosure of Invention

In view of this, the disclosed embodiments provide a schedulability model establishing method, a schedulability model generating device, an electronic device, a computer-readable storage medium, and a computer program product.

One aspect of the embodiments of the present disclosure provides a method for establishing a schedulability model, including:

determining a mapping relationship between model elements in the architectural analysis and design language model and system elements in the safety critical operating system;

generating a mapping rule table according to the mapping relationship, wherein the mapping rule table comprises a plurality of mapping relationships;

determining target model elements required for building a schedulability model from the model elements of the architectural analysis and design language model recorded in the mapping rule table;

determining schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element;

and generating the schedulability model by utilizing a preset modeling method, the mapping rule table and the schedulability attribute configuration information.

According to an embodiment of the present disclosure, the schedulability attribute configuration information at least includes one of the following information: scheduling attribute information, dispatch type information, execution time information, processor information, and memory information.

According to an embodiment of the present disclosure, the mapping relationship in the mapping rule table includes a partition mapping relationship, a module mapping relationship, a port mapping relationship, a thread mapping relationship, a memory mapping relationship, and a mode mapping relationship;

wherein the generating the schedulability model by using the preset modeling method, the mapping rule table, and the schedulability attribute configuration information includes:

generating a software architecture model by using the preset modeling method, the thread mapping relationship, the port mapping relationship, the execution time information, the dispatch type information and the schedulable attribute information;

generating a data component model by using the preset modeling method, the mode mapping relation and the port mapping relation;

generating an execution platform component model by using the preset modeling method, the module mapping relation, the partition mapping relation, the memory mapping relation, the storage information and the processor information;

and generating the schedulability model according to the software architecture model, the data component model and the execution platform component model.

According to an embodiment of the present disclosure, the method for establishing the schedulability model further includes:

obtaining a verification analysis tool, wherein the verification analysis tool has a function of analyzing schedulability of the schedulability model;

analyzing the schedulability of the schedulability model by using the verification analysis tool to obtain a schedulability analysis result;

and displaying the schedulability analysis result.

According to an embodiment of the present disclosure, the system element at least includes one of the following elements: a system partition element, a system module element, a system port element, a system thread element, a system memory element, and a system mode element.

Another aspect of the embodiments of the present disclosure provides a schedulability model generating device, including:

the mapping module is used for determining the mapping relation between model elements in the architecture analysis and design language model and system elements in the safety key operating system;

a first generating module, configured to generate a mapping rule table according to the mapping relationship, where the mapping rule table includes a plurality of mapping relationships;

a first determining module, configured to determine, from the model elements of the architectural analysis and design language model recorded in the mapping rule table, target model elements required for building a schedulability model;

a second determining module, configured to determine schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element;

and the second generation module is used for generating the schedulability model by utilizing a preset modeling method, the mapping rule table and the schedulability attribute configuration information.

Another aspect of an embodiment of the present disclosure provides an electronic device including: one or more processors; memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method as described above.

Another aspect of embodiments of the present disclosure provides a computer-readable storage medium storing computer-executable instructions for implementing the method as described above when executed.

Another aspect of an embodiment of the present disclosure provides a computer program product comprising computer executable instructions for implementing the method as described above when executed.

According to the embodiment of the disclosure, by determining the mapping relationship between the model elements in the architecture analysis and design language model and the system elements in the safety key operating system, generating the mapping rule table according to the mapping relationship, determining the schedulability attribute configuration information according to the model elements, and generating the schedulability model according to the preset modeling method, the mapping rule table and the schedulability attribute configuration information, because the architecture analysis and the design language support the analysis of the performance and the schedulability of the operating system, the safety key operating system based on the architecture analysis and the design language model can realize the description of the key characteristics such as the schedulability, the technical problem that the unified modeling language is difficult to describe the key characteristics such as the performance and the schedulability of the system is at least partially overcome, and further the description of the key characteristics such as the schedulability is realized, and further, the technical effect that the safety key operating system can stably run is guaranteed.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates a system architecture diagram for a safety critical operating system, in accordance with an embodiment of the present disclosure;

FIG. 2 schematically illustrates an exemplary system architecture of a method of building an application schedulability model, according to an embodiment of the present disclosure;

FIG. 3 schematically illustrates a flow chart of a method of building a schedulability model according to an embodiment of the present disclosure;

FIG. 4 schematically illustrates a flow diagram for generating a schedulability model using a preset modeling method, a mapping rule table, and schedulability attribute configuration information, according to an embodiment of the present disclosure;

FIG. 5 schematically illustrates a structural diagram of a software architecture model according to an embodiment of the present disclosure;

FIG. 6 schematically illustrates a structural schematic of a schedulability model according to an embodiment of the present disclosure;

FIG. 7 schematically illustrates a block diagram of a schedulability model generation apparatus according to an embodiment of the present disclosure; and

fig. 8 schematically shows a block diagram of an electronic device implementing a method of building a schedulability model according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B and C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a convention analogous to "A, B or at least one of C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B or C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

FIG. 1 schematically illustrates a system architecture diagram of a safety critical operating system, in accordance with an embodiment of the present disclosure.

Safety critical systems may relate to various directions and domains, and thus have a wide variety of types of safety critical systems. For example, for the case where the safety critical operating system is based on the ARINC653 standard, the system architecture of the safety critical operating system is as shown in fig. 1. The security critical operating system may include a target machine operating environment and a host machine operating environment. The target machine runtime environment may include an application Layer, an operating system kernel Layer, a Hardware Abstraction Layer (HAL), and a Board Support Package (BSP). The host operating environment may include other plug-ins such as an IDE integrated development platform, an editor and help, where the other plug-ins such as the editor and help may include multitask and multi-target debugging, Eclipse CDT plug-ins, and the like, for example, debugging of a visualization configuration, a task time planning table, a space planning table, and the like. Meanwhile, the host machine and the target machine carry out setting debugging through GDB (GNU symbololic Debuger) arranged on the host machine and the target machine.

Safety-critical systems are widely introduced into relevant important areas, which place high demands on the safety of the system. The safety critical system often fails due to the problems of complex task, large workload and the like. This is mainly because the safety-critical system is closely related to the user, and in addition, due to the quality of software development, the level of managers being uneven, the influence of physical environment, etc., it is more likely to have a fault or crash, which becomes a key and difficult point of the research of the safety-critical system.

The software in a safety critical system is called safety critical software, e.g. AgOS software. The good software quality can ensure the normal operation of the safety critical system and keep a low failure rate. The safety-critical operating system is essential core software in safety-critical fields such as aerospace electronics, military and finance due to high safety, high reliability and schedulability.

AgOS is used as safety key software, and a partition management mechanism meets ARINC653 standard, wherein a user uses a configuration file to realize the configuration of space and time partitions; maintaining all partitions by using a health monitoring mechanism according to ARINC653 standard, wherein a health monitoring module is responsible for monitoring a hardware module, an application program and an operating system; on the basis of the original board-level support package, further packaging is carried out to form a hardware abstraction layer interface for hardware, and the operating system is guaranteed to be unrelated to the concrete hardware implementation; the task scheduling table is used as the core of the task scheduling of the operating system, the task scheduling determined by the operating system is guaranteed, and the user plans the execution time sequence of the tasks in advance according to the execution period and the worst execution time of each task and the deployment of each function completion time of the system.

Although the traditional software development method can be used to achieve the schedulability index of a certain functional module, after the system is integrated, the schedulability requirement of the whole system can not be met. Therefore, a Model Driven Architecture (MDA) development method is proposed. The main idea of MDA is that all design and implementation can be guided by construction using models. The MDA development approach relies on building a correlation model to guide the design, analysis, construction, deployment, and maintenance of safety critical systems. Before the system is implemented, an MDA method is used for modeling, relevant non-functional attribute descriptions are added to the model to indicate indexes capable of verifying non-functionality, and verification by using the model can help designers to find potential errors, modify and improve original design and perfect the system architecture. Through the repeated interaction process of modeling, verification and design, the system development period is shortened, and unnecessary errors are avoided.

Using MDA to analyze a safety critical system, first the designer needs to know the respective modeling languages and choose from them the language that is most suitable for the current project. The model-driven development method MDD can analyze and verify the system at an early stage, ensure the correctness of system development and effectively reduce unnecessary time and cost consumption. Unified Modeling Language (UML) is its primary representative, but UML focuses on describing the software architecture of the system and is more difficult to describe the performance and key characteristics of the system, such as real-time, schedulability, and security of the hardware.

In implementing The disclosed concept, it is found that The Architecture Analysis and Design Language (AADL) is an architectural modeling Language based on The idea of MDA. The architectural analysis and design language is both a graphical language and a feature language. The method can successfully manufacture an accurate model of a complex real-time system architecture, and is suitable for performing structural design and test on the whole system for the operating system with critical performance.

In view of this, embodiments of the present disclosure provide a schedulability model establishing method, a schedulability model generating device, an electronic device, a computer-readable storage medium, and a computer program product. The method for establishing the schedulability model comprises the steps of determining a mapping relation between model elements in the architecture analysis and design language model and system elements in the safety key operating system; generating a mapping rule table according to the mapping relation, wherein the mapping rule table comprises a plurality of mapping relations; determining target model elements required for establishing a schedulability model from model elements of an architecture analysis and design language model recorded in a mapping rule table; determining schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element; and generating a schedulability model by utilizing a preset modeling method, a mapping rule table and schedulability attribute configuration information.

It should be noted that the method and the device for establishing the schedulability model provided by the disclosure can be used in the financial field. For example, the schedulability model may be a bank, or may be used in any field other than the financial field, for example, the computer technology, the aerospace, the industrial control, and other technical fields, and therefore, the application fields of the schedulability model establishing method and the device provided by the present disclosure are not limited.

Fig. 2 schematically illustrates an exemplary system architecture 200 to which a method of building schedulability models may be applied, according to an embodiment of the present disclosure. It should be noted that fig. 2 is only an example of a system architecture to which the embodiments of the present disclosure may be applied to help those skilled in the art understand the technical content of the present disclosure, and does not mean that the embodiments of the present disclosure may not be applied to other devices, systems, environments or scenarios.

As shown in fig. 2, a system architecture 200 according to this embodiment may include

terminal devices

202, 203, a network 204, and a server 205. The network 204 is used to provide a medium for communication links between the

terminal devices

202, 203 and the server 205. Network 204 may include various connection types, such as wired and/or wireless communication links, and so forth.

A user may use the

terminal devices

202, 203 to interact with the server 205 over the network 204 to receive or send messages or the like. The

terminal devices

202, 203 may have installed thereon various communication client applications, such as a modeling-type application, a web browser application, a search-type application, an instant messaging tool, etc. (by way of example only).

The

terminal devices

202, 203 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, desktop computers, and the like.

The server 205 may be a server providing various services, such as a background management server (for example only) providing support for websites browsed by users using the

terminal devices

202, 203. The background management server may analyze and perform other processing on the received data such as the user request, and feed back a processing result (e.g., a webpage, information, or data obtained or generated according to the user request) to the terminal device.

It should be noted that the method for establishing the schedulability model provided by the embodiment of the present disclosure may be generally executed by the

terminal device

202, or 203, or may also be executed by another terminal device different from the

terminal device

202, or 203. Accordingly, the schedulability model generation apparatus provided by the embodiment of the present disclosure may also be disposed in the

terminal device

202, or 203, or in another terminal device different from the

terminal device

202, or 203. Alternatively, the method for establishing the schedulability model provided by the embodiment of the present disclosure may also be executed by the server 205. Accordingly, the schedulability model generation apparatus provided by the embodiments of the present disclosure may be generally disposed in the server 205. The method for establishing the schedulability model provided by the embodiments of the present disclosure may also be performed by a server or a server cluster different from the server 205 and capable of communicating with the

terminal devices

202, 203 and/or the server 205. Accordingly, the schedulability model generation apparatus provided by the embodiments of the present disclosure may also be disposed in a server or a server cluster different from the server 205 and capable of communicating with the

terminal devices

202, 203 and/or the server 205.

It should be understood that the number of terminal devices, networks, and servers in fig. 2 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

Fig. 3 schematically shows a flow chart of a method of establishing a schedulability model according to an embodiment of the present disclosure.

As shown in fig. 3, the method for establishing the schedulability model may include operations S301 to S305.

In operation S301, a mapping relationship between model elements in the architectural analysis and design language model and system elements in the safety critical operating system is determined.

In operation S302, a mapping rule table is generated according to the mapping relationship, where the mapping rule table includes a plurality of mapping relationships.

In operation S303, from the model elements of the architectural analysis and design language model recorded in the mapping rule table, target model elements required for building the schedulability model are determined.

Schedulability attribute configuration information for scheduling the safety critical operating system is determined from the target model element in operation S304.

In operation S305, a schedulability model is generated using a preset modeling method, a mapping rule table, and schedulability attribute configuration information.

According to an embodiment of the present disclosure, the system elements may include at least one of the following elements: a system partition element, a system module element, a system port element, a system thread element, a system memory element, and a system mode element.

According to an embodiment of the present disclosure, the model element may include at least one of the following elements: a processor element, a virtual processor element, a component process element, a component thread element, a time data port element, a component memory element, and an event data port element.

According to an embodiment of the present disclosure, the schedulability property configuration information may include at least one of the following information: scheduling attribute information, dispatch type information, execution time information, processor information, and memory information.

According to an embodiment of the present disclosure, the tool used by the preset modeling method may include one of: osate tool, Power Designer tool, JUDE-Community tool, or BOUml tool.

According to embodiments of the present disclosure, the target model elements may include processor elements, virtual processor elements, component process elements, component thread elements, and the like.

According to embodiments of the present disclosure, the architectural analysis and design language is capable of modeling a safety critical operating system and providing modular functionality. The system module elements in the safety key operating system can be described by Processor information (Processor) in the architecture analysis and design language model, the system partition elements are described by virtual Processor elements (Process), the Process is equivalent to the system partition elements in the safety key operating system, different threads are segmented, and the threads belonging to different processes are protected; the component process element can be emulated using a component Thread element (Thread) component, a Thread representing a component that can execute concurrently, which can emulate the function of a process in an actual system.

Communication functions within the security critical operating system partition may also be described using an architectural analysis and design language. System port elements in a security critical operating system may be emulated using a temporal Data port element (Data ports) component; system Data port elements may be mapped using Data port elements (Data ports) for emulation; communications between system partition elements in a security critical operating system may also be mapped using Event data ports (Event data ports).

According to an embodiment of the present disclosure, schedulability attribute configuration information for scheduling a safety critical operating system is determined from a target model element. Adding schedulable attribute information for the component thread element by using properties keywords of the system thread element; defining dispatch type information of the component thread element by using a scheduling protocol attribute of the system thread element; defining a Period value of the Execution Time information using a Time Period attribute of the system thread element, and specifying an Execution Time in the Execution Time information using a computer _ Execution _ Time attribute of the system thread element; binding the component thread element with the Processor element using the Reference _ Processor attribute of the system module element; SEI using system module elements: : the mipscope attribute specifies the processor performance of the processor information; the Scheduling _ Protocol attribute of the use system partition element specifies the processor Scheduling algorithm for the processor information.

According to the embodiment of the disclosure, a schedulability model is generated by using a preset modeling method, a mapping rule table and schedulability attribute configuration information.

According to the embodiment of the disclosure, the mapping relationships in the mapping rule table include a partition mapping relationship, a module mapping relationship, a port mapping relationship, a thread mapping relationship, a memory mapping relationship, and a mode mapping relationship.

According to the embodiment of the disclosure, the mapping rule table is generated according to the mapping relation between the model element in the architecture analysis and design language model and the system element in the safety-critical operating system, wherein the mapping relation is shown in table 1.

TABLE 1

Fig. 4 schematically illustrates a flowchart for generating a schedulability model using a preset modeling method, a mapping rule table and schedulability attribute configuration information according to an embodiment of the present disclosure.

FIG. 5 schematically shows a structural diagram of a software architecture model according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 4, generating a schedulability model using a preset modeling method, a mapping rule table, and schedulability attribute configuration information may include operations S401 to S404.

In operation S401, a software architecture model is generated using a preset modeling method, a thread mapping relationship, a port mapping relationship, execution time information, dispatch type information, and schedulable attribute information.

In operation S402, a data component model is generated using a preset modeling method, a mode mapping relationship, and a port mapping relationship.

In operation S403, an execution platform component model is generated using a preset modeling method, a module mapping relationship, a partition mapping relationship, a memory mapping relationship, storage information, and processor information.

In operation S404, a schedulability model is generated according to the software architecture model, the data component model, and the execution platform component model.

According to the embodiment of the disclosure, a software architecture model is generated by using a preset modeling method, a thread mapping relationship, a port mapping relationship, execution time information, dispatch type information and schedulable attribute information, and is shown in fig. 5.

Fig. 5 includes a component thread element and a data port element, where in the mapping relationship, the threads of the component thread element include the following three threads: thread thr1, thread thr2, and thread thr3, the data port elements mainly include dataout of thread thr1, datain of thread thr2, and thread thr 3. And defining the element of the component thread according to the thread mapping relation. May include attributes such as execution time information, schedulable attribute information, footprint size, and power consumption. Wherein a thread in a component thread element may represent an active object. Threads can repeatedly transmit at regular intervals as specified by a time Period attribute (referred to as cycle based scheduling).

The software architecture model of the security critical operating system of FIG. 5 includes three processes, process A (i.e., PartA _ pro), process B (i.e., PartB _ pro), and process C (i.e., PartC _ pro). With each process thread thr1, thread thr2, and thread thr 3. The threads in the three processes all have communication, and the process B and the process C also have communication relationship, for example, the dataout of thr1 of the process B has communication relationship with the datain of thr1 of the process C.

According to the embodiment of the disclosure, a data component model is generated by using a preset modeling method, a mode mapping relationship and a port mapping relationship, and the definition of the data component model is shown in table 2.

TABLE 2

In table 2, the description of the data port or the event data port in the port mapping relationship specifies the type of data to be communicated through the port, and the application source code can be accessed in the form of a port change or a queue. The definition of the Data component may take the form of any of a Data component type, a Data component implementation, and a Data component.

According to the embodiment of the disclosure, an execution platform component model is generated by using a preset modeling method, a module mapping relation, a partition mapping relation, a memory mapping relation, storage information and processor information.

According to an embodiment of the present disclosure, the processor information may include processor performance information and processor scheduling algorithm information of one processor and three virtual processors. The processor is a physical processor that schedules and executes software. When generating the execution platform component model, binding the component thread element with the Processor element by using the Reference _ Processor attribute of the system module element, wherein the binding can be realized by the architectural analysis and design language model attribute belonging to the default _ properties. SEI using system module elements: : the mipscope attribute specifies the processor performance of the processor information; the Scheduling _ Protocol attribute of the use system partition element specifies the processor Scheduling algorithm for the processor information.

According to an embodiment of the present disclosure, a specific definition of the processor in the processor information is shown in table 3. For example, the processor name may be powerpc, and the processor includes three virtual processors, which may be part1_ cpu, part2_ cpu, and part3_ cpu, respectively. The main role of a virtual processor is to divide the processor into multiple blocks, each block representing a virtual logical resource, and each resource carrying a guaranteed portion of the physical processor. Virtual processors represent component thread elements that schedule and process executable tasks that have the same cycles represented by the component thread elements using a round-robin scheduling protocol, such as a scheduling protocol in which a thread invokes a single task or the like. And respectively binding the three virtual processors with different scheduling protocols in the three processes. The memory information may be part of a system element in a security critical operating system to assume data interaction functions of the bus, CPU, and process. The memory information may be implemented as a cache within the processor or may represent a hardware memory device actually present via a bus connection. The memory can be modeled as a memory component or as a composite memory cell by placing the memory components in a memory component.

TABLE 3

According to an embodiment of the present disclosure, a schedulability model is generated from a software architecture model, a data component model, and an execution platform component model, the schedulability model being as shown in FIG. 6.

Fig. 6 schematically shows a structural schematic diagram of a schedulability model according to an embodiment of the present disclosure.

The model elements in fig. 6 may include: the system comprises a component memory element main _ mem, a processor element main _ cpu and three component process elements, wherein the three component process elements can be PartB _ pro, PartC _ pro and PartA _ pro respectively.

According to an embodiment of the present disclosure, attributes are first defined in a security critical operating system (AGOS), as shown in table 4.

TABLE 4

As shown in table 4 and fig. 6, the connection of PartB _ pro. data output to PartC _ pro. data input is defined using the system thread element properties key; the component process elements are bound to the Processor information using the Actual _ Processor _ Binding property, e.g., PartA _ pro may be bound to main _ cpu. part1_ cpu, PartB _ pro to main _ cpu. part2_ cpu, PartC _ pro to main _ cpu. part3_ cpu; the Actual _ Memory _ Binding attribute is used to bind the component process element with the component Memory element, PartA _ pro to main _ mem. part1_ mem, PartB _ pro to main _ mem. part2_ mem, and PartC _ pro to main _ mem. part3_ mem.

The schedulability model of FIG. 6 may include three memory subcomponents, three processes, and three virtual processor subcomponents. The three memory subassemblies are part1_ mem, part2_ mem and part3_ mem, the three processes are respectively process A (namely PartA _ pro), process B (namely PartB _ pro) and process C (namely PartC _ pro), and the three virtual processor subassemblies are part1_ cpu, part2_ cpu and part3_ cpu. The communication between the part1_ mem and the part1_ cpu is realized through the process A, the communication between the part2_ mem and the part2_ cpu is realized through the process B, the communication between the part3_ mem and the part3_ cpu is realized through the process C, threads in the three processes all have communication, and the process B and the process C also have communication relations, for example, the dataout of the thr1 of the process B and the datain of the thr1 of the process C have communication relations.

According to an embodiment of the present disclosure, the method for establishing the schedulability model may further include the following operations.

And acquiring a verification analysis tool, wherein the verification analysis tool has a function of analyzing schedulability of the schedulability model. And analyzing the schedulability of the schedulability model by using a verification analysis tool to obtain a schedulability analysis result. And displaying the result of the schedulability analysis.

Validation analysis tools may include Osate tools, Cheddar tools, aadl detectors, according to embodiments of the present disclosure. The disclosed embodiments are illustrated with the Osate tool.

According to the embodiment of the disclosure, the Osate tool comprises a verification tool which can be used as schedulability analysis and can support two scheduling algorithms of single-rate scheduling and earliest deadline first. The embodiment of the disclosure performs schedulability experimental analysis by using a schedulability model established by an architecture analysis and design language.

According to the embodiment of the disclosure, taking the change of the dispatch type of a certain task as an example, under the condition that the scheduling algorithm, the executable time, the period and the worst thread completion time are not changed, the original periodic attribute of the task dec _ process _ thr1 is changed into the aperiodic attribute, then the simulation test is performed again, the schedulability analysis result is obtained and displayed, and the schedulability analysis result is shown in table 5.

TABLE 5

As can be seen from table 5, after the original periodic attribute of the task dec _ process _ thr1 is changed to the aperiodic attribute, the maximum response time of the cycle of the task is reduced, and the maximum response time is reduced to 12 ms. Therefore, the periods of different tasks can be arranged according to the requirements so as to realize the optimal scheduling time and schedulability.

The embodiment of the disclosure performs univariate modification control on different time attributes of each system thread element under the condition that the processor power in the processor information is unchanged by using the schedulability model, and performs comparative analysis on the result after each modification. The method specifically comprises the following steps: and setting a scheduling algorithm, executable time, period, worst task completion time and dispatching protocol of the tasks, and analyzing schedulability according to five factors.

Fig. 7 schematically shows a block diagram of a schedulability model generation apparatus according to an embodiment of the present disclosure.

As shown in fig. 7, the schedulability model generation apparatus 700 includes a mapping module 710, a first generation module 720, a first determination module 730, a second determination module 740, and a second generation module 750.

A mapping module 710 for determining a mapping relationship between model elements in the architectural analysis and design language model and system elements in the safety critical operating system.

The first generating module 720 is configured to generate a mapping rule table according to the mapping relationship, where the mapping rule table includes a plurality of mapping relationships.

The first determining module 730 is configured to determine, from the model elements of the architectural analysis and design language model recorded in the mapping rule table, target model elements required for building the schedulability model.

A second determining module 740 for determining schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element.

The second generating module 750 is configured to generate a schedulability model using a preset modeling method, a mapping rule table, and the schedulability attribute configuration information.

According to an embodiment of the present disclosure, the schedulability property configuration information comprises at least one of the following information: scheduling attribute information, dispatch type information, execution time information, processor information, and memory information.

According to an embodiment of the present disclosure, the second generation module 750 may include a first generation unit, a second generation unit, a third generation unit, and a synthesis unit.

And the first generating unit is used for generating a software architecture model by utilizing a preset modeling method, a thread mapping relation, a port mapping relation, execution time information, dispatch type information and schedulable attribute information.

And the second generation unit is used for generating the data component model by utilizing a preset modeling method, a mode mapping relation and a port mapping relation.

And the third generation unit is used for generating the execution platform component model by utilizing a preset modeling method, a module mapping relation, a partition mapping relation, a memory mapping relation, storage information and processor information.

And the synthesis unit is used for generating a schedulability model according to the software architecture model, the data component model and the execution platform component model.

According to an embodiment of the present disclosure, the schedulability model generation apparatus 700 may further include an obtaining module, an analyzing module, and a presenting module.

And the acquisition module is used for acquiring a verification analysis tool, wherein the verification analysis tool has a function of analyzing the schedulability of the schedulability model.

And the analysis module is used for analyzing the schedulability of the schedulability model by utilizing the verification analysis tool to obtain a schedulability analysis result.

And the display module is used for displaying the schedulability analysis result.

According to an embodiment of the present disclosure, the system elements include at least one of the following elements: a system partition element, a system module element, a system port element, a system thread element, a system memory element, and a system mode element.

Any number of modules, sub-modules, units, sub-units, or at least part of the functionality of any number thereof according to embodiments of the present disclosure may be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of the present disclosure may be implemented by being split into a plurality of modules. Any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of the present disclosure may be implemented at least partially as a hardware Circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented by hardware or firmware in any other reasonable manner of integrating or packaging a Circuit, or implemented by any one of three implementations of software, hardware, and firmware, or any suitable combination of any of them. Alternatively, one or more of the modules, sub-modules, units, sub-units according to embodiments of the disclosure may be at least partially implemented as a computer program module, which when executed may perform the corresponding functions.

For example, any plurality of the mapping module 710, the first generating module 720, the first determining module 730, the second determining module 740, and the second generating module 750 may be combined and implemented in one module/unit/sub-unit, or any one of the modules/units/sub-units may be split into a plurality of modules/units/sub-units. Alternatively, at least part of the functionality of one or more of these modules/units/sub-units may be combined with at least part of the functionality of other modules/units/sub-units and implemented in one module/unit/sub-unit. According to an embodiment of the present disclosure, at least one of the mapping module 710, the first generating module 720, the first determining module 730, the second determining module 740, and the second generating module 750 may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or by any other reasonable manner of integrating or packaging a circuit, such as hardware or firmware, or any one of three implementations of software, hardware, and firmware, or any suitable combination of any of them. Alternatively, at least one of the mapping module 710, the first generating module 720, the first determining module 730, the second determining module 740, and the second generating module 750 may be implemented at least in part as a computer program module that, when executed, may perform a corresponding function.

It should be noted that, in the embodiment of the present disclosure, the schedulability model generation apparatus portion corresponds to the schedulability model establishment method portion in the embodiment of the present disclosure, and the description of the schedulability model generation apparatus portion specifically refers to the schedulability model establishment method portion, which is not described herein again.

Fig. 8 schematically shows a block diagram of an electronic device adapted to implement the above described method according to an embodiment of the present disclosure. The electronic device shown in fig. 8 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 8, an electronic device 800 according to an embodiment of the present disclosure includes a processor 801 that can perform various appropriate actions and processes according to a program stored in a Read-Only Memory (ROM) 802 or a program loaded from a storage section 808 into a Random Access Memory (RAM) 803. The processor 801 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or associated chipset, and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), among others. The processor 801 may also include onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing different actions of the method flows according to embodiments of the present disclosure.

In the RAM 803, various programs and data necessary for the operation of the electronic apparatus 800 are stored. The processor 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. The processor 801 performs various operations of the method flows according to the embodiments of the present disclosure by executing programs in the ROM 802 and/or RAM 803. Note that the programs may also be stored in one or more memories other than the ROM 802 and RAM 803. The processor 801 may also perform various operations of method flows according to embodiments of the present disclosure by executing programs stored in the one or more memories.

Electronic device 800 may also include input/output (I/O) interface 805, input/output (I/O) interface 805 also connected to bus 804, according to an embodiment of the present disclosure. The system 800 may also include one or more of the following components connected to the I/O interface 805: an input portion 806 including a keyboard, a mouse, and the like; an output portion 807 including a Display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and a speaker; a storage portion 808 including a hard disk and the like; and a communication section 809 including a network interface card such as a LAN card, a modem, or the like. The communication section 809 performs communication processing via a network such as the internet. A drive 810 is also connected to the I/O interface 805 as necessary. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 810 as necessary, so that a computer program read out therefrom is mounted on the storage section 808 as necessary.

According to embodiments of the present disclosure, method flows according to embodiments of the present disclosure may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication section 809 and/or installed from the removable medium 811. The computer program, when executed by the processor 801, performs the above-described functions defined in the system of the embodiments of the present disclosure. The systems, devices, apparatuses, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the present disclosure.

The present disclosure also provides a computer-readable storage medium, which may be contained in the apparatus/device/system described in the above embodiments; or may exist separately and not be assembled into the device/apparatus/system. The computer-readable storage medium carries one or more programs which, when executed, implement the method according to an embodiment of the disclosure.

According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples may include, but are not limited to: a portable Computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM) or flash Memory), a portable compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the preceding. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

For example, according to embodiments of the present disclosure, a computer-readable storage medium may include the ROM 802 and/or RAM 803 described above and/or one or more memories other than the ROM 802 and RAM 803.

Embodiments of the present disclosure also include a computer program product comprising a computer program containing program code for performing the method provided by the embodiments of the present disclosure, when the computer program product is run on an electronic device, the program code being adapted to cause the electronic device to implement the method for establishing a schedulability model provided by the embodiments of the present disclosure.

The computer program, when executed by the processor 801, performs the above-described functions defined in the system/apparatus of the embodiments of the present disclosure. The systems, apparatuses, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the present disclosure.

In one embodiment, the computer program may be hosted on a tangible storage medium such as an optical storage device, a magnetic storage device, or the like. In another embodiment, the computer program may also be transmitted in the form of a signal on a network medium, distributed, downloaded and installed via communication section 809, and/or installed from removable media 811. The computer program containing program code may be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.

In accordance with embodiments of the present disclosure, program code for executing computer programs provided by embodiments of the present disclosure may be written in any combination of one or more programming languages, and in particular, these computer programs may be implemented using high level procedural and/or object oriented programming languages, and/or assembly/machine languages. The programming language includes, but is not limited to, programming languages such as Java, C + +, python, the "C" language, or the like. The program code may execute entirely on the user computing device, partly on the user device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A method for establishing a schedulability model, comprising the following steps:

determining target model elements required for building a schedulability model from the model elements of the architecture analysis and design language model recorded in the mapping rule table;

determining schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element; and

2. A method according to claim 1, wherein said schedulability attribute configuration information comprises at least one of: scheduling attribute information, dispatch type information, execution time information, processor information, and memory information.

3. The method of claim 2, wherein the mapping relationships in the mapping rule table include partition mapping relationships, module mapping relationships, port mapping relationships, thread mapping relationships, memory mapping relationships, and schema mapping relationships;

wherein the generating the schedulability model using the preset modeling method, the mapping rule table, and the schedulability attribute configuration information includes:

4. The method of claim 1, further comprising:

obtaining a verification analysis tool, wherein the verification analysis tool has a function of analyzing schedulability of the schedulability model; and

analyzing the schedulability of the schedulability model by using the verification analysis tool to obtain a schedulability analysis result; and

and displaying the schedulability analysis result.

5. The method of claim 1, wherein: the system element comprises at least one of the following elements: a system partition element, a system module element, a system port element, a system thread element, a system memory element, and a system mode element.

6. The method of claim 1, wherein: the model element includes at least one of the following elements: a processor element, a virtual processor element, a component process element, a component thread element, a temporal dataport element, a component memory element.

7. A schedulability model generation apparatus, comprising:

the first generation module is used for generating a mapping rule table according to the mapping relation, wherein the mapping rule table comprises a plurality of mapping relations;

a second determination module for determining schedulability attribute configuration information for scheduling the safety critical operating system according to the target model element; and

8. An electronic device, comprising:

one or more processors;

a memory for storing one or more programs,

wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any of claims 1-6.

9. A computer readable storage medium having stored thereon executable instructions which, when executed by a processor, cause the processor to implement the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program which, when executed by a processor, is adapted to carry out the method of any one of claims 1 to 6.