CN113390401A

CN113390401A - Physical quantity detection circuit, physical quantity sensor, and method for operating physical quantity detection circuit

Info

Publication number: CN113390401A
Application number: CN202110264054.9A
Authority: CN
Inventors: 田中敦嗣; 中岛克仁
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2020-03-12
Filing date: 2021-03-10
Publication date: 2021-09-14
Anticipated expiration: 2041-03-10
Also published as: CN113390401B; US20210285769A1; US11976923B2; JP2021143935A; JP7447571B2

Abstract

A physical quantity detection circuit, a physical quantity sensor, and a method of operating the physical quantity detection circuit prevent degradation of A/D conversion accuracy. The physical quantity detection circuit includes: an analog/digital conversion circuit that performs analog/digital conversion processing on an analog signal based on an output signal of the physical quantity detection element and outputs a 1 st digital signal; a digital operation circuit to which the 1 st digital signal is input, which performs operation processing on the 1 st digital signal, and which outputs a 2 nd digital signal; and a regulator circuit that supplies a power supply voltage to the analog/digital conversion circuit and the digital operation circuit. The digital arithmetic circuit does not perform an arithmetic processing start operation for starting arithmetic processing and an arithmetic processing end operation for ending arithmetic processing during an analog-to-digital conversion period for performing the analog-to-digital conversion.

Description

Physical quantity detection circuit, physical quantity sensor, and method for operating physical quantity detection circuit

Technical Field

The present invention relates to a physical quantity detection circuit, a physical quantity sensor, and a method of operating a physical quantity detection circuit.

Background

In various systems and electronic devices, physical quantity sensors capable of detecting various physical quantities, such as a gyro sensor for detecting an angular velocity and an acceleration sensor for detecting an acceleration, are widely used. When the physical quantity sensor is caused to function, an analog signal based on an output signal of the physical quantity detection element is usually converted into a digital signal, and an arithmetic processing based on the digital signal is performed.

Patent document 1 discloses the following structure: a detection circuit 60 having an A/D conversion circuit 100 and a control unit 140 having a DSP unit 150 are provided, and an output signal of the transducer 10 is converted by the A/D conversion circuit 100, and the converted digital signal is processed by the DSP unit. Further, patent document 1 discloses that a power supply voltage is supplied from the regulator circuit 22 to the detection circuit 60 and the control unit 140.

Patent document 1: japanese laid-open patent publication No. 2015-104035

If there is no digital signal to be processed, the DSP unit normally stands by without performing an operation. On the other hand, when a digital signal to be processed is input, the DSP unit starts to operate, and when a predetermined sequence calculation is ended, the DSP unit ends the operation. Therefore, the power consumption rapidly changes at the start timing when the DSP section starts to operate and at the end timing when the DSP section ends to operate. As a result, a load is applied to the regulator circuit at the start timing and the end timing, and the output voltage of the regulator circuit fluctuates. Therefore, in the case of a configuration in which a power supply voltage is supplied to the DSP unit and the a/D conversion circuit using a common regulator circuit as in the conventional art, there is a problem in that the digital signal output from the a/D conversion circuit fluctuates due to fluctuation of the output voltage of the regulator circuit, and the a/D conversion accuracy decreases.

Disclosure of Invention

The physical quantity detection circuit includes: an analog/digital conversion circuit that performs analog/digital conversion processing on an analog signal based on an output signal of the physical quantity detection element and outputs a 1 st digital signal; a digital operation circuit to which a 1 st digital signal is input, which performs operation processing on the 1 st digital signal, and which outputs a 2 nd digital signal; and a regulator circuit that supplies a power supply voltage to the analog/digital conversion circuit and the digital operation circuit, the digital operation circuit having the following configuration: during the analog-to-digital conversion period in which the analog-to-digital conversion is performed, an operation process start operation for starting the operation process and an operation process end operation for ending the operation process are not performed.

The physical quantity sensor includes: the physical quantity detection circuit; and a physical quantity detecting element.

A method of operating a physical quantity detection circuit, the physical quantity detection circuit having: an analog/digital conversion circuit that performs analog/digital conversion processing on an analog signal based on an output signal of the physical quantity detection element and outputs a 1 st digital signal; a digital operation circuit to which a 1 st digital signal is input, which performs operation processing on the 1 st digital signal, and which outputs a 2 nd digital signal; and a regulator circuit that supplies a power supply voltage to the analog/digital conversion circuit and the digital operation circuit, wherein in the operation method of the physical quantity detection circuit, the digital operation circuit has a configuration as follows: during the analog-to-digital conversion period in which the analog-to-digital conversion is performed, an operation process start operation for starting the operation process and an operation process end operation for ending the operation process are not performed.

Drawings

Fig. 1 is a functional block diagram of a physical quantity sensor according to embodiment 1.

Fig. 2 is a plan view of a vibrating reed of the physical quantity detecting element.

Fig. 3 is a diagram for explaining the operation of the physical quantity detection element.

Fig. 4 is a diagram for explaining the operation of the physical quantity detection element.

Fig. 5 is a diagram for explaining operation timings of the analog/digital conversion circuit and the digital operation circuit.

Fig. 6 is a diagram showing a configuration example of the drive circuit.

Fig. 7 is a diagram showing a configuration example of the detection circuit and the analog/digital conversion circuit.

Fig. 8 is a diagram showing a configuration example of the clock generation circuit.

Fig. 9 is a diagram showing a configuration example of the analog/digital conversion circuit.

Fig. 10 is a diagram showing a state of the analog/digital conversion circuit during the sampling period.

Fig. 11 is a diagram showing a state of the analog/digital conversion circuit during the analog/digital conversion.

Fig. 12 is a diagram showing a configuration example of a digital arithmetic circuit.

Description of the reference symbols

1: a physical quantity sensor; 10: a vibrator; 20: a drive circuit; 21: an I/V conversion circuit; 22: a high-pass filter; 23: a comparator; 24: a full-wave rectifying circuit; 25: an integrator; 26: a comparator; 30: a detection circuit; 32: a digital conversion circuit; 32 a: a clock generation circuit; 40: a data processing circuit; 41: a digital arithmetic circuit; 41 a: an input section; 41 b: a multiplier; 41 c: an adder; 41 d: a coefficient ROM; 41 e: a multiplier X input selector; 41 f: a multiplier Y input selector; 41 g: the adder B inputs the selector; 41 h: an operation result saving register; 41 i: a general purpose register; 41 j: a register output selector; 41 k: a register output selector; 41 l: a register output selector; 41 m: a sequencer; 41 n: an output section; 42: an interface circuit; 43: a control circuit; 44: an adjustment circuit; 50: a storage unit; 60: an oscillation circuit; 100: a physical quantity detection element; 101 a: driving the vibrating arm; 101 b: driving the vibrating arm; 102: detecting the vibrating arm; 103: a hammer portion; 104 a: a driving base; 104 b: a driving base; 105 a: a connecting arm; 105 b: a connecting arm; 106: a hammer portion; 107: a base for detection; 112: a drive electrode; 113: a drive electrode; 114: a detection electrode; 115: a detection electrode; 116: a common electrode; 140: a control unit; 150: a DSP section; 200: a physical quantity detection circuit; 210: a Q-V conversion circuit; 211: an operational amplifier; 212: a resistance; 213: a capacitor; 214: an operational amplifier; 215: a resistance; 216: a capacitor; 220: a variable gain amplifier; 221: an operational amplifier; 222: a resistance; 223: a capacitor; 224: a capacitor; 225: an operational amplifier; 226: a resistance; 227: a capacitor; 228: a capacitor; 230: a mixer; 231: a switch; 232: a switch; 233: a switch; 234: a switch; 240: a passive filter; 241: a resistance; 242: a resistance; 243: a capacitor; 270: a digital conversion circuit; 271N: a switch; 271P: a switch; 273N: a switch array; 273P: a switch array; 274N: a capacitor array; 274P: a capacitor array; 275N: a switch; 275P: a switch; 276: a comparator; 277: a logic circuit.

Detailed Description

1. Embodiment 1

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below are not unreasonably restrictive to the contents of the present invention described in the claims. In addition, not all of the configurations described below are essential constituents of the present invention.

Hereinafter, an angular velocity sensor, which is a physical quantity sensor that detects an angular velocity as a physical quantity, will be described as an example.

1-1. Structure of physical quantity sensor

Fig. 1 is a functional block diagram of a physical quantity sensor 1 of the present embodiment. The physical quantity sensor 1 of the present embodiment includes a physical quantity detection element 100 that outputs an analog signal relating to a physical quantity, and a physical quantity detection circuit 200.

The physical quantity detection element 100 includes a drive electrode and a vibration plate on which a detection electrode is disposed, and the vibration plate is generally sealed in a package with ensured airtightness in order to reduce the impedance of the vibration plate as much as possible and improve the oscillation efficiency. In the present embodiment, the physical quantity detection element 100 has a so-called double T-shaped vibrating reed having two driving vibrating arms of a T shape.

Fig. 2 is a plan view of the vibration plate of the physical quantity detection element 100 according to the present embodiment. The physical quantity detection element 100 has a double-T-shaped vibrating reed formed of a Z-cut quartz substrate, for example. The vibrating piece made of quartz has an advantage that the accuracy of detecting the angular velocity can be improved because the resonant frequency of the vibrating piece changes little with respect to temperature change. In fig. 2, the X, Y, and Z axes represent quartz axes. In the coordinates attached to the drawings, a direction along the X axis is referred to as an "X axis direction", a direction along the Y axis is referred to as a "Y axis direction", a direction along the Z axis is referred to as a "Z axis direction", a direction of an arrow is a positive "+" direction, and a direction opposite to the arrow is a negative "-" direction.

As shown in fig. 2, the

driving vibration arms

101a and 101b of the vibration piece of the physical quantity detection element 100 extend in the + Y axis direction and the-Y axis direction from the 2

driving bases

104a and 104b, respectively.

Driving electrodes

112 and 113 are formed on the side and upper surfaces of the driving vibration arm 101a, respectively, and driving

electrodes

113 and 112 are formed on the side and upper surfaces of the driving vibration arm 101b, respectively. The

drive electrodes

112 and 113 are connected to the drive circuit 20 via the DS terminal and the DG terminal of the physical quantity detection circuit 200 shown in fig. 1, respectively. The

driving base portions

104a and 104b are connected to a rectangular detection base portion 107 via connecting

arms

105a and 105b extending in the-X axis direction and the + X axis direction, respectively.

The detection vibration arm 102 extends from the detection base 107 in the + Y axis direction and the-Y axis direction.

Detection electrodes

114 and 115 are formed on the upper surface of the detection vibration arm 102, and a common electrode 116 is formed on the side surface of the detection vibration arm 102. The

detection electrodes

114 and 115 are connected to the detection circuit 30 via the S1 terminal and the S2 terminal of the physical quantity detection circuit 200 shown in fig. 1, respectively. In addition, the common electrode 116 is grounded.

When an alternating voltage is supplied as a drive signal between the drive electrode 112 and the drive electrode 113 of the drive vibrating arms 101a, 101B, the drive vibrating arms 101a, 101B perform flexural vibration in which the tips of the two drive vibrating arms 101a, 101B repeatedly approach and separate from each other as indicated by arrow B due to the inverse piezoelectric effect, as shown in fig. 3. Hereinafter, the bending vibration that drives the vibrating

arms

101a and 101b may be referred to as "excitation vibration".

In this state, when an angular velocity with the Z axis as the rotation axis is applied to the vibrating reed of the physical quantity detecting element 100, the drive vibrating arms 101a and 101B obtain a coriolis force in the direction perpendicular to both the bending vibration direction of the arrow B and the Z axis. As a result, as shown in fig. 4, the connecting

arms

105a and 105b vibrate as indicated by arrows C. Then, the detection vibrating arm 102 performs bending vibration as indicated by arrow D in conjunction with the vibration of the connecting

arms

105a and 105 b. The flexural vibration of the detection vibrating arm 102 caused by the coriolis force is shifted by 90 ° from the flexural vibration of the driving vibrating

arms

101a and 101 b.

Further, if the magnitude of the vibration energy or the magnitude of the vibration amplitude when the driven vibrating

arms

101a and 101b perform flexural vibration is equal among the 2 driven vibrating

arms

101a and 101b, the vibration energy of the driven vibrating

arms

101a and 101b is balanced, and the detection vibrating arm 102 does not perform flexural vibration in a state where the angular velocity is not applied to the physical quantity detection element 100. However, when the vibration energy of the two driving

vibration arms

101a, 101b is out of balance, the detection vibration arm 102 generates flexural vibration even in a state where the angular velocity is not applied to the physical quantity detection element 100. This bending vibration is called leakage vibration, and is similar to the vibration based on coriolis force, but is the same phase as the drive signal, although the bending vibration is the arrow D.

Then, due to the piezoelectric effect, an alternating current charge based on these flexural vibrations is generated on the

detection electrodes

114 and 115 of the detection vibrating arm 102. Here, the alternating-current electric charge generated based on the coriolis force varies depending on the magnitude of the coriolis force (i.e., the magnitude of the angular velocity applied to the physical quantity detection element 100). On the other hand, the alternating-current charge generated based on the leakage vibration is constant regardless of the magnitude of the angular velocity applied to the physical quantity detection element 100.

Further, rectangular weight portions 103 having a width wider than that of the driving

vibration arms

101a and 101b are formed at the ends of the driving

vibration arms

101a and 101 b. By forming the weight 103 at the tip of the driving

vibration arms

101a, 101b, the coriolis force can be increased, and a desired resonance frequency can be obtained with relatively short vibration arms. Similarly, a weight portion 106 having a width wider than that of the detection vibration arm 102 is formed at the tip of the detection vibration arm 102. By forming the weight 106 at the end of the detection resonating arm 102, the ac charge generated in the

detection electrodes

114 and 115 can be increased.

As described above, the physical quantity detection element 100 outputs the alternating current charge based on the coriolis force and the alternating current charge based on the leakage vibration of the excitation vibration via the

detection electrodes

114 and 115 with the Z axis as the detection axis. The physical quantity detection element 100 functions as an inertial sensor that detects an angular velocity. Hereinafter, the ac charge based on the coriolis force may be referred to as an "angular velocity component", and the ac charge based on the leakage vibration may be referred to as a "vibration leakage component".

Returning to the description of fig. 1, the physical quantity detection circuit 200 includes the regulator circuit 10, the drive circuit 20, the detection circuit 30, the analog/digital conversion circuit 32, the data processing circuit 40, the storage section 50, and the oscillation circuit 60. The physical quantity detection Circuit 200 may be realized by, for example, an Integrated Circuit (IC) on a single chip. The physical quantity detection circuit 200 may be configured by omitting or changing a part of these elements, or by adding another element.

The regulator circuit 10 generates a constant voltage or a constant current such as a reference voltage as an analog ground voltage based on the power supply voltage VDD and the ground voltage gnd supplied from the VDD terminal and the VSS terminal of the physical quantity detection circuit 200, respectively, and supplies the same to the drive circuit 20, the detection circuit 30, the analog/digital conversion circuit 32, the data processing circuit 40, the oscillation circuit 60, and the like. The constant voltage supplied to each circuit by the regulator circuit 10 is an example of the power supply voltage of each circuit.

The drive circuit 20 generates a drive signal for exciting the physical quantity detection element 100 to vibrate, and supplies the drive signal to the drive electrode 112 of the physical quantity detection element 100 via the DS terminal. The drive circuit 20 receives an oscillation current generated in the drive electrode 113 by the excitation vibration of the physical quantity detection element 100 via the DG terminal, and performs feedback control on the amplitude level of the drive signal so that the amplitude of the oscillation current is kept constant. The drive circuit 20 generates a detection signal SDET having the same phase as the drive signal, and outputs the detection signal SDET to the detection circuit 30.

The detection circuit 30 receives the ac charges generated in the two

detection electrodes

114 and 115 of the physical quantity detection element 100 via the S1 terminal and the S2 terminal of the physical quantity detection circuit 200, detects an angular velocity component included in the ac charges using the detection signal SDET, and outputs an analog signal VAO1 corresponding to the magnitude of the angular velocity component to the analog/digital conversion circuit 32.

The analog/digital conversion circuit 32 receives the analog signal VAO1 as an input, converts the analog signal into a digital signal VDO having a digital value corresponding to the magnitude of the angular velocity component, and outputs the digital signal VDO. The digital signal VDO is an example of the 1 st digital signal. In the present embodiment, the analog/digital conversion circuit 32 performs analog/digital conversion in synchronization with a clock signal SC output from a control circuit 43 described later.

The storage unit 50 includes a non-volatile memory (not shown) in which various trimming data (for example, adjustment data and correction data) for the drive circuit 20 and the detection circuit 30 are stored. Further, an adjustment value for instructing a timing at which the digital arithmetic circuit 41 starts arithmetic operation, which will be described later, is stored. The adjustment value may be defined in various ways, and for example, a configuration in which the adjustment value is defined according to the number of main clock signals MCLK described later may be mentioned. In this case, the arithmetic processing of the digital arithmetic circuit 41 is started at a timing when a predetermined number of main clock signals MCLK indicated by the adjustment value are output after the reference timing synchronized with the main clock signal MCLK.

The nonvolatile Memory may be configured as a MONOS (Metal Oxide Nitride Silicon) type Memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory), for example. Further, the storage unit 50 may be configured to include a register not shown in the figure, and when the power supply of the physical quantity detection circuit 200 is turned on, that is, when the voltage of the VDD terminal rises from 0V to a desired voltage, the various trimming data stored in the nonvolatile memory may be transferred to and held in the register, and the various trimming data held in the register may be supplied to the drive circuit 20 and the detection circuit 30.

The oscillation circuit 60 generates a main clock signal MCLK, and outputs the main clock signal MCLK to the digital operation circuit 41. The oscillator circuit 60 may be configured as a ring oscillator or a CR oscillator circuit, for example.

The data processing circuit 40 includes a digital arithmetic circuit 41, an interface circuit 42, a control circuit 43, and an adjustment circuit 44. The digital operation circuit 41 operates based on the main clock signal MCLK. Specifically, the adjustment circuit 44 instructs the digital arithmetic circuit 41 to start the operation based on the adjustment value stored in the storage unit 50, and starts the arithmetic processing. For example, when the adjustment value is defined according to the number of the master clock signals MCLK, the master clock signals MCLK output from the control circuit 43 and the oscillation circuit 60 are divided by frequency to generate a reference timing signal SCLK indicating a reference timing of a constant cycle, and the reference timing signal SCLK is output to the adjustment circuit 44. The adjustment circuit 44 counts the number of the main clock signals MCLK based on the reference timing signal SCLK, and starts the operation of the digital operation circuit 41 when the predetermined number indicated by the adjustment value is reached.

Fig. 5 is a timing chart for explaining timings of various signals. As shown in fig. 5, the main clock signal MCLK is a pulse of a constant period output from the oscillation circuit 60. The reference timing signal SCLK is a pulse signal of a constant period, and the period of the reference timing signal SCLK coincides with the operation period of the digital operation circuit 41.

In fig. 5, the operation period of the digital arithmetic circuit 41 is represented as "DSP operation". That is, in the example shown in fig. 5, the adjustment circuit 44 causes the digital operation circuit 41 to start the operation process at the timing of the rising edge of the 4 th master clock signal MCLK after the reference timing signal SCLK. Therefore, in the present embodiment, the adjustment circuit 44 adjusts the timing at which the operation of the digital operation circuit 41 is started. In the present embodiment, the operation period of the digital arithmetic circuit 41 is constant regardless of the arithmetic processing content. Therefore, it can be said that the adjustment circuit 44 adjusts the timing of the operation of starting the arithmetic processing by the digital arithmetic circuit 41 and also adjusts the timing of the operation of ending the arithmetic processing. When the operation period of the digital arithmetic circuit 41 is variable, the adjustment circuit 44 adjusts the operation start operation and the operation end operation.

The digital operation circuit 41 starts operating at the start timing adjusted by the adjustment circuit 44, and performs a predetermined operation process on the digital signal VDO input from the analog/digital conversion circuit 32. That is, the digital operation circuit 41 starts the operation processing after a constant period from the reference timing signal SCLK every time the reference timing signal SCLK is output. In addition, the period required for the arithmetic processing is constant in the digital arithmetic circuit 41, and the arithmetic processing is ended before the constant period from the reference timing signal SCLK. By repeating this operation, the digital arithmetic circuit 41 performs arithmetic processing every time the reference timing signal SCLK is output. When the arithmetic processing is performed, the digital arithmetic circuit 41 outputs the digital data VO obtained by the arithmetic processing.

In the present embodiment, a plurality of digital signals VDO input from the analog/digital conversion circuit 32 are taken in, and digital data VO is output. For example, the digital operation circuit 41 performs an operation process based on the statistical value (average value or the like) of the digital signal VDO of 4 times output from the analog/digital conversion circuit 32. In fig. 5, an analog/digital conversion period in which the analog/digital conversion circuit 32 performs analog/digital conversion is represented as a high level period in the "a/D period". Then, the timing T for generating the operation to start the operation of the digital arithmetic circuit 41 is generated₄The analog/digital conversion period of the captured signal is denoted by D₁～D₄. Of course, the number of the digital signals VDO taken into the digital arithmetic circuit 41 is not limited to 4, and may be other numerical values such as 8. The digital data VO is an example of the 2 nd digital signal.

The control circuit 43 generates a clock signal SC indicating the operation timing of the analog/digital conversion circuit 32, and outputs the clock signal SC to the analog/digital conversion circuit 32. In the present embodiment, the digital signal VDO is acquired a predetermined number of times in the process of 1 operation process by the digital operation circuit 41. Therefore, the control circuit 43 generates the clock signal SC so that pulses of the same number of times as the number of times of capturing the digital signal VDO are output in the cycle of the reference timing signal SCLK that is output once for one operation process of the digital operation circuit 41.

For example, in the example shown in fig. 5, the clock signal SC is generated so as to be output 4 times within 1 cycle of the reference timing signal SCLK. Such a control circuit 43 can be realized by, for example, a frequency divider circuit that divides the main clock signal MCLK.

The analog/digital conversion circuit 32 performs analog/digital conversion in synchronization with the clock signal SC, and performs analog/digital conversion a number of times corresponding to a predetermined number of times of acquisition within a period for 1 time of arithmetic processing by the digital arithmetic circuit 41. Specifically, the analog/digital conversion circuit 32 performs the sample-and-hold operation during a period in which the switch control signal S is at a high level in fig. 5, that is, a period before the clock signal SC. When the clock signal SC is input, the analog/digital conversion circuit 32 compares the reference voltage applied to the comparator with the sampled and held voltage to perform analog/digital conversion. In fig. 5, a period during which the conversion is performed is represented as an a/D period. The operation of the analog/digital conversion circuit 32 will be described in detail later.

The interface circuit 42 executes processing for outputting the digital data VO calculated by the digital calculation circuit 41 to the MCU 5 in response to a request from an MCU (Micro Control Unit) 5 as an external device of the physical quantity detection circuit 200, processing for reading data stored in a nonvolatile memory or a register of the storage Unit 50 and outputting the data to the MCU 5, processing for writing data input from the MCU 5 into the nonvolatile memory or the register of the storage Unit 50, and the like. The Interface circuit 42 is an Interface circuit such as an SPI (Serial Peripheral Interface) bus, and receives a selection signal, a clock signal, and a data signal transmitted from the MCU 5 via the XCS terminal SCLK and the SDI terminal of the physical quantity detection circuit 200, respectively, and outputs the data signal to the MCU 5 via the SDO terminal of the physical quantity detection circuit 200. The interface circuit 42 may be a variety of buses other than the SPI bus, for example, I²And a corresponding interface Circuit such as a C (Inter-Integrated Circuit) bus.

1-2. Structure of drive circuit

Next, the drive circuit 20 will be explained. Fig. 6 is a diagram showing a configuration example of the drive circuit 20. As shown in fig. 6, the drive circuit 20 of the present embodiment includes an I/V conversion circuit 21, a high-pass filter 22, a comparator 23, a full-wave rectification circuit 24, an integrator 25, and a comparator 26. The drive circuit 20 of the present embodiment may be configured by omitting or changing a part of these elements, or by adding another element.

The I/V conversion circuit 21 converts an oscillation current generated by the excitation vibration of the physical quantity detection element 100 and input via a DG terminal into an alternating voltage signal. The high-pass filter 22 removes an offset of the output signal of the I/V conversion circuit 21.

The comparator 23 compares the voltage of the output signal of the high-pass filter 22 with a reference voltage to generate a binarized signal. Then, the comparator 23 turns on the NMOS transistor to output a low level when the binarized signal is at a high level, and turns off the NMOS transistor when the binarized signal is at a low level, and outputs the output voltage of the integrator 25 pulled up via the resistor as a high level. The output signal of the comparator 23 is supplied as a drive signal to the physical quantity detection element 100 via the DS terminal. By matching the frequency of the drive signal with the resonance frequency of the physical quantity detection element 100, the physical quantity detection element 100 can be oscillated stably.

The full-wave rectifier circuit 24 full-wave rectifies the output signal of the I/V conversion circuit 21 and outputs a direct current signal. The integrator 25 integrates and outputs the output voltage of the full-wave rectifier circuit 24 with reference to a desired voltage VRDR supplied from the regulator circuit 10. The higher the output of the full-wave rectifying circuit 24, i.e., the larger the amplitude of the output signal of the I/V conversion circuit 21, the lower the output voltage of the integrator 25. Therefore, the larger the oscillation amplitude, the lower the high level voltage of the drive signal as the output signal of the comparator 23, the smaller the oscillation amplitude, the higher the high level voltage of the drive signal, and thus Automatic Gain Control (AGC) is performed to keep the oscillation amplitude constant. The comparator 26 amplifies the voltage of the output signal of the high-pass filter 22 to generate a square wave voltage signal as a binarized signal, and outputs the square wave voltage signal as a detection signal SDET.

1-3. Structure of detection circuit

Next, the detection circuit 30 and the analog/digital conversion circuit 32 are explained. Fig. 7 is a diagram showing an example of the configuration of the detection circuit 30 and the analog/digital conversion circuit 32. As shown in fig. 7, the detection circuit 30 of the present embodiment includes a Q-V conversion circuit 210, a variable gain amplifier 220, a mixer 230, and a passive filter 240. The detection circuit 30 of the present embodiment may be configured by omitting or changing a part of these elements or by adding another element.

The Q-V conversion circuit 210 includes an operational amplifier 211, a resistor 212, a capacitor 213, an operational amplifier 214, a resistor 215, and a capacitor 216. Ac charges including an angular velocity component and a vibration leakage component are input to the operational amplifier 211 from the detection electrode 114 of the vibrating reed of the physical quantity detection element 100 via the S1 terminal. The resistor 212 is a feedback resistor of the operational amplifier 211. Further, the capacitor 213 is a feedback capacitance of the operational amplifier 211. Similarly, an ac charge including an angular velocity component and a vibration leakage component is input from the detection electrode 115 of the vibrating reed of the physical quantity detecting element 100 to the operational amplifier 214 via the S2 terminal.

Resistor 215 is the feedback resistor of op amp 214. Further, the capacitor 216 is a feedback capacitance of the operational amplifier 214. The phase of the ac charge input to the operational amplifier 211 differs by 180 ° from the phase of the ac charge input to the operational amplifier 214, and the phase of the output signal of the operational amplifier 211 is opposite to the phase of the output signal of the operational amplifier 214. The Q-V conversion circuit 210 configured as described above converts the ac charges input from the S1 terminal and the S2 terminal into voltage signals, and outputs differential signals having opposite phases to each other. That is, the Q-V conversion circuit 210 functions as a signal conversion circuit that converts the output signal of the physical quantity detection element 100 into a voltage.

The variable gain amplifier 220 includes an operational amplifier 221, a resistor 222, a capacitor 223, a capacitor 224, an operational amplifier 225, a resistor 226, a capacitor 227, and a capacitor 228. The resistances of the

resistors

222, 226 are variable, and the capacitances of the

capacitors

223, 224, 227, 228 are variable.

The signal output from the operational amplifier 211 is input to the operational amplifier 221 via the capacitor 224. The resistor 222 is a feedback resistor of the operational amplifier 221. Further, the capacitor 223 is a feedback capacitance of the operational amplifier 221. Similarly, the signal output from the operational amplifier 214 is input to the operational amplifier 225 via the capacitor 228. Resistor 226 is the feedback resistor of operational amplifier 225. Further, the capacitor 227 is a feedback capacitance of the operational amplifier 225. The variable gain amplifier 220 configured as described above amplifies the differential signal output from the Q-V conversion circuit 210 and outputs a differential signal of a desired voltage level.

Mixer 230 includes switch 231, switch 232, switch 233, and switch 234. The

switches

231 and 233 are turned on when the detection signal SDET output from the drive circuit 20 is at a high level, and turned off when the detection signal SDET output from the drive circuit 20 is at a low level. Switches 232 and 234 are turned on when detection signal SDET is at a low level, and turned off when detection signal SDET is at a high level. Mixer 230 directly outputs the differential signal output from variable gain amplifier 220 when detection signal SDET is at a high level, and outputs a signal obtained by interchanging the positive and negative of the differential signal output from variable gain amplifier 220 when detection signal SDET is at a low level. The mixer 230 configured as described above functions as a detector circuit, detects the differential signal output from the variable gain amplifier 220 using the detection signal SDET, and outputs a differential signal including an angular velocity component. The differential signal output from the mixer 230 is a signal having a voltage level corresponding to the angular velocity applied to the physical quantity detection element 100. The differential signal output from the mixer 230 is an example of "an analog signal based on the output signal of the physical quantity detection element".

Passive filter 240 includes a resistor 241, a resistor 242, and a capacitor 243. One end of the resistor 241 is connected to one end of the capacitor 243, one end of the resistor 242 is connected to the other end of the capacitor 243, and the differential signal output from the mixer 230 is input to the other end of the resistor 241 and the other end of the resistor 242. The passive filter 240 thus configured functions as a low-pass filter and outputs the differential signals Vp and Vn obtained by attenuating high-frequency noise of the differential signal output from the mixer 230. The differential signals Vp and Vn correspond to the analog signal VAO1 shown in fig. 1.

The passive filter 240 also functions as an anti-aliasing filter for the analog/digital conversion circuit 32. Since the passive filter 240 does not include an active element such as a transistor that generates 1/f noise, the output noise is lower than that of an active filter configured using an active element, and the S/N ratio of the output signal of the physical quantity sensor 1 can be increased. In addition, the passive filter 240 may be a band-pass filter according to the use of the physical quantity sensor 1.

1-4. structure of analog/digital conversion circuit

Next, the analog/digital conversion circuit 32 will be explained. The analog/digital conversion circuit 32 has a clock generation circuit 32 a. The clock generation circuit 32a is a circuit that generates the clock signal ADCLK.

The clock signal ADCLK is a clock signal for operating a logic circuit 277, which will be described later, of the analog/digital conversion circuit 32, and is generated using the clock signal SC output from the control circuit 43 as a trigger. The clock generation circuit 32a is triggered by the clock signal SC, but the generation of the clock signal ADCLK itself is performed asynchronously with the clock signal SC or the master clock signal MCLK.

As such a circuit, for example, a circuit as shown in fig. 8 can be given. The clock generation circuit 32a shown in fig. 8 includes a D flip-flop, and a delay circuit is connected between an output terminal Q and a reset terminal R of the D flip-flop. The delay circuit is constituted by a multi-stage inverter. The input terminal D of the D flip-flop is fixed to a high level. In this configuration, when the input trigger In is input to the clock terminal C, the output Out becomes a high level. Since the high-level signal is delayed by the delay circuit and then input to the reset terminal R, the D flip-flop is reset at this stage, and the output Out becomes low. By repeating this operation, a continuous pulse signal is output at the output Out. In this example, the pulse signal becomes the clock signal ADCLK.

In the present embodiment, the clock generation circuit 32a is stopped after the clock signal ADCLK is output the number of times necessary for the operation of the logic circuit 277. That is, in the present embodiment, while the clock generation circuit 32a outputs the clock signal ADCLK, the logic circuit 277 performs analog-to-digital conversion. The period during which the analog/digital conversion is performed is an analog/digital conversion period, which is shown as an a/D period in fig. 5.

In fig. 5, the clock signal ADCLK generated during this a/D period is shown. The scale in the time direction of the clock signal ADCLK is shown in an enlarged manner, and the first 1 cycle Tm of the clock signal SC shown in fig. 5 is shown in an enlarged manner.

The analog-digital conversion circuit 32 operates based on the clock signal ADCLK, and samples the differential signals Vp and Vn into the input capacitance of the analog-digital conversion circuit 32 to convert the differential signals into digital signals.

In the present embodiment, the analog/digital conversion circuit 32 is a successive approximation type analog/digital conversion circuit. Fig. 9 is a diagram showing a configuration example of the analog/digital conversion circuit 32. As shown in fig. 9, the analog/digital conversion circuit 32 of the present embodiment includes a switch 271P, a switch 271N, a switch array 273P, a switch array 273N, a capacitor array 274P, a capacitor array 274N, a switch 275P, a switch 275N, a comparator 276, and a logic circuit 277. The analog/digital conversion circuit 32 of the present embodiment may be configured by omitting or changing a part of these elements or by adding other elements.

The

capacitor arrays

274P and 274N each have a plurality of capacitors having different capacitance values and function as input capacitances of the analog-to-digital conversion circuit 32. The logic circuit 277 controls the operations of the

switches

271P, 271N, 275P, 275N and the

switch arrays

273P, 273N in accordance with the input clock signal ADCLK.

Specifically, the logic circuit 277 first turns the switch control signal S high, controls the

switches

271P and 271N on, and performs a sample-and-hold operation of sampling the input signals Vp and Vn into the capacitors of the

capacitor arrays

274P and 274N.

Fig. 10 is a diagram showing the connection state of the

capacitor arrays

274P and 274N in a state where the switch control signal S is at a high level. In this state, the differential signal Vp output from the passive filter 240 is supplied to one end of each capacitor of the capacitor array 274P. One end of each capacitor of the capacitor array 274N is supplied with the differential signal Vn output from the passive filter 240. The reference voltage is supplied to the other end of each capacitor of the

capacitor arrays

274P and 274N.

Next, when a predetermined time required for sampling has elapsed after the switching control signal S is changed from the low level to the high level, the logic circuit 277 changes the switching control signal S from the high level to the low level. In this embodiment, the period during which the switch control signal S is at a low level is an analog-to-digital conversion period. When the switch control signal S becomes low level, the logic circuit 277 controls the

switches

271P, 271N to be off, and controls the

switches

275P, 275N to be off. The logic circuit 277 repeats the operation of switching the

switch arrays

273P and 273N times and applying the power supply voltage vdd or the ground voltage gnd to the capacitors of the

capacitor arrays

274P and 274N, depending on whether the binarized signal output from the comparator 276 is at the high level or the low level. The logic circuit 277 converts the binary signal output from the comparator 276 in parallel to generate an N-bit digital signal VDO having a digital value corresponding to the difference between the voltage of the input signal Vp and the voltage of the input signal Vn.

Fig. 11 is a diagram showing a state in which the switch control signal S is at a low level, that is, a connection state of the

capacitor arrays

274P and 274N during the analog-to-digital conversion. In this state, the switch array 273P is controlled by a control signal from the logic circuit 277, one end of each capacitor of the capacitor array 274P is connected to the power supply voltage vdd or the ground voltage gnd, and the other end of each capacitor of the capacitor array 274P is connected to one input terminal of the comparator 276. In addition, the switch array 273N is controlled by a control signal from the logic circuit 277, one end of each capacitor of the capacitor array 274N is connected to the power supply voltage vdd or the ground voltage gnd, and the other end of each capacitor of the capacitor array 274N is connected to the other input terminal of the comparator 276.

1-5. improvement of A/D conversion accuracy

The analog/digital conversion circuit 32 of the present embodiment operates using the power supply voltage generated by the regulator circuit 10, and converts an analog signal into a digital signal based on the comparison of the comparator 276. Therefore, when the power supply voltage fluctuates, the accuracy of analog/digital conversion may be degraded. As described above, in the present embodiment, the analog/digital conversion circuit 32 and the data processing circuit 40 are driven by the same regulator circuit 10 receiving power supply. Therefore, when the power consumption in the data processing circuit 40 changes rapidly, the voltage supplied to the analog/digital conversion circuit 32 may fluctuate. In this case, the power supply voltage used in the analog/digital conversion circuit 32 may fluctuate. When the power supply voltage fluctuates, the digital signal VDO output from the analog/digital conversion circuit 32 may have a value different from the original value.

In the present embodiment, the power consumption in the data processing circuit 40 changes abruptly at the timing when the arithmetic processing in the digital arithmetic circuit 41 starts to operate and at the timing when the arithmetic processing ends to operate. Therefore, when at least one of the timing of the operation start operation and the timing of the operation end operation is included in the analog/digital conversion period in the analog/digital conversion circuit 32, the conversion accuracy in the analog/digital conversion circuit 32 may be degraded.

Therefore, in the present embodiment, the digital arithmetic circuit 41 is configured to perform the arithmetic processing start operation and the arithmetic processing end operation in a period other than the analog/digital conversion period. Specifically, in the present embodiment, the analog-to-digital conversion period is started with the clock signal SC as a trigger. Therefore, in the present embodiment, the longest analog/digital conversion period required for conversion in the analog/digital conversion circuit 32 is determined by design, actual measurement, or the like of the physical quantity detection element 100 and the analog/digital conversion circuit 32.

In the present embodiment, the timing later than the end timing of the analog-to-digital conversion period that is the longest analog-to-digital conversion period and earlier than the next clock signal SC is determined in advance. Then, in order to start the arithmetic processing of the digital arithmetic circuit 41 at this timing, an adjustment value for instructing the digital arithmetic circuit 41 to start the arithmetic processing is determined.

The adjustment value is determined so that the arithmetic processing by the digital arithmetic circuit 41 is ended at a timing later than the end timing of the analog-to-digital conversion period that is the longest analog-to-digital conversion period and earlier than the next clock signal SC. Therefore, by performing the operation for starting the arithmetic processing in the digital arithmetic circuit 41 based on the adjustment value and performing the operation for ending the arithmetic processing, the digital arithmetic circuit 41 can perform the operation for starting the arithmetic processing and the operation for ending the arithmetic processing in a period other than the analog/digital conversion period. Therefore, in the present embodiment, the digital conversion by the analog/digital conversion circuit 32 can be performed without lowering the conversion accuracy.

In the present embodiment, the analog-to-digital conversion period varies depending on temperature or the like, and the temperature characteristic may be different from the temperature characteristic of the cycle of the main clock signal MCLK. Specifically, the clock signal ADCLK, which is an operation clock of the analog/digital conversion circuit 32 according to the present embodiment, is generated by the clock generation circuit 32 a. On the other hand, the oscillation circuit 60 generates a master clock signal MCLK or a reference timing signal SCLK, which is an operation clock of the digital operation circuit 41. The clock signal SC, which triggers the operation of the clock generation circuit 32a, is generated from the master clock signal MCLK, but the clock signal ADCLK is generated by the clock generation circuit 32a independently of the master clock signal MCLK. Therefore, in the present embodiment, the operation clock of the analog/digital conversion circuit 32 and the operation clock of the digital operation circuit 41 are generated by different clock generation circuits.

In the present embodiment, the temperature characteristic that varies during the analog-to-digital conversion is different from the temperature characteristic that varies the cycle of the main clock signal MCLK, because the operating clock generation circuits are different from each other. Therefore, even if the cycle of the master clock signal MCLK, the reference timing signal SCLK, and the clock signal SC is assumed to be constant, the analog/digital conversion period may vary.

In fig. 5, the situation of the variation during the analog/digital conversion is highlighted. E.g. during analog/digital conversion D₁～D₄Is varied in length. Since the analog/digital conversion period may vary depending on temperature or the like in this manner, the longest analog/digital conversion period required for conversion in the analog/digital conversion circuit 32 is determined in advance as described above.

In fig. 5, an example in which the analog/digital conversion period is longest is represented as D_max. In this way, the adjustment value is adjusted so that the operation start operation and the operation end operation of the digital operation circuit 41 become the longest D during the analog-to-digital conversion period_maxThe time comes within a period Ts between the end timing of the analog/digital conversion period of the time and the output timing of the next clock signal SC.

With the above configuration, the operation start operation and the operation end operation of the digital operation circuit 41 are not performed during the analog/digital conversion period in which the comparator performs the analog/digital conversion by the power supply voltage in the analog/digital conversion circuit 32. Therefore, even if the output voltage of the regulator circuit 10 fluctuates due to the operation start operation and the operation end operation of the digital operation circuit 41, the conversion accuracy of the analog/digital conversion circuit 32 does not decrease.

1-6 modifications

In the above-described embodiment or the embodiments described later, the input signal of the analog/digital conversion circuit 32 is a differential signal, but may be a single-ended signal. In this case, the differential signal output from the physical quantity detection element 100 is converted into a single-ended signal in any one of the Q-V conversion circuit 210, the variable gain amplifier 220, the mixer 230, and the passive filter 240 of the detection circuit 30. For example, the variable gain amplifier 220 may convert the differential signal output from the Q-V conversion circuit 210 into a single-ended signal, and the mixer 230 and the passive filter 240 may perform the above-described processes on the single-ended signal.

In the above-described embodiment, the example of the angular velocity sensor including the physical quantity detection element 100 that detects the angular velocity is described as the physical quantity sensor 1, but the physical quantity detected by the physical quantity detection element 100 is not limited to the angular velocity, and may be angular acceleration, velocity, force, or the like. The vibrating reed of the physical quantity detecting element 100 may not be of a double T shape, but may be of a tuning fork type, a comb tooth type, or a triangular prism type, a quadrangular prism type, a columnar type, or other shapes. The vibrating reed of the physical quantity detecting element 100 may be made of, for example, quartz (SiO) instead of quartz₂) And lithium tantalate (LiTaO) is used₃) Lithium niobate (LiNbO)₃) Silicon semiconductors can also be used as piezoelectric materials such as piezoelectric single crystals and piezoelectric ceramics such as lead zirconate titanate (PZT). The vibrating reed of the physical quantity detection element 100 may have a structure in which a piezoelectric thin film such as zinc oxide (ZnO) or aluminum nitride (AlN) sandwiched between drive electrodes is disposed on a part of the surface of a silicon semiconductor, for example. The physical quantity detection element 100 is not limited to a piezoelectric type element, and may be a vibrating type element such as an electrodynamic type, a capacitance type, an eddy current type, an optical type, or a strain gauge type. For example, the physical quantity detecting element 100 may be an electrostatic capacitance type MEMS (Micro Electro Mechanical Systems) vibrator. Further, the detection method of the physical quantity detection element 100The optical system is not limited to the vibration system, and may be, for example, an optical system, a rotary system, or a fluid system.

In the above-described embodiment, the example of the single-axis sensor having one physical quantity detection element 100 is described as the physical quantity sensor 1, but the physical quantity sensor 1 may be a multi-axis sensor having a plurality of physical quantity detection elements 100. For example, the physical quantity sensor 1 may be a 3-axis gyro sensor having 3 physical quantity detection elements that detect angular velocities around 3 axes different from each other, or may be a composite sensor having a physical quantity detection element that detects an angular velocity and a physical quantity detection element that detects acceleration.

2. Embodiment 2

The configuration for preventing the conversion accuracy of the analog/digital conversion circuit 32 from being degraded by the voltage variation in the regulator circuit 10 is not limited to embodiment 1. That is, the digital operation circuit 41 may be configured not to perform the operation start operation and the operation end operation during the analog-to-digital conversion period in which the analog-to-digital conversion is performed.

Such a configuration is a configuration in which the digital operation circuit 41 performs an operation process at least during an analog/digital conversion period. That is, if the digital arithmetic circuit 41 is configured to always perform the arithmetic processing during the analog-to-digital conversion period, the digital arithmetic circuit 41 can be configured not to perform the arithmetic processing start operation and the arithmetic processing end operation during the analog-to-digital conversion period.

The configuration in which the digital arithmetic circuit 41 performs arithmetic processing at least during analog/digital conversion can also be realized by performing arithmetic processing in the digital arithmetic circuit 41 all the time. That is, if the digital arithmetic circuit 41 is configured to always perform arithmetic processing, an explicit arithmetic processing start operation and an explicit arithmetic processing end operation are not performed. As a result, the operation start operation and the explicit operation end operation are not performed during the analog-to-digital conversion period.

Such a configuration is, for example, a configuration in which the digital arithmetic circuit 41 performs arithmetic processing also in the period Td shown in fig. 5. Specifically, the present invention can be realized by the following configuration: in the same configuration as that shown in fig. 1, the digital operation circuit 41 alternately repeats the 1 st operation process, which is an operation process for the 1 st digital signal, and the 2 nd operation process, which is not used for the output of the 2 nd digital signal. That is, during the operation period of the digital operation circuit 41 shown in fig. 5, the 1 st operation processing for performing the operation processing on the 1 st digital signal and outputting the 2 nd digital signal is executed, and the 2 nd operation processing is executed during the period Td.

The digital operation circuit 41 performing such an operation is realized by a circuit shown in fig. 12, for example. The digital arithmetic circuit 41 shown in fig. 12 includes an input unit 41a, a multiplier 41B, an adder 41c, a coefficient ROM 41d, a multiplier X input selector 41e, a multiplier Y input selector 41f, an adder B input selector 41g, an arithmetic result storage register 41h, a general-purpose register 41i, register

output selectors

41j, 41k, and 41l, a sequencer 41m, and an output unit 41 n.

The sequencer 41m controls and selects each selector of the multiplier X input selector 41e, the multiplier Y input selector 41f, the adder B input selector 41g, and the

register output selectors

41j, 41k, and 41l based on the adjustment value stored in the storage unit 50. The sequencer 41m controls each of the operation result storage register 41h and the general-purpose register 41i for storing the operation result. That is, the sequencer 41m controls each selector to select a desired operator input, and causes the multiplier 41b and the adder 41c to perform product-sum operation and store the result in the register. The coefficient ROM 41d is a ROM that holds coefficients, and the coefficients can be adjusted according to adjustment values stored in the storage unit 50.

In the present embodiment, the operation result storage register 41h is a register for holding tap of a filter, for example, and is a register used for each type of operation processing, such as a register for holding an operation result. On the other hand, the general-purpose register 41i is a register that temporarily holds an intermediate processing result.

In the present embodiment, the adjustment value for the 1 st arithmetic processing and the adjustment value for the 2 nd arithmetic processing are stored in the storage unit 50. The sequencer 41m starts the 1 st arithmetic processing at a predetermined timing synchronized with the reference timing signal SCLK. That is, the sequencer 41m takes in the digital signal VDO of the predetermined number of times of taking in at a rate of once every 1 time of the reference timing signal SCLK, controls each selector, and selects the input X, Y to the multiplier 41 b. The sequencer 41m controls each selector to select the input B to the adder 41 c. The sequencer 41m controls each selector to select a register and hold the operation result. As a result of the above, the digital data VO is output from the output unit 41 n.

On the other hand, the sequencer 41m executes the 2 nd arithmetic processing during a period from the timing when the 1 st arithmetic processing ends to the timing when the next 1 st arithmetic processing starts. At this time, the sequencer 41m starts the 2 nd arithmetic processing based on the adjustment value for the 2 nd arithmetic processing at the time when the 1 st arithmetic processing is finished. In the present embodiment, the period required for the 1 st arithmetic processing is constant and predetermined. The period of the reference timing signal SCLK is also a period determined by the master clock signal MCLK, and is predetermined. Therefore, the length of the period Td during which the 2 nd arithmetic processing is to be executed is also known.

Therefore, the adjustment value for the 2 nd arithmetic processing is determined in advance so that the sequencer 41m executes arithmetic processing of the same length as the period Td. Therefore, the sequencer 41m executes the 2 nd arithmetic processing during the period Td, and if the period Td ends, the 2 nd arithmetic processing ends and the 1 st arithmetic processing starts. The digital signal input to the input unit 41a in the 2 nd arithmetic processing may be the same as or different from that in the 1 st arithmetic processing.

In the present embodiment, at least a part of the 2 nd arithmetic processing is the same as the 1 st arithmetic processing. That is, the adjustment value for the 2 nd arithmetic processing is information for executing a part of the 1 st arithmetic processing. As described above, since part of the 2 nd arithmetic processing is the same as the 1 st arithmetic processing, the power consumption of the 2 nd arithmetic processing is substantially the same as the power consumption of the 1 st arithmetic processing, and the statistical fluctuation range of the power consumption is within the predetermined range. Therefore, in the present embodiment, the power consumption in the digital operation circuit 41 does not vary greatly. Therefore, the output voltage of the regulator circuit 10 does not fluctuate due to the digital operation circuit 41, and even if the regulator circuit 10 is shared by the digital operation circuit 41 and the analog/digital conversion circuit 32, the accuracy of analog/digital conversion does not decrease.

The 2 nd arithmetic processing is executed during the 1 st arithmetic processing, and the presence of the 2 nd arithmetic processing suppresses variation in power consumption of the digital arithmetic circuit 41, and as a result, it is sufficient to prevent a decrease in conversion accuracy of the analog/digital conversion circuit 32. Therefore, the power consumption in the 1 st arithmetic processing and the power consumption in the 2 nd arithmetic processing may be different. For example, the power consumption in the 2 nd arithmetic processing may be smaller than the power consumption in the 1 st arithmetic processing.

Such a configuration can also be realized by adjusting the adjustment value for the 2 nd arithmetic processing. Specifically, in the digital arithmetic circuit 41 shown in fig. 12, if a fixed value is selected to be input to the input X and the input Y of the multiplier 41b, the multiplier 41b is configured by a combinational circuit, and therefore, a constant value is output from the multiplier 41b, and the operation of the multiplier 41b can be substantially stopped. Then, if each selector is controlled so that the value of the general-purpose register 41i is input to the adder 41c, for example, the multiplier 41b can be stopped and the adder 41c can be operated.

If the adjustment value is selected so that the sequencer 41m performs such processing, it is possible to prevent the generation of power consumption of the multiplier 41b and to realize a state in which power is consumed by the operation of the adder 41 c. As a result, the power consumption of the 2 nd arithmetic processing can be suppressed, and the presence of the 2 nd arithmetic processing can prevent the power consumption of the digital arithmetic circuit 41 from rapidly changing at the start and end of the 1 st arithmetic processing. Therefore, even if the regulator circuit 10 is shared by the digital operation circuit 41 and the analog/digital conversion circuit 32, it is possible to prevent the accuracy of analog/digital conversion from being lowered.

5. Other embodiments and the like

The analog/digital conversion circuit is not limited as long as it can perform analog/digital conversion processing on an analog signal based on the output signal of the physical quantity detection element and output the 1 st digital signal. That is, the analog signal is converted into the digital signal in accordance with the power supply voltage supplied from the regulator circuit, and therefore, there is a possibility that the output accuracy of the digital signal is lowered in accordance with the output voltage variation of the regulator circuit, and all analog/digital conversion circuits are targeted. Therefore, a circuit other than the SAR analog-to-digital conversion circuit as in the above-described embodiment, for example, a delta-sigma type circuit having a comparator, or the like may be used.

The digital operation circuit may be any circuit as long as it receives the 1 st digital signal, performs operation processing on the 1 st digital signal, and outputs the 2 nd digital signal. That is, the digital arithmetic circuit is driven by the power supply voltage supplied from the regulator circuit, and the power supplied from the regulator circuit greatly fluctuates at the start time of the operation for starting the arithmetic processing and the end time of the operation for ending the arithmetic processing. The arithmetic processing and the circuit for performing the arithmetic processing are not limited to the above-described embodiments, and various processes and circuits are possible.

The digital arithmetic circuit may be configured so that an arithmetic processing start operation for starting the arithmetic processing and an arithmetic processing end operation for ending the arithmetic processing are not performed during the analog-to-digital conversion period. Therefore, the present invention is not limited to the configuration in which the 2 nd arithmetic processing is performed as in the above-described embodiment, and the configuration in which the 2 nd arithmetic processing or the original 1 st arithmetic processing is continued in the digital arithmetic circuit. For example, the 2 nd arithmetic processing or the 1 st arithmetic processing is performed during the analog/digital conversion period, and the arithmetic processing start operation and the arithmetic processing end operation are performed during a period other than the analog/digital conversion period, or a period in which the arithmetic processing is not performed may exist.

The regulator circuit may be any circuit as long as it supplies a power supply voltage to the analog/digital conversion circuit and the digital operation circuit. That is, the regulator circuit may be any circuit that generates a predetermined voltage from power supplied from the outside and supplies the generated voltage to any circuit. The supply target of the power supply voltage includes at least an analog/digital conversion circuit and a digital operation circuit, and may include other circuits. The voltage value is not limited, and may be the same as or different from the analog/digital conversion circuit and the digital operation circuit.

The configuration in which the operation clock of the analog/digital conversion circuit and the operation clock of the digital operation circuit are generated by different clock generation circuits is not limited to the above configuration. That is, when the operation clock of the analog/digital conversion circuit and the operation clock of the digital operation circuit are generated by different clock generation circuits, the relationship between the analog/digital conversion period and the operation start operation and the operation end operation is not constant. Therefore, even if the analog-to-digital conversion period varies, it is necessary to perform control so that the operation start operation and the operation end operation do not fall within the analog-to-digital conversion period. Such a problem may occur due to the difference in clock generation circuits between the analog/digital conversion circuit and the digital operation circuit. Therefore, the clock generation circuits may be different from each other, and may have a partially overlapping structure.

The above-described embodiment and modification are examples, and are not limited thereto. For example, the embodiments and the modifications can be appropriately combined. The present invention includes substantially the same structures as those described in the embodiments, for example, structures having the same functions, methods, and results or structures having the same objects and effects. The present invention includes a structure obtained by replacing a non-essential part of the structure described in the embodiments. The present invention includes a configuration that can achieve the same operational effects as the configurations described in the embodiments or a configuration that can achieve the same object. The present invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

Claims

1. A physical quantity detection circuit having:

an analog/digital conversion circuit that performs analog/digital conversion processing on an analog signal based on an output signal of the physical quantity detection element and outputs a 1 st digital signal;

a digital operation circuit to which the 1 st digital signal is input, which performs operation processing on the 1 st digital signal, and which outputs a 2 nd digital signal; and

a regulator circuit that supplies a power supply voltage to the analog/digital conversion circuit and the digital operation circuit,

the digital arithmetic circuit does not perform an arithmetic processing start operation for starting arithmetic processing and an arithmetic processing end operation for ending arithmetic processing during an analog-to-digital conversion period in which the analog-to-digital conversion processing is performed.

2. The physical quantity detection circuit according to claim 1,

the operation clock of the analog/digital conversion circuit and the operation clock of the digital operation circuit are generated by different clock generation circuits.

3. The physical quantity detection circuit according to claim 1 or 2, wherein,

the digital arithmetic circuit performs arithmetic processing at least during the analog/digital conversion.

4. The physical quantity detection circuit according to claim 1,

the digital operation circuit alternately repeats a 1 st operation process and a 2 nd operation process not used for output of the 2 nd digital signal, the 1 st operation process being an operation process on the 1 st digital signal.

5. The physical quantity detection circuit according to claim 4,

at least a part of the 2 nd arithmetic processing is the same as the 1 st arithmetic processing.

6. The physical quantity detection circuit according to claim 4 or 5, wherein,

the power consumption of the 2 nd arithmetic processing is substantially the same as the power consumption of the 1 st arithmetic processing.

7. The physical quantity detection circuit according to claim 4 or 5, wherein,

the power consumption of the 2 nd arithmetic processing is smaller than the power consumption of the 1 st arithmetic processing.

8. The physical quantity detection circuit according to claim 1 or 2, wherein,

the digital arithmetic circuit performs the arithmetic processing start operation and the arithmetic processing end operation in a period other than the analog-to-digital conversion period.

9. The physical quantity detection circuit according to claim 8,

the physical quantity detection circuit includes an adjustment circuit that adjusts a timing of the operation to start the arithmetic processing and a timing of the operation to end the arithmetic processing.

10. The physical quantity detection circuit according to claim 9,

the physical quantity detection circuit has a storage section for storing the adjustment value,

the adjustment circuit adjusts the timing of the operation for starting the arithmetic processing and the timing of the operation for ending the arithmetic processing based on the adjustment value stored in the storage unit.

11. A physical quantity sensor having:

the physical quantity detection circuit according to any one of claims 1 to 10; and

the physical quantity detection element.

12. A method of operating a physical quantity detection circuit, the physical quantity detection circuit having:

in the operation method of the physical quantity detection circuit,