CN113380767B - Chip version number control structure and method - Google Patents
Chip version number control structure and method Download PDFInfo
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- CN113380767B CN113380767B CN202110524457.2A CN202110524457A CN113380767B CN 113380767 B CN113380767 B CN 113380767B CN 202110524457 A CN202110524457 A CN 202110524457A CN 113380767 B CN113380767 B CN 113380767B
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- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 160
- 238000012986 modification Methods 0.000 claims abstract description 5
- 230000004048 modification Effects 0.000 claims abstract description 5
- 230000005669 field effect Effects 0.000 claims description 13
- 238000013461 design Methods 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/71—Version control; Configuration management
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
Abstract
The invention discloses a chip version number control structure and a method, which belong to the field of chip version design and comprise the following steps: the first region includes a plurality of first metal layers; the second area comprises a plurality of second metal layers, and logic level signals flowing in the first metal layers and the second metal layers are different; the plurality of bit control lines are respectively connected with a first metal layer or a second metal layer; the switching control module is used for disconnecting one metal layer of one area and switching the disconnected metal layer to the metal layer of the same layer of the other area; and the output module is connected with the plurality of bit control lines and is used for reading output signals of the corresponding plurality of bit control lines when the connection relation of any one of the first metal layer or the second metal layer is changed, and forming a version number after chip modification. The invention has the beneficial effects that: the chip version number can be changed at will through the switching control module, and the chip version number is updated, stored and managed.
Description
Technical Field
The invention relates to the field of chip version design, in particular to a chip version number control structure and method.
Background
The chip version number (chip version) is a version used to identify the integrated circuit (Integrated Circuit, IC) chip. In IC designs, the chip version number is typically represented by a binary number of several bits.
When a chip is developed, a chip which can be normally used finally is usually obtained by carrying out repeated version changing, and the version number of the chip is correspondingly changed when the chip is changed, so that the corresponding bit is required to be changed to form a new chip version number so as to record the development version of the chip, and the matched chip software or test program can be used for correspondingly configuring the chip according to the chip version number in the subsequent process.
In the prior art, a register is generally used to store a version number of a chip, and the version number of the chip needs to be changed by operating the register after each change of design of the chip.
Disclosure of Invention
The invention aims to provide a chip version number control structure and a method.
The technical problems solved by the invention can be realized by adopting the following technical scheme:
the invention provides a chip version number control structure, which comprises:
the first area comprises a plurality of first metal layers which are sequentially stacked, and a through hole layer is arranged between two adjacent first metal layers;
the second area comprises a plurality of second metal layers which are sequentially stacked, a through hole layer is arranged between two adjacent second metal layers, and logic level signals flowing in the first metal layers and the second metal layers are different;
a plurality of bit control lines, wherein the bit control lines are respectively connected with one of the first metal layers or one of the second metal layers, and the number of the bit control lines is the same as the number of bits of the chip version number;
the switching control module is used for disconnecting one metal layer of one area and switching and connecting the disconnected metal layer to the metal layer of the same layer of the other area;
and the output module is connected with the plurality of bit control lines and is used for reading output signals of the corresponding plurality of bit control lines when the connection relation of any one layer of the first metal layer or the second metal layer is changed, and forming a version number after chip modification.
Preferably, the first metal layer includes the same number of first version control circuits as the bit control lines, and the logic high level signal or the logic low level signal is transmitted along a path of the first version control circuits;
the second metal layer includes the same number of second version control circuits as the bit control lines, and the logic low level signal or the logic high level signal is transmitted along a path of the second version control circuits.
Preferably, a bottom metal layer in the first metal layer is connected to an output end of an N-type field effect transistor, and the N-type field effect transistor is used for outputting a logic low level signal;
the bottom metal layer in the second metal layer is connected with the output end of a P-type field effect transistor, and the P-type field effect transistor is used for outputting a logic high level signal.
Preferably, each bit control line is connected to a top metal layer of the first metal layer or the second metal layer of the corresponding bit, respectively.
Preferably, the number of the second metal layers and the first metal layers are the same.
Preferably, the first metal layer and the first metal layer are 6 layers respectively.
Preferably, the number of the bit control lines is 16, and the corresponding chip version number is 16 bits.
Preferably, the output module is a universal digital interface, and the universal digital interface reads the corresponding plurality of bit control lines in sequence and outputs the version number modified by the chip.
The invention also provides a chip version number control method for controlling the chip version number control structure, which is used for respectively modifying the metal layer corresponding to at least one bit in the chip version number, and specifically comprises the following steps:
breaking one of the metal layers in one region into three parts;
the portion connected to the top metal layer of the three portions of the metal layer that are disconnected is switched to the metal layer of the same layer of the other region.
Preferably, one of the disconnected metal layers is any one of the first metal layer or the second metal layer.
The technical scheme of the invention has the beneficial effects that:
in the invention, the traditional register is replaced by arranging a plurality of bit control lines and a switching control module, and the chip version number can be arbitrarily changed by the switching control module to update, store and manage the chip version number.
Drawings
FIG. 1 is a schematic diagram of a chip version number control structure according to the present invention;
FIG. 2 is a schematic diagram of a structure of an embodiment of the invention when the 3 rd metal layer of the chip is modified;
fig. 3 is a schematic structural diagram of another embodiment of the present invention when the 6 th metal layer of the chip is modified.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention provides a chip version number control structure and a method, which belong to the field of chip version design, and as shown in fig. 1, the chip version number control structure comprises:
the first area comprises a plurality of first metal layers (MA 1, MA2, MA3, MA4, MA5 … MAn) which are sequentially stacked, and a through hole layer (V11, V12, V13, V14 …) is arranged between two adjacent first metal layers;
the second area comprises a plurality of second metal layers (MB 1, MB2, MB3, MB4 and MB5 … MBn) which are sequentially stacked, a through hole layer (V21, V22, V23 and V24 …) is arranged between two adjacent second metal layers, and logic level signals flowing in the first metal layers and the second metal layers are different;
the plurality of bit control lines are respectively connected with one of the first metal layers or one of the second metal layers, and the number of the bit control lines is the same as the number of bits of the chip version number;
a switching control module (not shown) for disconnecting one of the metal layers of one region and switching the disconnected metal layer to the same metal layer of the other region;
and an output module (not shown in the figure) connected with the plurality of bit control lines for reading the output signals of the corresponding plurality of bit control lines and forming the modified version number of the chip when the connection relation of any one of the first metal layer or the second metal layer is changed.
Specifically, the chip comprises a first area and a second area, the first area and the second area respectively comprise a plurality of metal layers which are sequentially stacked from top to bottom, a through hole layer is arranged between two adjacent metal layers, logic level signals flow along the metal layers and the through hole layer, logic level signals flowing in the first metal layer in the first area and logic level signals flowing in the second metal layer in the second area are different, and if the first metal layer is connected with a logic high level signal, the second metal layer is connected with a logic low level signal; if the first metal layer is connected with the logic low level signal, the second metal layer is connected with the logic high level signal;
further, the device further includes a plurality of bit control lines, the number of the bit control lines is the same as the number of bits of the chip version number, each bit control line is connected to a metal layer through which a corresponding logic level signal flows, for example, in this embodiment, the chip version number is 16 bits, and there are 16 bit control lines, hereinafter, a first metal layer is connected to a logic high level signal, a second metal layer is connected to a logic low level signal, and assuming that the chip version number is "0000 0000 0000 0001", the bit control line with the lowest number of bits is connected to the first metal layer, and the rest bit control lines are connected to the second metal layer.
Further, the switching control module is further included, and is configured to disconnect one metal layer of the first area (second area), and switch and connect the disconnected metal layer to the metal layer of the same layer of the second area (first area), as shown in fig. 2, for example, disconnect MA3 in the first area, that is, disconnect the connection between the via layers V12 and V13, divide the metal layer MA3 into 3 parts, that is, an upper layer (that is, a part connected to the top metal layer MAn), a middle layer, and a lower layer (that is, a part connected to the bottom metal layer MA 1), connect the upper layer of the disconnected MA3 to the metal layer MB3 of the second area, where, because the initial state of the bit control line itself is 1, after the bit control line is switched, the bit control line switches from the output of the main, the upper layer main … MA3, MB3, V22, MB2, MB 21, and MB1 to a logic low level signal, that is, after the bit control line is switched, a transition from 1 to 0 is implemented, and a transition from 1 to 0 is not consistent with the first bit control line to 0;
further, the device also comprises an output module, which can be any general digital interface of the chip, is connected with a plurality of bit control lines, and is used for changing logic level signals flowing to the bit control lines when the connection relation of any first metal layer or second metal layer is changed, namely reading the output signals of the corresponding plurality of bit control lines and forming a modified version number of the chip.
As a preferred embodiment, the universal digital interface reads the corresponding plurality of bit control lines in sequence and outputs the version number after the chip modification.
As a preferred embodiment, the first metal layer includes the same number of first version control circuits as the bit control lines, and a logic high level signal or a logic low level signal is transmitted along a path of the first version control circuits;
the second metal layer includes the same number of second version control circuits as the bit control lines, and a logic low level signal or a logic high level signal is transmitted along a path of the second version control circuits.
Specifically, the metal layers include version control circuits, the logic level signals are transmitted along the version control circuits in the metal layers, and the first metal layer is connected with the logic high level signals, and the second metal layer is connected with the logic low level signals.
As a preferred embodiment, the bottom metal layer in the first metal layer is connected to an output end of an N-type field effect transistor NMOS, and the N-type field effect transistor NMOS is used for outputting a logic low level signal;
the bottom metal layer in the second metal layer is connected with the output end of a P-type field effect transistor (PMOS) which is used for outputting a logic high level signal;
similarly, a bottom metal layer in the first metal layer is connected with the output end of the P-type field effect transistor PMOS and is used for transmitting a logic high level signal;
the bottom metal layer in the second metal layer is connected with the output end of the N-type field effect transistor NMOS and is used for transmitting a logic low level signal.
As a preferred embodiment, each bit control line is connected to a top metal layer of the first metal layer or the second metal layer, respectively, of the corresponding bit.
Specifically, in this embodiment, taking the first metal layer connected to the logic high level signal and the second metal layer connected to the logic low level signal as an example, if the state of the bit control line corresponding to the bit is 1, the bit control line is connected to the version control circuit of the corresponding bit in the top metal layer of the first metal layer; if the state of the bit control line corresponding to the bit is 0, the bit control line is connected with the version control circuit of the corresponding bit in the top metal layer of the second metal layer.
As a preferred embodiment, the number of the second metal layers and the number of the first metal layers are the same, and preferably, in this embodiment, the first metal layers and the first metal layers are 6 layers, respectively.
As a preferred embodiment, the number of bit control lines is 16, and the corresponding chip version number is 16 bits.
The invention also provides a chip version number control method for controlling the chip version number control structure, which is used for respectively modifying the metal layer corresponding to at least one bit in the chip version number, and specifically comprises the following steps:
breaking one metal layer in one area into three parts;
the portion of the three portions of the disconnected metal layer connected to the top metal layer is switched to the metal layer of the same layer connected to another region.
In a preferred embodiment, one of the disconnected metal layers is either the first metal layer or the second metal layer.
Specifically, in this embodiment, taking the first metal layer and the first metal layer as 6 layers as examples, the bit control line is connected to the output end of MA6 in the first area, that is, the initial state is 1;
as shown in fig. 3, MA6 in the first area is disconnected, that is, the connection between the metal layers MA6 and V15 is disconnected, the metal layer MA6 is divided into an upper layer (that is, a portion connected to output), a middle layer, and a lower layer (that is, a portion connected to the bottom metal layer MA 1), the upper layer of the disconnected MA6 is connected to the metal layer MB6 in the second area, after switching, the bit control lines are switched from output ends output, upper layer, MB6, V25, MB5, V24, MB4, V23, MB3, V22, MB2, V21, and MB1 of the MA6 to logic low level signals, that is, after the bit control lines are switched, a switching from 1 to 0 is implemented, and a switching principle of each bit control line from 1 to 0 or from 0 to 1 is consistent with the above, which will not be repeated herein;
it should be noted that the process of modifying the metal layer in the present invention is to facilitate understanding, and the present invention can directly obtain the version number of the chip through a plurality of bit control lines after the metal layer is modified, i.e. after the version is changed.
The technical scheme of the invention has the beneficial effects that:
in the invention, the traditional register is replaced by arranging a plurality of bit control lines and a switching control module, and the chip version number can be arbitrarily changed by the switching control module to update, store and manage the chip version number.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A chip version number control structure, characterized by comprising:
the first area comprises a plurality of first metal layers which are sequentially stacked, and a through hole layer is arranged between two adjacent first metal layers;
the second area comprises a plurality of second metal layers which are sequentially stacked, a through hole layer is arranged between two adjacent second metal layers, and logic level signals flowing in the first metal layers and the second metal layers are different;
a plurality of bit control lines, wherein the bit control lines are respectively connected with one of the first metal layers or one of the second metal layers, and the number of the bit control lines is the same as the number of bits of the chip version number;
the switching control module is used for disconnecting one metal layer of one area and switching and connecting the disconnected metal layer to the metal layer of the same layer of the other area;
and the output module is connected with the plurality of bit control lines and is used for reading output signals of the corresponding plurality of bit control lines when the connection relation of any one layer of the first metal layer or the second metal layer is changed, and forming a version number after chip modification.
2. The chip version number control structure of claim 1 wherein said first metal layer comprises as many first version control circuits as said bit control lines, a logic high level signal or a logic low level signal being transmitted along a path of said first version control circuits;
the second metal layer includes the same number of second version control circuits as the bit control lines, and a logic low level signal or a logic high level signal is transmitted along a path of the second version control circuits.
3. The chip version number control structure of claim 1, wherein a bottom metal layer of the first metal layer is connected to an output terminal of an N-type field effect transistor, and the N-type field effect transistor is configured to output a logic low level signal;
the bottom metal layer in the second metal layer is connected with the output end of a P-type field effect transistor, and the P-type field effect transistor is used for outputting a logic high level signal.
4. The chip version number control structure of claim 1, wherein each bit control line is connected to a top metal layer of the first metal layer or the second metal layer, respectively, of a corresponding bit.
5. The chip version number control structure of claim 1, wherein the number of the second metal layers and the number of the first metal layers are the same.
6. The chip version number control structure of claim 1, wherein the first metal layer and the first metal layer are 6 layers respectively.
7. The chip version number control structure of claim 1, wherein the number of bit control lines is 16, and the corresponding chip version number is 16 bits.
8. The chip version number control structure of claim 1, wherein the output module is a universal digital interface, and the universal digital interface reads the corresponding plurality of bit control lines in sequence and outputs the version number modified by the chip.
9. A chip version number control method for controlling a chip version number control structure according to any one of claims 1 to 8, characterized in that the modification of the metal layer corresponding to at least one bit in the chip version number comprises:
breaking one of the metal layers in one region into three parts;
the portion connected to the top metal layer of the three portions of the metal layer that are disconnected is switched to the metal layer of the same layer of the other region.
10. The method of claim 9, wherein one of the metal layers is any one of the first metal layer or the second metal layer.
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| CN202110524457.2A CN113380767B (en) | 2021-05-13 | 2021-05-13 | Chip version number control structure and method |
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| CN202110524457.2A CN113380767B (en) | 2021-05-13 | 2021-05-13 | Chip version number control structure and method |
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| CN113380767A CN113380767A (en) | 2021-09-10 |
| CN113380767B true CN113380767B (en) | 2024-01-12 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543190A (en) * | 2010-12-28 | 2012-07-04 | 炬力集成电路设计有限公司 | Semiconductor device, chip and bit data modifying method |
| CN102903714A (en) * | 2011-07-29 | 2013-01-30 | 瑞昱半导体股份有限公司 | Layout structure of integrated circuit and version control circuit |
| CN103503438A (en) * | 2011-05-24 | 2014-01-08 | 索尼公司 | Solid-state image pick-up device and camera system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10567683B2 (en) * | 2014-06-06 | 2020-02-18 | Rambus Inc. | Image sensor with depletion-level pixel charge transfer control |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543190A (en) * | 2010-12-28 | 2012-07-04 | 炬力集成电路设计有限公司 | Semiconductor device, chip and bit data modifying method |
| CN103503438A (en) * | 2011-05-24 | 2014-01-08 | 索尼公司 | Solid-state image pick-up device and camera system |
| CN102903714A (en) * | 2011-07-29 | 2013-01-30 | 瑞昱半导体股份有限公司 | Layout structure of integrated circuit and version control circuit |
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| CN113380767A (en) | 2021-09-10 |
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