CN113380742A - Bonding structure, polycrystalline circle three-dimensional integrated structure and preparation method thereof - Google Patents
Bonding structure, polycrystalline circle three-dimensional integrated structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims abstract description 222
- 238000000034 method Methods 0.000 claims abstract description 56
- 230000008569 process Effects 0.000 claims abstract description 40
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 36
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000011241 protective layer Substances 0.000 claims abstract description 30
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 21
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000010354 integration Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 39
- 238000010586 diagram Methods 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 239000011799 hole material Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
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- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
The invention relates to the technical field of bonding processes, in particular to a bonding structure, a polycrystalline circle three-dimensional integrated structure and a preparation method thereof. The structure comprises an upper interconnection layer, an upper protection layer, a bonding dielectric layer, a lower protection layer and a lower interconnection layer which are stacked; a through upper bonding channel is arranged in the upper protective layer; a through middle bonding channel is arranged in the bonding medium layer; a through lower bonding channel is arranged in the lower protective layer; a bonding silicide layer is arranged in a space formed by the upper bonding channel, the middle bonding channel and the lower bonding channel; the bonding silicide layer contacts the upper interconnect layer at the upper bonding via and the lower interconnect layer at the lower bonding via, respectively. According to the invention, the silicide is used for filling the bonding channel in the bonding medium layer, so that a good bonding interface can be realized through annealing treatment, the plasma treatment process is reduced, and the reliability and the process efficiency of the wafer bonding process are improved.
Description
Technical Field
The invention relates to the technical field of bonding processes, in particular to a bonding structure, a polycrystalline circle three-dimensional integrated structure and a preparation method thereof.
Background
As device dimensions continue to shrink, moore's law has been difficult to continue in two-dimensional planar structures. Three-dimensional integration technology is considered to be an effective method to continue moore's law. The wafer bonding is an important research subject, and two wafers with different structures can be combined together to form a whole by adopting a wafer bonding technology. For example, the peripheral circuit and the memory cell of the three-dimensional memory may be first completed on two wafers, and then the upper and lower wafers may be bonded to form the complete memory. And the two wafers are subjected to signal transmission through the interconnection through holes after bonding.
Because of its advantages of low resistivity, good electromigration resistance, copper metal is the main bonding via material. Copper is adopted as a bonding through hole material, multi-step plasma treatment is required before bonding, and after bonding is completed, problems are easy to occur at the interface, for example, two parts of copper do not grow together completely, more defects are left at the interface, and the problems of reliability and stability are caused.
Therefore, how to improve the reliability and the process efficiency of the wafer bonding process is a technical problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a bonding structure, a polycrystalline circle three-dimensional integrated structure and a preparation method thereof, so as to improve the reliability and the process efficiency of a wafer bonding process.
In order to achieve the above object, the embodiments of the present invention provide the following solutions:
in a first aspect, an embodiment of the present invention provides a bonding structure for multi-wafer three-dimensional integration, including: the upper interconnection layer, the upper protection layer, the bonding dielectric layer, the lower protection layer and the lower interconnection layer are stacked;
a through upper bonding channel is arranged in the upper protective layer;
a through middle bonding channel is arranged in the bonding medium layer;
a through lower bonding channel is arranged in the lower protective layer;
a bonding silicide layer is arranged in a space formed by the upper bonding channel, the middle bonding channel and the lower bonding channel; the bonding silicide layer is respectively in contact connection with the upper interconnection layer at the upper bonding channel and the lower interconnection layer at the lower bonding channel.
In one possible embodiment, the bonding silicide layer is a bonding nickel silicide layer, the upper interconnect layer is an upper nickel silicide interconnect layer, and the lower interconnect layer is a lower nickel silicide interconnect layer.
In a possible embodiment, a barrier layer is further disposed around the bonded silicide layer.
In one possible embodiment, the barrier layer includes an inner tantalum barrier layer and an outer tantalum nitride barrier layer.
In one possible embodiment, the bonding silicide layer is a bonding nickel silicide layer, the upper interconnect layer is an upper copper interconnect layer, and the lower interconnect layer is a lower copper interconnect layer.
In one possible embodiment, the upper protection layer is an upper silicon nitride protection layer, and the lower protection layer is a lower silicon nitride protection layer.
In a second aspect, an embodiment of the present invention provides a polycrystalline circular three-dimensional integrated structure, including: an upper wafer, a lower wafer and a bonding structure as described in any of the first aspects;
the upper protective layer and the upper interconnection layer are superposed on the surface of the base layer of the upper wafer;
the lower protective layer and the lower interconnect layer are stacked on a surface of the base layer of the lower wafer.
In a third aspect, an embodiment of the present invention provides a method for preparing a polycrystalline circular three-dimensional integrated structure, where the method includes:
step 11, depositing a dielectric layer on the protective layer of the wafer;
step 12, etching a bonding channel on the dielectric layer; the bonding channel penetrates through the dielectric layer and the protective layer;
step 13, filling amorphous silicon or polycrystalline silicon in the bonding channel;
step 14, depositing a bonding metal layer on the dielectric layer to enable the bonding metal layer to cover the bonding channel;
step 15, performing a first annealing process to enable the bonding metal layer to react with the amorphous silicon or the polycrystalline silicon in the bonding channel to form a silicide, removing the unreacted bonding metal layer on the upper layer, and exposing the bonding channel to manufacture a bonding interface on the dielectric layer;
step 16, obtaining a first wafer to be bonded;
step 17, repeating the steps 11 to 15 to obtain a second wafer to be bonded;
and 18, aligning and stacking the bonding channels of the first wafer and the bonding channels of the second wafer, and carrying out a second-step annealing process to bond the first wafer and the second wafer together.
In a possible embodiment, before the step 13, the method further comprises:
and depositing a barrier material in the bonding channel to manufacture a barrier layer.
In one possible embodiment, the barrier layer includes an inner tantalum barrier layer and an outer tantalum nitride barrier layer.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the invention, the silicide is used for filling the bonding channel in the bonding medium layer, so that a good bonding interface can be realized through annealing treatment, the plasma treatment process is reduced, and the reliability and the process efficiency of the wafer bonding process are improved.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a bonding structure for three-dimensional integration of multiple wafer circles provided in this embodiment;
fig. 2 is a schematic structural diagram of a three-dimensional integrated structure of a poly-circle provided in this embodiment;
FIG. 3 is a flow chart of a method for fabricating a three-dimensional integrated structure of a poly-crystal circle according to the present embodiment;
FIG. 4 is a schematic process diagram of step 11;
FIG. 5 is a schematic process diagram of step 12;
FIG. 6 is a schematic process diagram of step 13;
FIG. 7 is a schematic process diagram of step 14;
FIG. 8 is a schematic process diagram of step 15;
FIG. 9 is a schematic process diagram of step 18;
fig. 10 is a schematic process diagram of step 21.
Description of reference numerals: 101 is an upper protection layer, 102 is an upper interconnection layer, 103 is a bottom layer of an upper wafer, 201 is a lower protection layer, 202 is a lower interconnection layer, 203 is a bottom layer of a lower wafer, 300 is a bonding dielectric layer, 301 is a bonding silicide layer, 401 is a protection layer, 402 is an interconnection layer, 403 is a bottom layer, 404 is a dielectric layer, 405 is a bonding channel, 406 is a bonding metal layer, 407 is a silicide layer, 408 is a tantalum barrier inner layer, and 409 is a tantalum nitride barrier outer layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention belong to the scope of protection of the embodiments of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a bonding structure for three-dimensional integration of a poly-circle, which specifically includes: the device comprises an upper interconnection layer, an upper protection layer, a bonding dielectric layer, a bonding silicide layer, a lower protection layer and a lower interconnection layer.
In this embodiment, the upper interconnect layer and the upper protective layer are stacked on the surface of the base layer of the upper wafer, and the lower interconnect layer and the lower protective layer are stacked on the surface of the base layer of the lower wafer.
In the bonding structure, an upper interconnection layer, an upper protection layer, a bonding dielectric layer, a lower protection layer and a lower interconnection layer are sequentially stacked.
Specifically, the upper protective layer and the lower protective layer may be silicon nitride protective layers; the bonding dielectric layer can be made of silicon dioxide or a low-k material, wherein "k" in the "low-k material" is a dielectric constant to describe the electricity storage capacity of the dielectric material, and the low-k (low-k) material refers to a dielectric material with a k value lower than a set value, wherein the set value can be 2.8, that is, a dielectric material with a k value lower than 2.8 is a low-k material.
A through upper bonding channel is arranged in the upper protective layer; a through middle bonding channel is arranged in the bonding medium layer; and a through lower bonding channel is arranged in the lower protective layer.
Specifically, the upper bonding channel may be a through hole on the upper protection layer, and may also be a conductive channel on the upper protection layer, which is not limited herein; the lower bonding via may be a via hole on the lower protection layer, and may also be a conductive channel on the lower protection layer, which is not limited herein.
The upper bonding channel, the middle bonding channel and the lower bonding channel are provided with overlapping regions along the stacking direction, so that the upper bonding channel, the middle bonding channel and the lower bonding channel can form a communicating space, and a bonding silicide layer is arranged in the communicating space; the bonded silicide layer has an upper end contacting the upper interconnect layer at the upper bonding via and a lower end contacting the lower interconnect layer at the lower bonding via.
Of course, in order to reduce the process difficulty, the upper bonding channel, the middle bonding channel and the lower bonding channel can be vertically arranged in an equal width mode.
According to the embodiment of the invention, the silicide is used for filling the bonding channel in the bonding medium layer, so that a good bonding interface can be realized through annealing treatment, plasma treatment procedures are reduced, and the reliability and the process efficiency of the wafer bonding process are improved.
In practical application, the bonding silicide layer can be made of nickel silicide, even if the bonding nickel silicide layer is used as the bonding silicide layer, the upper interconnection layer can be made of nickel silicide to form an upper nickel silicide interconnection layer, and the lower interconnection layer can be made of nickel silicide to form a lower nickel silicide interconnection layer.
Of course, the material for bonding the silicide layer may be cobalt silicide, and the like, and is not limited herein.
If the upper interconnection layer and the lower interconnection layer adopt a copper interconnection structure, namely the upper copper interconnection layer is adopted as the upper interconnection layer, and the lower copper interconnection layer is adopted as the lower interconnection layer, the problem of diffusion of copper metal into the dielectric layer needs to be considered at the moment.
In order to reduce copper diffusion, the bonding silicide layer in the embodiment is wrapped and arranged with a barrier layer to prevent copper metal in the upper interconnection layer and the lower interconnection layer from diffusing into the bonding silicide layer and the bonding dielectric layer.
In order to improve the protection capability of copper diffusion, the barrier layer in the embodiment adopts a double-layer structure, specifically including a tantalum barrier inner layer and a tantalum nitride barrier outer layer which are sleeved together, so as to provide a good protection capability of copper diffusion.
Based on the same inventive concept as the method, an embodiment of the present invention further provides a polycrystalline circle three-dimensional integrated structure, as shown in fig. 2, which is a schematic structural diagram of the embodiment, and specifically includes: an upper wafer, a lower wafer, and a bonding structure as described in any of the above.
An upper protective layer and an upper interconnect layer are stacked on a surface of the base layer of the upper wafer; the lower protective layer and the lower interconnect layer are disposed on a surface of the base layer of the lower wafer.
Based on the same inventive concept as the method, an embodiment of the present invention further provides a method for manufacturing a polycrystalline circular three-dimensional integrated structure, and fig. 3 shows a flowchart of the embodiment of the method, which specifically includes the following steps.
And 11, depositing a dielectric layer on the protective layer of the wafer.
Specifically, as shown in fig. 4, which is a process diagram of the present step, the present step may adopt a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
Specifically, an interconnection layer and a protection layer are sequentially stacked on a base layer of the wafer. The interconnection layer can adopt a copper interconnection structure or a nickel silicide interconnection structure, and the protective layer can adopt a silicon nitride layer.
Specifically, the dielectric layer may be made of silicon dioxide or a low-k material, "k" in the "low-k material" is a dielectric constant to describe the electricity storage capability of the dielectric material, and the low-k (low-k) material refers to a dielectric material having a k value lower than a set value, where the set value may be 2.8, that is, a dielectric material having a k value lower than 2.8 is a low-k material.
Step 12, etching a bonding channel on the dielectric layer; the bonding channel penetrates through the dielectric layer and the protective layer.
Specifically, as shown in fig. 5, a process diagram of the step may be implemented by using photolithography and chemical etching.
Specifically, the bonding channel on the protection layer may be a through hole on the protection layer, and may also be a conductive channel on the protection layer, which is not limited herein.
And step 13, filling amorphous silicon or polycrystalline silicon in the bonding channel.
Specifically, as shown in fig. 6, the process diagram of this step can be implemented by using a silicon material filling technique.
And 14, depositing a bonding metal layer on the dielectric layer to enable the bonding metal layer to cover the bonding channel.
Specifically, as shown in fig. 7, the process diagram of this step is shown, the bonding metal layer may be a nickel metal layer, a cobalt metal layer, or the like, and the chemical vapor deposition process and/or the physical vapor deposition process may be used in this step, which is not limited herein.
Step 15, performing a first annealing process to enable the bonding metal layer to react with the amorphous silicon or the polycrystalline silicon in the bonding channel to form a silicide, removing the unreacted bonding metal layer on the upper layer, and exposing the bonding channel to manufacture a bonding interface on the dielectric layer;
specifically, as shown in fig. 8, which is a process diagram of this step, the bonding metal layer reacts with the amorphous silicon or the polysilicon in the bonding channel, and the original amorphous silicon or polysilicon is converted into a silicide to form a silicide layer.
And step 16, obtaining a first wafer to be bonded.
And step 17, repeating the steps 11 to 15 to obtain a second wafer to be bonded.
And 18, aligning and stacking the bonding channels of the first wafer and the bonding channels of the second wafer, and carrying out a second-step annealing process to bond the first wafer and the second wafer together.
Specifically, fig. 9 is a schematic process diagram of this step.
In practical application, the bonding silicide layer can be made of nickel silicide, even if the bonding nickel silicide layer is used as the bonding silicide layer, the upper interconnection layer can be made of nickel silicide to form an upper nickel silicide interconnection layer, and the lower interconnection layer can be made of nickel silicide to form a lower nickel silicide interconnection layer.
Of course, the material for bonding the silicide layer may be cobalt silicide, and the like, and is not limited herein.
If the upper interconnection layer and the lower interconnection layer adopt a copper interconnection structure, namely the upper copper interconnection layer is adopted as the upper interconnection layer, and the lower copper interconnection layer is adopted as the lower interconnection layer, the problem of diffusion of copper metal into the dielectric layer needs to be considered at the moment.
In order to reduce copper diffusion, the present embodiment further includes a step 21 before the step 13.
Step 21, depositing a barrier material in the bonding channel to manufacture a barrier layer
As shown in fig. 10, which is a schematic process diagram of this step, in order to improve the protection capability of copper diffusion, the barrier layer has a double-layer structure including an inner tantalum barrier layer and an outer tantalum nitride barrier layer.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
according to the embodiment of the invention, the silicide is used for filling the bonding channel in the bonding medium layer, so that a good bonding interface can be realized through annealing treatment, plasma treatment procedures are reduced, and the reliability and the process efficiency of the wafer bonding process are improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A bonded structure for three-dimensional integration of polycrystallme circles, comprising: the upper interconnection layer, the upper protection layer, the bonding dielectric layer, the lower protection layer and the lower interconnection layer are stacked;
a through upper bonding channel is arranged in the upper protective layer;
a through middle bonding channel is arranged in the bonding medium layer;
a through lower bonding channel is arranged in the lower protective layer;
a bonding silicide layer is arranged in a space formed by the upper bonding channel, the middle bonding channel and the lower bonding channel; the bonding silicide layer is respectively in contact connection with the upper interconnection layer at the upper bonding channel and the lower interconnection layer at the lower bonding channel.
2. The bonding structure of claim 1, wherein the bonding silicide layer is a bonding nickel silicide layer, the upper interconnect layer is an upper nickel silicide interconnect layer, and the lower interconnect layer is a lower nickel silicide interconnect layer.
3. The bonded structure of claim 1, wherein a barrier layer is further disposed around the bonded silicide layer.
4. The bonded structure of claim 3 wherein the barrier layer comprises a nested inner tantalum barrier layer and an outer tantalum nitride barrier layer.
5. The bonded structure of claim 3 or 4 wherein the bonded silicide layer is a bonded nickel silicide layer, the upper interconnect layer is an upper copper interconnect layer, and the lower interconnect layer is a lower copper interconnect layer.
6. The bonding structure of any of claims 1 to 4, wherein the upper protective layer is an upper silicon nitride protective layer and the lower protective layer is a lower silicon nitride protective layer.
7. A polycrystallme circle three-dimensional integrated structure, comprising: an upper wafer, a lower wafer and a bonding structure according to any one of claims 1 to 6;
the upper protective layer and the upper interconnection layer are superposed on the surface of the base layer of the upper wafer;
the lower protective layer and the lower interconnect layer are stacked on a surface of the base layer of the lower wafer.
8. A method for preparing a polycrystalline round three-dimensional integrated structure is characterized by comprising the following steps:
step 11, depositing a dielectric layer on the protective layer of the wafer;
step 12, etching a bonding channel on the dielectric layer; the bonding channel penetrates through the dielectric layer and the protective layer;
step 13, filling amorphous silicon or polycrystalline silicon in the bonding channel;
step 14, depositing a bonding metal layer on the dielectric layer to enable the bonding metal layer to cover the bonding channel;
step 15, performing a first annealing process to enable the bonding metal layer to react with the amorphous silicon or the polycrystalline silicon in the bonding channel to form a silicide, removing the unreacted bonding metal layer on the upper layer, and exposing the bonding channel to manufacture a bonding interface on the dielectric layer;
step 16, obtaining a first wafer to be bonded;
step 17, repeating the steps 11 to 15 to obtain a second wafer to be bonded;
and 18, aligning and stacking the bonding channels of the first wafer and the bonding channels of the second wafer, and carrying out a second-step annealing process to bond the first wafer and the second wafer together.
9. The method of claim 8, wherein prior to step 13, the method further comprises:
and depositing a barrier material in the bonding channel to manufacture a barrier layer.
10. The method of claim 9, wherein the barrier layer comprises an inner tantalum barrier layer and an outer tantalum nitride barrier layer.
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| US20040056329A1 (en) * | 2002-09-25 | 2004-03-25 | Maiz Jose A. | Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement |
| CN102651335A (en) * | 2011-02-28 | 2012-08-29 | Nxp股份有限公司 | A biosensor chip and a method of manufacturing the same |
| CN109964313A (en) * | 2019-02-11 | 2019-07-02 | 长江存储科技有限责任公司 | Bonding semiconductor structure and forming method thereof with the bonding contacts made of indiffusion conductive material |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040056329A1 (en) * | 2002-09-25 | 2004-03-25 | Maiz Jose A. | Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement |
| CN102651335A (en) * | 2011-02-28 | 2012-08-29 | Nxp股份有限公司 | A biosensor chip and a method of manufacturing the same |
| CN109964313A (en) * | 2019-02-11 | 2019-07-02 | 长江存储科技有限责任公司 | Bonding semiconductor structure and forming method thereof with the bonding contacts made of indiffusion conductive material |
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