CN113377597A

CN113377597A - Simulation system and method for storing and reading simulation data

Info

Publication number: CN113377597A
Application number: CN202110722201.2A
Authority: CN
Inventors: 张玉田
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2021-09-10
Anticipated expiration: 2041-06-28
Also published as: CN113377597B

Abstract

The embodiment of the disclosure provides a simulation system and a method for storing and reading simulation data, wherein the simulation system comprises: a host; the system comprises a plurality of hardware simulators in communication connection with a host, wherein the plurality of hardware simulators comprise a first hardware simulator and a second hardware simulator; a storage system communicatively coupled to the host and the plurality of hardware emulators, respectively; the first hardware emulator is configured to: acquiring a designed first module from a host, performing hardware simulation on the first module to obtain first simulation data, and transmitting the first simulation data to a storage system; the second hardware emulator is configured to: acquiring a designed second module from the host, performing hardware simulation on the second module to obtain second simulation data, and transmitting the second simulation data to the storage system; the storage system is configured to: the first simulation data and the second simulation data are received and stored in a first storage unit of the storage system. The embodiment of the disclosure can completely store simulation data, so that the hardware simulation process is continuously performed.

Description

Simulation system and method for storing and reading simulation data

Technical Field

The embodiment of the disclosure relates to the technical field of logic system design, in particular to a simulation system and a method for storing and reading simulation data.

Background

The logic System design (abbreviated as "design") refers to a design for a Circuit such as an ASIC (Application Specific Integrated Circuit) or an SOC (System-On-Chip). Design is typically done through a specialized HDL (Hardware Description Language). The design may be characterized layer by layer using HDL such that a circuit structure of complex design can be represented using a series of modules.

In hardware simulation of a design, a hardware simulator may generate simulation data. At this time, it is necessary to provide a simulation data storage scheme to ensure that the simulation data can be completely stored.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a simulation system and a method for storing and reading simulation data, so as to ensure that the simulation data can be completely stored.

In order to achieve the above object, the embodiments of the present disclosure provide the following technical solutions.

In a first aspect, an embodiment of the present disclosure provides a simulation system, including: a host; a plurality of hardware emulators in communication connection with the host computer, wherein the plurality of hardware emulators comprises a first hardware emulator and a second hardware emulator; and a storage system communicatively coupled to the host and the plurality of hardware emulators, respectively, wherein the first hardware emulator is configured to: acquiring a designed first module from a host, performing hardware simulation on the first module to obtain first simulation data, and transmitting the first simulation data to a storage system; the second hardware emulator is configured to: acquiring a designed second module from the host, performing hardware simulation on the second module to obtain second simulation data, and transmitting the second simulation data to the storage system; the storage system is configured to: the method includes receiving first emulation data and second emulation data, and storing the first emulation data and the second emulation data to a first memory location in a memory system.

In a second aspect, an embodiment of the present disclosure provides a method for storing simulation data, including:

downloading a first module of a design from a host;

performing hardware simulation on the first module to obtain first simulation data of a first hardware simulator;

the first emulation data is transmitted to a storage system communicatively coupled to a plurality of hardware emulators, including the first hardware emulator, such that the first emulation data is stored to a first storage location in the storage system.

In a third aspect, an embodiment of the present disclosure provides a method for reading emulation data, including:

acquiring a data reading instruction transmitted by a host, wherein the data reading instruction is used for reading simulation data of a first hardware simulator, the simulation data comprises first simulation data, the first simulation data is stored in a first storage unit of a storage system, the storage system is in communication connection with a plurality of hardware simulators, and the hardware simulators comprise the first hardware simulator; and

in response to the data read instruction, a command is transmitted to the storage system, the command instructing at least the storage system to transmit the first emulation data in the first storage unit to the host.

The simulation system provided by the embodiment of the disclosure is provided with the storage system, and the storage system is respectively in communication connection with the host and the hardware simulators. For any hardware simulator in the plurality of hardware simulators, if the hardware simulator performs hardware simulation on the designed module and obtains simulation data, the hardware simulator can transmit the simulation data to the storage system. Therefore, the storage system can receive the simulation data generated by the hardware simulators and store the simulation data generated by the hardware simulators into the first storage unit in the storage system, so that the simulation data of the hardware simulators can be uniformly stored. Because the storage capacity of the hardware simulator is limited and limited by the space of the verification board, the hardware simulator is difficult to expand the storage capacity of the hardware simulator, so the hardware simulator does not always have enough capacity to completely store simulation data, and the simulation process of the hardware simulator is very easy to interrupt. According to the embodiment of the disclosure, the storage system in communication connection with the hardware simulators is arranged, and the simulation data generated by the hardware simulators are uniformly stored in the first storage unit of the storage system, so that the simulation data generated by the hardware simulators can be completely stored when the storage capacity of the hardware simulators is not enough to store the simulation data. The simulation system provided by the embodiment of the disclosure can ensure that the hardware simulation process is not interrupted because the simulation data cannot be completely stored, so that the hardware simulation process can be continuously performed.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a simulation system.

FIG. 2 is a schematic diagram of a hardware simulation of the simulation system implementation design of FIG. 1.

Fig. 3 is a schematic diagram of a simulation system provided in the embodiment of the present disclosure.

Fig. 4A is a schematic diagram of a hardware simulation for implementing a design provided in the embodiment of the present disclosure.

Fig. 4B is another schematic diagram of a hardware simulation for implementing a design provided by the embodiment of the present disclosure.

Fig. 5A is a schematic diagram of reading emulation data according to an embodiment of the disclosure.

Fig. 5B is another schematic diagram of reading emulation data according to an embodiment of the present disclosure.

Fig. 5C is a further schematic diagram of reading emulation data according to an embodiment of the present disclosure.

FIG. 6 is a flowchart of a method for storing simulation data according to an embodiment of the present disclosure.

Fig. 7 is a flowchart of a method for reading emulation data according to an embodiment of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The simulation design is mainly divided into two categories of software simulation and hardware simulation. Software emulation is the simulation of a design on a host computer running a software emulation tool to verify the functionality of the design. Hardware simulation is the simulation of a design by a verification board connected to a host to verify the function of the design. The disclosed embodiments mainly explore the hardware simulation of the design.

FIG. 1 schematically illustrates an alternative schematic of a simulation system 100. Simulation system 100 may implement hardware simulations of a design. As shown in FIG. 1, the simulation system 100 may include: a host computer 110 and a verification board 120. Host 110 is communicatively coupled to authentication board 120. The number of the authentication plate 120 may be one or more.

As further shown in fig. 1, host 110 may include: a processor 111, a memory 112, a network interface 113, a peripheral interface 114, and a bus 115. The processor 111, the memory 112, the network interface 113, and the peripheral interface 114 are communicatively connected to each other inside the host through a bus 115.

Processor 111 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. In the disclosed embodiment, processor 111 may be used to perform editing of a design and to divide the edited design into a plurality of modules. In some embodiments, processor 111 may also include multiple processors integrated into a single logic component. As shown in fig. 1, the processor 111 may include a plurality of processors 111a, 111b, and 111 c.

The memory 112 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In the field of software simulation of a design, the software simulation tool may be a computer program stored in memory 112. In the field of hardware simulation of a design, a compiler that compiles the design may be a computer program stored in memory 112. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., for implementing design compilation) as well as data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 111 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 112 may include volatile memory devices or nonvolatile memory devices. In some embodiments, the memory 112 may include Random Access Memory (RAM), Read Only Memory (ROM), optical disks, magnetic disks, hard disks, Solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 113 may be configured to provide communications with other external devices to the host 110 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, the network interface may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

Peripheral interface 114 may be configured to connect host 110 with one or more peripheral devices to enable input and output of information. For example, the peripheral devices may include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

The bus 115 may be configured to transfer information between various components of the host 110 (e.g., the processor 111, the memory 112, the network interface 113, and the peripheral interface 114), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), and so forth.

It should be noted that although the host architecture only shows the processor 111, the memory 112, the network interface 113, the peripheral interface 114 and the bus 115, in a specific implementation, the host architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will appreciate that the above-described host architecture may also include only the components necessary to implement the embodiments of the present disclosure, and need not include all of the components shown in the figures.

As further shown in fig. 1, the verification board 120 may include: an FPGA (Field Programmable Gate Array) 121 and a communication interface 122. One verification board 120 may have one or more FPGAs 121 therein, and the verification board 120 connected to the host 110 may be one or more. In some embodiments, an FPGA socket may be provided in the verification board 120, and the FPGA 121 may be plugged into the FPGA socket. For example, one verification board 120 may be provided with one or more FPGA slots, one FPGA slot being plugged into one FPGA 121.

The FPGA 121 in the verification board 120 may be configured to perform hardware simulation on the designed module. An FPGA 121 is usually accompanied by a storage unit 123 for storing simulation data generated by the FPGA 121 itself. One FPGA 121 may emulate one or more modules of a design.

The communication interface 122 may be configured to enable a communication connection between the FPGA 121 and the host 110. The communication interface 122 may be connected to any one of the network interface 113, the peripheral interface 114, and the bus 115 (e.g., an external bus) of the host 110 to enable communication connection of the FPGA 121 with the host 110. In some embodiments, the communication interface 122 may be a serial communication interface (e.g., an RS-232 serial communication interface, etc.).

It should be noted that, although the above-mentioned verification board architecture only shows the FPGA 121, the communication interface 122 and the storage unit 123 disposed in the FPGA, in a specific implementation process, the verification board architecture may further include other components necessary for achieving normal operation. Furthermore, it will be understood by those skilled in the art that the above-described verification board architecture may also include only the components necessary to implement the embodiments of the present disclosure, and not necessarily all of the components shown in the figures.

In the field of hardware simulation of a design, the host computer 110 may compile the design using a compiler and then hardware simulate the design by the FPGA in the verification board 120. The compiler may be a computer program running on the host 110 shown in fig. 1.

FIG. 2 shows an alternative schematic diagram of simulation system 100 implementing hardware simulation of a design. As shown in fig. 1 and 2, the simulation system 100 may include: compiler 210, segmenter 220, FPGA230, and FPGA 240. Compiler 210 and segmenter 220 may be computer programs running on host 110. The

FPGAs

230 and 240 may be any two FPGAs disposed on the same verification board 120, or may be any two FPGAs disposed on different verification boards. The FPGA230 itself has a storage unit 231 attached thereto, and the FPGA240 itself has a storage unit 241 attached thereto.

Compiler 210 may generate object code based on the computer code to be compiled. The computer code to be compiled may also be referred to as source code, such as written design 250. Typically, the source language in which the source code is written is a high level programming language. The high-level programming language may be, for example, a software programming language such as C + +, Java, or a hardware description language such as VHDL, Verilog, systemveilog. The object code may be, for example, assembly code, machine code, a netlist, etc. In the embodiments of the present disclosure, the object code is described by taking a machine code as an example, but those skilled in the art will understand that the machine code in the embodiments of the present application may be replaced by other types of object codes. Generally, compiler 210 may be stored in memory 112 shown in FIG. 1 and executed by processor 111 to compile design 250 into object code.

Segmenter 220 may segment the compiled design (i.e., the object code of the design, such as a netlist) into a plurality of modules 251 through 25n of the design. Segmenter 220 may be stored in memory 112 shown in fig. 1 and executed by processor 111 to segment a compiled design into multiple modules.

After the divider 220 divides the compiled design into a plurality of modules 251 to 25n, the host 110 may allocate the modules 251 to 25n to a plurality of FPGAs according to a certain allocation strategy for hardware simulation. For example, host 110 may randomly assign modules 251 through 25n to multiple FPGAs. One FPGA can perform hardware emulation of one or more assigned modules. As shown in fig. 2, host 110 may assign at least module 251 to FPGA230 and at least module 252 to FPGA 240.

FPGA230 may perform hardware emulation of at least module 251. As shown in fig. 2, the FPGA230 may download the assigned module 251 from the host 110 and store it in the storage unit 231. Based on the module 251 stored in the storage unit 231, the FPGA230 may perform hardware simulation on the module 251 to obtain the simulation data 260. The simulation data 260 obtained by the FPGA230 may be stored in the storage unit 231.

FPGA240 can perform hardware emulation of at least module 252. As shown in FIG. 2, FPGA240 can download assigned module 252 from host 110 and store it in storage unit 241. Based on the module 252 stored in the storage unit 241, the FPGA240 may perform hardware simulation on the module 252 to obtain simulation data 270. The simulation data 270 obtained by the FPGA240 may be stored in the storage unit 241.

The hardware simulation process of other modules of the design (except for modules 251 and 252) at the assigned FPGA is the same as the process described above for FPGA230 simulating module 251 and FPGA240 simulating module 252 in fig. 2. It can be seen that the FPGA of the simulation design stores the obtained simulation data in its own attached storage unit (for example,

FPGAs

230 and 240 store simulation data 260 and 270 in their own attached storage units 231 and 241, respectively). However, the storage capacity of the storage unit attached to the FPGA itself is limited, and is limited by the space of the verification board, and the FPGA is difficult to expand the storage capacity of the FPGA itself, which results in a situation that when the FPGA generates simulation data with a large data volume (for example, when the FPGA debugs a module, a large amount of waveform data is generated), the storage unit attached to the FPGA itself is not enough to store the simulation data, and thus the hardware simulation process of the FPGA is interrupted.

Based on the above situation, the embodiment of the present disclosure further considers that a storage system is arranged outside the FPGA to store the simulation data generated by the plurality of FPGAs in a unified manner. FIG. 3 shows a schematic diagram of an exemplary simulation system provided by an embodiment of the present disclosure. Referring to fig. 1 and 3, the simulation system shown in fig. 3 further includes, on the basis of the simulation system 100 shown in fig. 1: a storage system 300. The storage system 300 may include: a control unit 310, a storage unit 320, and a PCI-E interface 330.

The control unit 310 is a processing device provided in the storage system 300 for performing data processing and management. In some embodiments, control unit 310 may be an FPGA. The control unit 310 in the storage system 300 can communicate with the FPGA 121 in the verification board 120 (for example, the control unit 310 and the FPGA 121 communicate with each other through FPGA-to-FPGA communication), so as to realize data transmission between the verification board 120 and the storage system 300.

The storage unit 320 is a storage device provided in the storage system 300 for storing data. In the disclosed embodiment, simulation data generated by a plurality of FPGAs may be partially or entirely stored in the storage unit 320.

The PCI-E interface 330 is an interface for communicatively connecting the storage system 300 and the host 110, and can implement data transmission between the storage system 300 and the host 110.

The storage system 300 shown in fig. 3 may be understood as a local storage system to which the host 110 is connected, and in the case where the storage system 300 is used as a local storage system, the architecture of the storage system 300 shown in fig. 3 is merely an alternative illustration. The disclosed embodiments may also support communication between the storage system 300 and the host 110 through other communication interfaces, not limited to the PCI-E interface. The embodiments of the present disclosure may also support communication between the storage system 300 and the verification board 120 through other manners, not limited to inter-FPGA communication. It should be noted that in some other embodiments, the embodiment of the present disclosure may also support the storage system 300 as a network storage system, and in the case that the storage system 300 is used as a network storage system, the storage system 300 may be communicatively connected to the verification board 120 and the host 110 through network communication.

Based on the simulation system provided by the embodiment of the disclosure, fig. 4A shows an exemplary schematic diagram of hardware simulation for implementing a design provided by the embodiment of the disclosure. The process of implementing hardware simulation of a design according to the embodiments of the present disclosure may be described as follows, with reference to fig. 2 and 4A.

For the hardware simulation process of the FPGA230 on the module 251, the FPGA230 may download the assigned module 251 from the host 110 and store the module 251 in the storage unit 231 attached thereto. The FPGA230 may perform hardware simulation on the module 251 based on the module 251 stored in the storage unit 231. The module-based hardware simulation is a continuous process, and the simulation data 260 obtained by the FPGA230 simulation module 251 may include: simulation data 261 and simulation data 262. The simulation data 261 may be generated prior to the simulation data 262. The FPGA230 may store the simulation data 261 into the storage unit 231 based on the remaining storage capacity of the storage unit 231 being sufficient to store the simulation data 261 (e.g., the remaining storage capacity of the storage unit 231 is not less than the data amount of the simulation data 261). After the storage unit 231 stores the emulation data 261, the FPGA230 may transfer the emulation data 262 to the storage system 300 based on the remaining storage capacity of the storage unit 231 being insufficient to store the emulation data 262.

In some embodiments, the FPGA230 may transmit the emulation data 262 to the memory system 300 when certain conditions are met. The specific condition may be that the remaining storage capacity of the storage unit 231 is smaller than the data amount of the simulation data 262, or that the data storage amount of the storage unit 231 reaches the storage capacity upper limit, or that the data storage amount of the storage unit 231 reaches a certain percentage of the storage capacity upper limit (e.g., 80%, 90%, etc.).

After the storage system 300 receives the simulation data 262 transmitted by the FPGA230, the control unit 310 in the storage system 300 may determine the corresponding storage partition 321 of the FPGA230 in the storage unit 320, and store the simulation data 262 in the storage partition 321 of the storage unit 320.

In some embodiments, the memory unit 320 in the memory system 300 may be provided with a plurality of memory partitions 321 to 32m, and one memory partition may be used to store simulation data generated by one FPGA in the verification board. The FPGA based on the simulation design may include

FPGAs

230 and 240, and the plurality of memory partitions may include a memory partition 321 corresponding to FPGA230 and a memory partition 322 corresponding to FPGA 240. In an alternative implementation, the storage system 300 may set a correspondence between the storage partitions and the FPGA identities. When one FPGA of the simulation design transmits simulation data to the storage system, the FPGA can carry a corresponding FPGA identification, so that the storage system can store the transmitted simulation data into a corresponding storage partition based on the carried FPGA identification. For example, the FPGA230 may carry an FPGA identification of the FPGA230 when transmitting the simulation data to the storage system, so that the storage system stores the simulation data transmitted by the FPGA230 to the corresponding storage partition 321 based on the FPGA identification of the FPGA 230.

For the hardware simulation process of the FPGA240 to the module 252, the FPGA240 may download the assigned module 252 from the host 110 and store the module 252 in the storage unit 241 attached thereto. The FPGA240 performs hardware simulation of the module 252 based on the module 252 stored in the storage unit 241. The simulation data 270 obtained by the FPGA240 simulation module 252 may include: simulation data 271 and simulation data 272. Simulation data 271 may be generated prior to simulation data 272. The FPGA240 may store the simulation data 271 into the storage unit 241 based on the remaining storage capacity of the storage unit 241 being sufficient to store the simulation data 271. After the storage unit 241 stores the simulation data 271, the FPGA240 may transmit the simulation data 272 to the storage system 300 based on the remaining storage capacity of the storage unit 241 being insufficient to store the simulation data 272.

After the storage system 300 receives the simulation data 272 transmitted by the FPGA240, the control unit 310 in the storage system 300 may determine the corresponding storage partition 322 of the FPGA240 in the storage unit 320, and store the simulation data 272 in the storage partition 322 of the storage unit 320.

The hardware simulation process of other modules of the design (except for modules 251 and 252) at the assigned FPGA is the same as that described above for the FPGA230 simulating module 251 and the FPGA240 simulating module 252 in fig. 4A. It can be seen that, when the storage unit of the FPGA of the simulation design is not enough to store the subsequently generated simulation data, the FPGA can transmit the simulation data that cannot be stored in the storage unit of the FPGA to the storage system 300 for unified storage. That is, the storage system 300 may store simulation data that the FPGA itself cannot store, and collectively store simulation data generated by a plurality of FPGAs. Under the condition of combining the simulation data stored in the storage system 300 and the simulation data stored by the FPGA, the embodiment of the disclosure can ensure that the simulation data generated by the FPGA can be completely stored, and ensure that the simulation process of the design is not interrupted because the simulation data cannot be completely stored, so that the hardware simulation process of the design can be continuously performed.

It should be noted that, because the storage system 300 is located outside the verification board and is connected to the host through communication, the storage unit 320 in the storage system 300 is not limited to the space of the verification board during capacity expansion, and the storage unit 320 in the storage system 300 can be flexibly expanded based on the data storage requirement.

In some embodiments, where the FPGA that simulates the design itself stores part of the simulation data (e.g., where the FPGA230 stores part of the simulation data 261 in the simulation data 260), embodiments of the present disclosure may optimize the means by which the host 110 allocates modules to the FPGA in order to more efficiently utilize the storage space of the FPGA's own storage cells. When the host 110 allocates modules for the FPGAs, the remaining storage capacity of each FPGA can be determined, and the data amount of simulation data generated by each module of the design can be estimated; thus, the host 110 may allocate the designed module to the FPGA according to an allocation policy that the data amount of the simulation data is positively correlated with the remaining storage capacity of the FPGA. For example, if the remaining storage capacity of the FPGA230 is larger, the host-distributed module 251 predicts larger data amount of the generated simulation data; the smaller the remaining storage capacity of the FPGA230, the smaller the amount of data the host distributed module 251 predicts the simulation data generated. That is to say, the larger the remaining storage capacity of the FPGA is, the larger the data amount of the simulation data predicted and generated by the allocated module is, so that the remaining storage capacity of the FPGA can be efficiently utilized.

FIG. 4B illustrates another exemplary diagram for implementing hardware simulation of a design provided by an embodiment of the present disclosure. The process of implementing hardware simulation of a design according to the embodiments of the present disclosure may be described as follows, with reference to fig. 2 and 4B.

For the hardware simulation process of the FPGA230 on the module 251, the FPGA230 may download the assigned module 251 from the host 110 and store the module 251 in the storage unit 231 attached thereto. The FPGA230 performs hardware simulation on the module 251 based on the module 251 stored in the storage unit 231 to obtain simulation data 260. The FPGA230 may transfer the emulation data 260 directly to the memory system 300.

After the storage system 300 receives the simulation data 260 transmitted by the FPGA230, the control unit 310 in the storage system 300 may determine the corresponding storage partition 321 of the FPGA230 in the storage unit 320, and store the simulation data 260 in the storage partition 321.

For the hardware simulation process of the FPGA240 to the module 252, the FPGA240 may download the assigned module 252 from the host 110 and store the module 252 in the storage unit 241 attached thereto. The FPGA240 performs hardware simulation on the module 252 based on the module 252 stored in the storage unit 241 to obtain simulation data 270. The FPGA240 transfers the emulation data 270 directly to the memory system 300.

After the storage system 300 receives the simulation data 270 transmitted by the FPGA240, the control unit 310 in the storage system 300 may determine the corresponding storage partition 322 of the FPGA240 in the storage unit 320, and store the simulation data 270 in the storage partition 322.

The hardware simulation process of other modules of the design (except for modules 251 and 252) at the assigned FPGA is the same as that described above for the FPGA230 simulating module 251 and the FPGA240 simulating module 252 in fig. 4B. It can be seen that the FPGA of the simulation design can directly transmit the generated simulation data to the storage system 300, so that the storage system 300 can uniformly store the simulation data generated by each FPGA. That is to say, the FPGA of the simulation design does not use its own storage unit to store the simulation data, but directly transmits the simulation data to the storage system 300 for storage, thereby reducing the occurrence of the situation that the storage capacity of the FPGA itself is not enough to store the simulation data. The embodiment of the disclosure can ensure that the simulation data generated by the FPGA can be completely stored in the storage system 300, and ensure that the simulation process of the design is not interrupted due to the fact that the simulation data cannot be completely stored, so that the hardware simulation process of the design can be continuously performed.

After a FPGA of the one or more FPGAs completes hardware simulation (e.g., after a certain FPGA completes hardware simulation on an assigned module), the host 110 may analyze simulation data generated by the FPGA, and at this time, the host 110 may transmit a data reading instruction to the FPGA, thereby triggering a simulation data reading process of the FPGA. In the implementation of reading the simulation data, based on the hardware simulation process shown in fig. 4A, the embodiment of the present disclosure further provides a corresponding simulation data reading scheme. Fig. 5A illustrates an exemplary schematic diagram of reading emulation data provided by an embodiment of the present disclosure. The process of reading emulation data provided by the embodiments of the present disclosure may be described as follows, as shown in fig. 4A and 5A.

For the emulation data reading process of the FPGA230, the host 110 may transmit a data read instruction 510 to the FPGA 230. The data instructions 510 are used to read the emulation data 260 of the FPGA 230. Since the simulation data 260 includes the simulation data 261 and the simulation data 262, and the simulation data 261 is stored in the storage unit 231 of the FPGA230 itself and the simulation data 262 is stored in the storage system 300, reading the simulation data 260 generated by the FPGA230 involves reading the simulation data 261 in the storage unit 231 and the simulation data 262 in the storage system 300.

In the embodiment of the present disclosure, after the FPGA230 receives the data reading instruction 510 transmitted from the host, the FPGA230 may generate the command 520 and transmit the emulation data 261 stored in the self storage unit 231 and the command 520 to the storage system 300. In the disclosed embodiment, the command 520 is used to instruct the storage system 300 to integrate the stored emulation data 262 of the FPGA230 with the currently transmitted emulation data 261 and feed back to the host 110.

After the storage system 300 receives the emulation data 261 and the command 520, the control unit 310 in the storage system 300 may read the emulation data 262 from the storage partition 321 of the storage unit 320 based on the command 520. The control unit 310 further integrates the simulation data 261 and the simulation data 262, and then transmits the integrated simulation data 260 to the host 110, so that the host 110 can read the simulation data of the FPGA 230. In some embodiments, the integration of the simulation data 261 and the simulation data 262 by the control unit 310 may include: the simulation data 261 and the simulation data 262 are subjected to data compression, and then the compressed data are grouped, wherein one group of data may include data of multiple bits (for example, one group of data may include data of 8 bits), and the multiple groups of data correspond to one storage unit in the storage unit (for example, 8 groups of data correspond to one storage unit of 64 bits in the storage unit).

In some embodiments, the control unit 310 may communicate with the host 110 via the PCI-E interface 330 to transmit the integrated simulation data 260 to the host 110.

The process of the host 110 reading the simulation data of the FPGA240 and the simulation data of other FPGAs is the same as the process of the host 110 reading the simulation data of the FPGA230 in fig. 5A. It can be seen that, in the case that the FPGA of the simulation design stores part of the simulation data itself and the storage system 300 stores another part of the simulation data, the FPGA can transmit part of the simulation data stored by the FPGA itself to the storage system 300, the storage system 300 integrates the part of the simulation data stored by the FPGA itself and another part of the simulation data stored in the storage system, and then the storage system 300 transmits the integrated simulation data to the host 110, so that the host 110 reads the simulation data of the FPGA.

As an alternative implementation of fig. 5A, fig. 5B illustrates another alternative schematic diagram of reading emulation data provided by the embodiment of the present disclosure. The process of reading emulation data provided by the embodiments of the present disclosure may be described as follows, as shown in fig. 4A and 5B.

In the embodiment of the present disclosure, after the FPGA230 receives the data reading instruction 510 transmitted by the host, the FPGA230 may generate the command 520 and transmit the emulation data 261 stored in the self storage unit 231 to the host 110, and simultaneously transmit the command 520 to the storage system 300. In the disclosed embodiment, the command 520 is used to instruct the storage system 300 to transmit the stored emulation data 262 of the FPGA230 to the host 110.

After the memory system 300 receives the command 520, the control unit 310 in the memory system 300 may read the emulation data 262 from the memory partition 321 of the memory unit 320 based on the command 520. The control unit 310 further transmits the emulation data 262 to the host 110.

After the host 110 receives the simulation data 261 transmitted by the FPGA230 and the simulation data 262 transmitted by the storage system 300, the simulation data 261 and the simulation data 262 may be integrated to obtain the integrated simulation data 260, so as to read the simulation data of the FPGA 230. The process of obtaining the simulation data by the host integration can be similarly described with reference to the corresponding parts in the foregoing, and is not described herein again.

The process of the host 110 reading the simulation data of the FPGA240 and the simulation data of other FPGAs is the same as the process of the host 110 reading the simulation data of the FPGA230 in fig. 5B. It can be seen that in the case where the FPGA that simulates the design stores part of the simulation data itself and the storage system 300 stores another part of the simulation data, the FPGA may transmit part of the simulation data stored by itself directly to the host 110 and instruct the storage system 300 to transmit another part of the stored simulation data to the host 110. Thus, the host can integrate a part of the simulation data transmitted by the FPGA with another part of the simulation data transmitted by the storage system 300, so as to enable the host 110 to read the simulation data of the FPGA.

In the implementation of reading the simulation data, based on the hardware simulation process shown in fig. 4B, the embodiment of the present disclosure further provides a corresponding simulation data reading scheme. FIG. 5C is a schematic diagram illustrating still another alternative for reading emulation data provided by an embodiment of the present disclosure. The process of reading the emulation data provided by the embodiment of the present disclosure may be described as follows, as shown in fig. 4B and 5C.

For the emulation data reading process of the FPGA230, the host 110 may transmit a data read instruction 510 to the FPGA 230. The data instructions 510 are used to read the emulation data 260 of the FPGA 230. Because the emulation data 260 of the FPGA230 is stored directly in the memory system 300, embodiments of the present disclosure are directed only to reading the emulation data 260 in the memory system 300.

In the disclosed embodiment, after the FPGA230 receives the data reading instruction 510 transmitted by the host, the FPGA230 may generate the command 520 and transmit the command 520 to the memory system 300. In the disclosed embodiment, the command 520 is used to instruct the storage system 300 to transmit the stored emulation data 260 of the FPGA230 to the host 110.

After the memory system 300 receives the command 520, the control unit 310 in the memory system 300 may read the emulation data 260 from the memory partition 321 of the memory unit 320 based on the command 520. Control unit 310 further transmits emulation data 260 to host 110 to enable host 110 to read the emulation data of FPGA 230.

The process of the host 110 reading the emulation data of the other FPGAs is the same as the process of the host 110 reading the emulation data of the FPGA230 in fig. 5C. It can be seen that in the case where the FPGA of the simulation design does not store simulation data, but the storage system 300 directly stores the simulation data of the FPGA, the FPGA can instruct the storage system 300 to transmit the stored simulation data to the host 110, so as to enable the host 110 to read the simulation data of the FPGA.

Based on the above described technical solution, an embodiment of the present disclosure provides a simulation system, which may include:

a host (e.g., host 110 shown in FIG. 3);

a plurality of hardware emulators communicatively coupled to the host, the plurality of hardware emulators including a first hardware emulator (e.g., FPGA230 of fig. 4A) and a second hardware emulator (e.g., FPGA240 of fig. 4A); and

a storage system (e.g., the storage system 300 shown in fig. 4A) communicatively coupled to the host and the plurality of hardware emulators, respectively, wherein,

the first hardware emulator is configured to: obtaining a first module of a design (e.g., module 251 shown in FIG. 4A) from a host, performing a hardware simulation on the first module to obtain first simulation data (e.g., simulation data 262 shown in FIG. 4A), and transmitting the first simulation data to a storage system;

the second hardware emulator is configured to: obtaining a second module of the design from the host (e.g., module 252 of FIG. 4A), hardware simulating the second module to obtain second simulation data (e.g., simulation data 272 of FIG. 4A), and transmitting the second simulation data to the storage system;

the storage system is configured to: the method includes receiving first and second emulation data, and storing the first and second emulation data to a first memory location (e.g., memory location 320 shown in FIG. 4A) in a memory system.

In further embodiments, a first storage unit in a storage system may include multiple storage partitions (e.g., storage partitions 321-32 m shown in FIG. 4A), one storage partition may store emulation data generated by a hardware emulator; the plurality of memory partitions may include a first memory partition (e.g., memory partition 321 shown in fig. 4A) and a second memory partition (e.g., memory partition 322 shown in fig. 4A). The storage system, in implementing the storing of the first emulation data and the second emulation data to the first storage unit, may be further configured to: first emulation data (e.g., emulation data 262, shown in FIG. 4A) is stored to a first memory partition, and second emulation data (e.g., emulation data 272, shown in FIG. 4A) is stored to a second memory partition.

In further some embodiments, a first hardware emulator (e.g., FPGA230 shown in fig. 4A) may include a second storage unit (e.g., storage unit 231 shown in fig. 4A). The first hardware emulator, in effecting the transfer of the first emulation data to the storage system, may be further configured to: in response to the data storage amount of the second storage unit reaching a predetermined condition, first emulation data (e.g., emulation data 262 shown in fig. 4A) is transmitted to the storage system.

In some embodiments, the data storage amount of the second storage unit reaching the predetermined condition includes any one of:

the data storage capacity of the second storage unit reaches the upper limit of the storage capacity;

the data storage capacity of the second storage unit reaches a certain percentage of the upper storage capacity, and the certain percentage is less than 1;

the remaining data capacity of the second storage unit is smaller than the data amount of the first emulation data.

In further some embodiments, based on the host reading emulation data (e.g., emulation data 260 shown in fig. 4A, 5A) of the first hardware emulator, the first hardware emulator may be further configured to: acquiring a data reading instruction (for example, the data instruction 510 shown in fig. 5A) transmitted by a host, wherein the data reading instruction is used for reading simulation data of a first hardware simulator (for example, the FPGA230 shown in fig. 5A); in response to the data read instruction, a command (e.g., command 520 shown in FIG. 5A) is transmitted to the memory system.

Based on the commands transmitted by the first hardware emulator, the storage system may be further configured to: in response to the command, at least first emulation data (e.g., emulation data 262 shown in FIG. 5A) stored in the first storage unit is transferred to the host.

In further some embodiments, the first hardware emulator simulates the first module and obtains third emulation data (e.g., emulation data 261 shown in fig. 4A and 5A), and the third emulation data is stored in a second storage unit (e.g., storage unit 231 shown in fig. 4A and 5A) in the first hardware emulator, and the second storage unit also stores the first module (e.g., module 251 shown in fig. 4A).

In some further embodiments, in the case that the first hardware emulator emulates the first module and obtains the third emulation data, the first hardware emulator, in acquiring the data reading instruction transmitted by the host, may be further configured to: and transmitting the third simulation data stored in the second storage unit to the storage system in response to the data reading instruction.

Based on the third emulation data and the command transmitted by the first hardware emulator, the storage system, when enabled to transmit at least the first emulation data stored in the first storage unit to the host, may be further configured to: in response to a command (e.g., command 520 shown in FIG. 5A), the first emulation data (e.g., emulation data 262 shown in FIG. 4A, FIG. 5A) and the third emulation data (e.g., emulation data 261 shown in FIG. 4A, FIG. 5A) are integrated, and the integrated emulation data (e.g., emulation data 260 shown in FIG. 5A) is transmitted to the host.

In some further embodiments, in the case that the first hardware emulator emulates the first module and obtains the third emulation data, the first hardware emulator, in acquiring the data reading instruction transmitted by the host, may be further configured to: and transmitting the third simulation data stored in the second storage unit to the host in response to the data reading instruction.

Based on the command transmitted by the first hardware emulator, the storage system, when implementing at least the transmission of the first emulation data stored in the first storage unit to the host, may be directly configured to: the first emulation data (e.g., emulation data 262 shown in fig. 4A, 5A) stored in the first storage unit is transmitted to the host.

Based on the third emulation data transmitted by the first hardware emulator, and the first emulation data transmitted by the storage system, the host may be further configured to: and receiving first simulation data transmitted by the storage system and third simulation data transmitted by the first hardware simulator, and integrating the first simulation data and the third simulation data.

In further embodiments, the hardware emulator referred to in the embodiments of the present disclosure may include an FPGA (e.g., FPGA 121 in verification board 120 shown in fig. 3), and the memory system may include an FPGA (e.g., control unit 310 shown in fig. 3) and a PCI-E interface; the hardware simulator and the storage system can perform data transmission through communication between the FPGA; the storage system and the host can carry out data transmission through the PCI-E interface.

The embodiment of the disclosure also provides a method for storing simulation data. FIG. 6 illustrates a flowchart of an exemplary method 600 of storing simulation data provided by an embodiment of the present disclosure. The method 600 may be performed by a hardware simulator (e.g., the FPGA230 shown in figure 4A) for simulating a design. As shown in fig. 6, the method 600 may include the following steps.

In step S610, a first module of a design (e.g., module 251 shown in fig. 4A) is downloaded from a host (e.g., host 110 shown in fig. 3).

In step S612, a hardware simulation is performed on the first module to obtain first simulation data (e.g., simulation data 262 shown in fig. 4A) of a first hardware simulator (e.g., FPGA230 shown in fig. 4A).

In step S614, the first emulation data is transmitted to a storage system (e.g., the storage system 300 shown in fig. 4A) communicatively connected to a plurality of hardware emulators, including the first hardware emulator, so that the first emulation data is stored to a first storage unit (e.g., the storage unit 320 shown in fig. 4A) in the storage system.

The specific implementation and extensible steps of the steps in the method shown in fig. 6 can refer to the related description of the simulation system part; the foregoing description regarding the FPGA230 can be considered as a description regarding the first hardware emulator.

The embodiment of the disclosure also provides a method for reading the simulation data. FIG. 7 illustrates a flowchart of an exemplary method 700 of reading emulation data provided by an embodiment of the present disclosure. The method 700 may be performed by a hardware simulator (e.g., the FPGA230 shown in figure 5A) for simulating a design. As shown in fig. 7, the method 700 may include the following steps.

In step S710, a data reading instruction (e.g., the data instruction 510 shown in fig. 5A) transmitted by a host (e.g., the host 110 shown in fig. 5A) is obtained, the data reading instruction being used to read emulation data of a first hardware emulator (e.g., the FPGA230 shown in fig. 5A), the emulation data including first emulation data (e.g., the emulation data 262 shown in fig. 5A), the first emulation data being stored in a first storage unit (e.g., the storage unit 320 shown in fig. 5A) of a storage system (e.g., the storage system 300 shown in fig. 5A), the storage system being communicatively connected with a plurality of hardware emulators, and the plurality of hardware emulators including the first hardware emulator.

In step S712, in response to the data read instruction, a command (e.g., command 520 shown in fig. 5A) is transmitted to the storage system, the command instructing at least the storage system to transmit the first emulation data in the first storage unit to the host.

The steps of the method shown in fig. 7 are specifically implemented and extensible, and reference may be made to the above description of the simulation system part; the foregoing description regarding the FPGA230 can be considered as a description regarding the first hardware emulator.

While various embodiments have been described above in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the disclosed embodiments are not to be limited to the disclosed embodiments, but on the contrary, are intended to cover various modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.

It should be noted that the computer-readable media of the present embodiments, both permanent and non-permanent, removable and non-removable, may implement any method or technology for storing information. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The foregoing description of specific embodiments of the present disclosure has been described. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A simulation system, comprising:

a host;

a plurality of hardware emulators in communicative connection with the host computer, the plurality of hardware emulators including a first hardware emulator and a second hardware emulator; and

a storage system communicatively coupled to the host and the plurality of hardware emulators, respectively, wherein,

the first hardware emulator is configured to: acquiring a first designed module from a host, performing hardware simulation on the first module to obtain first simulation data, and transmitting the first simulation data to the storage system;

the second hardware emulator is configured to: acquiring a designed second module from a host, performing hardware simulation on the second module to obtain second simulation data, and transmitting the second simulation data to the storage system;

the storage system is configured to: the first emulation data and the second emulation data are received, and the first emulation data and the second emulation data are stored to a first storage unit in the storage system.

2. The emulation system of claim 1, wherein the first storage unit comprises a plurality of storage partitions including a first storage partition and a second storage partition;

the storage system is further configured to: storing the first emulation data to the first memory partition and the second emulation data to a second memory partition.

3. The simulation system of claim 1, wherein the first hardware simulator comprises a second storage unit; the first hardware emulator is further configured to: transmitting the first emulation data to the storage system in response to the data storage amount of the second storage unit reaching a predetermined condition.

4. The simulation system of any of claims 1-3, wherein the first hardware simulator is further configured to: acquiring a data reading instruction transmitted by a host, wherein the data reading instruction is used for reading simulation data of the first hardware simulator; transmitting a command to the storage system in response to the data read instruction;

the storage system is further configured to: in response to the command, at least first emulation data stored in the first storage unit is transmitted to the host.

5. The simulation system of claim 4, wherein the first hardware simulator simulates the first module further resulting in third simulation data, the third simulation data being stored in a second storage unit in the first hardware simulator, the second storage unit further storing the first module.

6. The simulation system of claim 5, wherein the first hardware simulator is further configured to: transmitting third simulation data stored in the second storage unit to the storage system in response to the data reading instruction;

the storage system is further configured to: and responding to the command, integrating the first simulation data and the third simulation data, and transmitting the integrated simulation data to the host.

7. The simulation system of claim 5, wherein the first hardware simulator is further configured to: transmitting third simulation data stored in the second storage unit to the host in response to the data reading instruction;

the host is configured to: and receiving the first simulation data transmitted by the storage system and the third simulation data transmitted by the first hardware simulator, and integrating the first simulation data and the third simulation data.

8. The simulation system of claim 1, wherein the hardware simulator comprises an FPGA, and the storage system comprises an FPGA and a PCI-E interface; the hardware simulator and the storage system are communicated through the FPGA to carry out data transmission; and the storage system and the host carry out data transmission through a PCI-E interface.

9. A method of storing emulation data, comprising:

downloading a first module of a design from a host;

transmitting the first emulation data to a storage system communicatively coupled to a plurality of hardware emulators, including the first hardware emulator, to cause the first emulation data to be stored to a first storage location in the storage system.

10. A method of reading emulation data, comprising:

in response to the data read instruction, transmitting a command to the storage system, the command instructing at least the storage system to transmit the first emulation data in the first storage unit to the host.