CN113371674A - Wide-range pressure sensor chip and monolithic integration preparation method thereof - Google Patents

Wide-range pressure sensor chip and monolithic integration preparation method thereof Download PDF

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CN113371674A
CN113371674A CN202110593586.7A CN202110593586A CN113371674A CN 113371674 A CN113371674 A CN 113371674A CN 202110593586 A CN202110593586 A CN 202110593586A CN 113371674 A CN113371674 A CN 113371674A
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layer
silicon
soi
etching
pressure sensor
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王高峰
王明浩
程瑜华
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Hangzhou Dianzi University
Hangzhou Dianzi University Wenzhou Research Institute Co Ltd
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Hangzhou Dianzi University
Hangzhou Dianzi University Wenzhou Research Institute Co Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors

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Abstract

The invention discloses a wide-range pressure sensor chip and a monolithic integration preparation method thereof. The existing pressure sensor chip has the problems of low linearity and sensitivity and narrow measuring range. The invention relates to monolithic microfabrication of piezoresistive pressure sensors. The pressure sensor mainly comprises a vacuum chamber, a pressure sensitive membrane and a Wheatstone bridge formed by four piezoresistors. The novel silicon-polyimide composite pressure-sensitive membrane can increase the measurement range of the pressure sensor by increasing the membrane thickness, and can improve the sensitivity and the linearity of the pressure sensor by combining the rigidity and the flexibility. When the external pressure changes, the common deformation of the silicon film and the polyimide film causes the resistance value of the piezoresistance to change and causes the output voltage of the Wheatstone bridge to change.

Description

Wide-range pressure sensor chip and monolithic integration preparation method thereof
Technical Field
The invention belongs to the technical field of MEMS sensors, and particularly relates to a monolithic integration preparation method for a wide-range pressure sensor chip.
Background
With the development of silicon-based micromachining technology, silicon-based pressure sensors have been well developed and widely used in industrial and commercial applications. In recent years, with the expansion of electronic device markets such as automobiles, aerospace, biomedical, internet of things, portable electronic devices and the like, the development of a monolithic integrated silicon-based micro-pressure sensor chip with multiple functions, high reliability, low cost and large-scale manufacturing capability becomes a hot spot of the current consumption market.
Jianan Dong et al at Zhejiang university, in the paper "Monolithic-integrated pixel-responsive MEMS accelerometric sensor with glass-silicon-glass discovery channel structure", developed a novel Monolithic composite MEMS sensor. The composite sensor integrates a piezoresistive pressure sensor and a piezoresistive accelerometer on a chip. The multi-sensor chip of the sandwich structure is prepared by adopting a batch micro-processing technology and an anodic bonding technology. Wherein, the pressure sensor adopts a rectangular sensitive membrane structure. The pressure sensing diaphragm of the pressure sensor is etched using a single mask. And carrying out anodic bonding by adopting Pyrex7740 glass and the silicon layer on the back surface to form a vacuum chamber of the pressure sensor. The groove is designed and manufactured around the bonding area on the front surface of the wafer to ensure the electric conduction between the LPCVD amorphous silicon layer and the silicon substrate, and the piezoresistance can be protected from the P-N junction breakdown in the anodic bonding process. However, the sensitive film in such a pressure sensor chip is prepared by wet etching, and the repeatability and consistency thereof are difficult to ensure, which is not favorable for mass production. Finally, the pressure measurement range of the pressure sensor is small, and the pressure sensor is difficult to adapt to pressure detection in a high-pressure environment.
Disclosure of Invention
Aiming at the defects in the prior art, the invention uses an SOI (silicon on insulator) silicon wafer as a substrate of a sensor and realizes the accurate control of the thickness of a pressure sensitive film by a buried oxide layer etching stopping technology; the silicon-PI composite pressure sensitive film structure is formed by spin-coating a Polyimide (PI) thin film on a silicon film. The novel silicon-PI composite pressure-sensitive membrane can increase the measurement range of the pressure sensor by increasing the membrane thickness on one hand, and can improve the sensitivity and the linearity of the pressure sensor by combining the rigidity and the flexibility on the other hand.
The invention relates to a wide-range pressure sensor chip, which comprises a back glass layer, an SOI bottom silicon layer, an SOI buried oxide layer, an SOI top silicon layer and a polyimide passivation layer which are sequentially stacked from bottom to top, wherein the back glass layer, the SOI bottom silicon layer, the SOI buried oxide layer, the SOI top silicon layer and the polyimide passivation layer jointly form a sensor chip structure; the back glass layer and the SOI bottom silicon layer are bonded together through an anodic bonding process, and a vacuum chamber of the pressure sensor is formed; the SOI top silicon layer and the polyimide passivation layer jointly form a pressure sensitive membrane. The four piezoresistors distributed on the SOI top silicon layer form a Wheatstone bridge structure. When the external pressure changes, the deformation of the pressure sensitive membrane causes the resistance values of the four piezoresistors to change and leads to the change of the output voltage of the Wheatstone bridge structure. The magnitude of the external pressure is calculated by detecting the magnitude of the output voltage.
Preferably, the piezoresistance in the SOI top silicon layer is formed from low concentration boron doped silicon. Before the back glass layer and the SOI bottom silicon layer are bonded through an anodic bonding process, a layer of metal aluminum is sputtered on the edge of the SOI silicon wafer through high power to form a conductive path between the front side and the back side of the SOI silicon wafer, so that failure or breakdown piezoresistance in the anodic bonding process is avoided.
Preferably, the interconnection lines between the piezoresistors are made of evaporated aluminum, and conduction is achieved by ohmic contact between the aluminum and the doped silicon.
Preferably, the piezoresistance has a length and width of 250 microns and 20 microns, respectively. The four piezoresistors are respectively piezoresistors R1, R2, R3 and R4 which are sequentially arranged; the distance between the pressure resistor R1 and the pressure resistor R2 and the distance between the pressure resistor R3 and the pressure resistor R4 are both 140 micrometers; the piezoresistor R2 is spaced 50 microns from the piezoresistor R3. The length, width and thickness of the SOI top silicon layer are 900, 450 and 50 microns respectively.
The monolithic integration preparation method of the wide-range pressure sensor chip comprises the following specific steps:
s1: the SOI is used as a substrate, and four piezoresistors, a bonding pad, an interconnection line and a plane structure of a passivation layer are formed by utilizing micro-processing technologies such as photoetching, ion implantation, plasma enhanced chemical vapor deposition, reactive ion etching, spin coating, evaporation deposition, wet etching, stripping and the like;
s2: and forming a vacuum chamber of the pressure sensor by adopting double-sided alignment photoetching, back deep silicon etching, RIE (reactive ion etching) for etching the buried oxide layer and back silicon-glass anodic bonding process.
Preferably, the specific process of step S1 is as follows:
1) the SOI silicon wafer is used as a substrate, and the substrate is cleaned, dried and baked.
2) Spin coating a layer of positive photoresist and carrying out photoetching and patterning to form a boron ion injection window.
3) And implanting boron ions to form the lightly doped piezoresistive structure.
4) The piezoresistive region is covered with a polyimide film, and the alignment mark is transferred to the silicon substrate by deep silicon etching.
5) Spin-coating a layer of positive photoresist and carrying out photoetching and patterning to form a secondary boron ion injection window.
6) And implanting boron ions to form heavily doped contact points and wires.
7) PECVD deposits a layer of silicon oxide.
8) Spin coating a layer of positive photoresist and carrying out photoetching and patterning to form a silicon oxide etching window.
9) RIE etches the silicon oxide to expose the ion implanted regions and the aluminum wire contacts.
10) And evaporating and depositing a layer of metallic aluminum as a conductive metal layer.
11) Spin coating a layer of positive photoresist and carrying out photoetching and patterning to form a mask for wet etching of aluminum.
12) And (5) wet etching the aluminum metal layer to form a metal interconnection line and a bonding pad.
13) And a layer of polyimide film is deposited by spin coating to be used as a polyimide passivation layer.
14) Spin coating a layer of positive photoresist and carrying out photoetching and patterning to form an etching window of the polyimide.
15) RIE etches the polyimide, exposing the window of the aluminum pad and the top silicon layer at the edge of the SOI.
16) And evaporating and depositing a layer of metallic aluminum to be used as a conductive metal layer of the SOI top layer silicon and the SOI bottom layer silicon.
Preferably, the specific process of step S1 is as follows:
1) the SOI silicon wafer is used as a substrate, and the substrate is cleaned, dried and baked.
2) A layer of silicon oxide is deposited as an insulating layer on the front side of the SOI using PECVD.
3) A layer of polysilicon is deposited as an implant layer on the front side of the SOI using LPCVD.
4) And injecting boron ions to form the lightly doped polysilicon piezoresistive structure layer.
5) And spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching and patterning to form a polysilicon etching mask. Next, four piezoresistive and alignment marks are formed on the front side of the SOI using a deep silicon etch.
6) And spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching and patterning to form a secondary boron ion implantation window.
7) And implanting boron ions to form a heavily doped contact point.
8) PECVD deposits a layer of silicon oxide.
9) And spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching and patterning to form a silicon oxide etching window.
10) RIE etches the silicon oxide to expose the ion implanted regions and the aluminum wire contacts.
11) A layer of aluminum is vapor deposited as a conductive metal layer.
12) And spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching and patterning to form a mask for wet etching aluminum.
13) And (5) wet etching the aluminum metal layer to form a metal interconnection line and a bonding pad.
14) And a layer of polyimide film is deposited by spin coating to be used as a polyimide passivation layer.
15) Spin coating a layer of positive photoresist and carrying out photoetching and patterning to form an etching window of the polyimide. Subsequently, RIE etches the polyimide, exposing the window of the aluminum pad and the top silicon layer at the edge of the SOI.
Preferably, the specific process of step S2 is as follows:
1) and spin-coating a layer of positive photoresist on the back surface of the substrate, and carrying out double-sided alignment photoetching patterning to expose the etching area.
2) RIE etches the silicon oxide and DRIE etches the silicon to the buried oxide layer.
3) RIE etches the back oxide layer and the buried oxide layer.
4) And polishing the back silicon, and then carrying out back silicon-glass anodic bonding.
5) And mechanically cutting the wafer to release the single pressure sensor chip.
The invention has the beneficial effects that:
1. the invention uses the silicon-PI composite film (namely the superposed SOI top silicon layer and the polyimide passivation layer) as the pressure sensitive film, and the pressure measuring range can be improved on the premise of ensuring the linearity and the sensitivity by combining two materials with different Young modulus.
2. According to the invention, the SOI silicon wafer is used as the substrate of the sensor, and the thickness of the pressure sensitive silicon film is accurately controlled by the buried oxide layer etching stopping technology, so that the consistency and the repeatability of the sensor are improved.
3. The invention realizes the conduction of the front and the back of the SOI by adopting a layer of metal deposited by high-power sputtering on the edge of the SOI, thereby ensuring that the voltage in the anodic bonding process can be effectively applied to a bonding interface, simultaneously avoiding the breakdown of piezoresistance and greatly improving the yield of devices.
Drawings
FIG. 1 is a schematic front view of the present invention;
FIG. 2 is a schematic cross-sectional view of the present invention;
FIG. 3 is a schematic diagram of a four piezoresistive and Wheatstone bridge configuration of the present invention;
FIG. 4 is a process flow diagram of the preparation method of the present invention;
fig. 5 is a graph showing output characteristics of the pressure sensor prepared according to the present invention at room temperature.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in FIG. 1, the front structure of a wide-range pressure sensor chip comprises four parallel piezoresistors R1(1), R2(2), R3(3) and R4(4), aluminum pads, interconnecting wires (5) and a pressure sensitive film (6) on a silicon film of a pressure sensor. The piezoresistors R1(1), R2(2), R3(3) and R4(4) form a Wheatstone full-bridge structure through aluminum interconnection lines (5). The pressure sensitive membrane (6) is mainly composed of a silicon membrane and a polyimide film, and the pressure range can be improved on the premise of ensuring the linearity by combining two materials with different Young modulus. The thickness of the silicon film in the pressure sensitive film is 40-50 microns, the thickness of the polyimide film is 5-10 microns, the length and the width of the pressure sensitive film are 0.90mm and 0.45mm respectively, and the length and the width of the piezoresistor are 0.25mm and 0.02mm respectively.
As shown in FIG. 2, the cross-sectional structure of the wide-range pressure sensor chip comprises a back anodic bonding glass layer, an SOI bottom silicon layer, an SOI buried oxide layer (9), an SOI top silicon layer (8), a polyimide passivation layer (7) and a vacuum chamber which are sequentially stacked from bottom to top to form the sensor chip structure. The back-side anodic bonding glass layer and the SOI bottom silicon layer are bonded together by an anodic bonding process to form a vacuum chamber of the pressure sensor. Wherein the SOI top silicon layer (8) is the silicon film; the polyimide passivation layer (7) is the polyimide film.
The working principle of the wide-range pressure sensor chip is as follows: when the external pressure changes, the common deformation of the silicon film and the polyimide film causes the resistance values of the four piezoresistors R1(1), R2(2), R3(3) and R4(4) to change and causes the output voltage of the bridge to change. The magnitude of the external pressure can be calculated by detecting the magnitude of the output voltage of the bridge.
The wide range pressure sensor chip is prepared using either of the following two embodiments.
Example 1
The monolithic integration preparation method of the wide-range pressure sensor chip comprises the following specific steps:
s1: the method comprises the steps that an SOI (silicon on insulator) is used as a substrate, and micro-processing technologies such as photoetching, ion implantation, Plasma Enhanced Chemical Vapor Deposition (PECVD), Reactive Ion Etching (RIE), spin coating, evaporation deposition, wet etching, stripping and the like are utilized to form plane structures such as piezoresistance (1, 2, 3 and 4), a bonding pad, an interconnecting wire (5) and a passivation layer (7);
s2: and forming a back cavity of the pressure sensor by adopting double-sided alignment photoetching, back deep silicon etching, RIE (reactive ion etching) for etching the buried oxide layer and back silicon-glass anode bonding processes.
The specific process of step S1 is as follows:
1) as shown in fig. 4-1, using an SOI silicon wafer as a substrate, the SOI was ultrasonically cleaned in acetone, ethanol, and deionized water for 5 minutes, blow-dried with nitrogen, and then baked on a hot plate at 180 degrees celsius for 15 minutes, respectively.
2) As shown in fig. 4-2, a 5 micron thick positive photoresist was spin coated on the front side of the SOI and patterned by photolithography to form a boron ion implantation window. Then, the implantation concentration was 4X 1014cm-2Forming a lightly doped piezoresistive structure.
3) As shown in fig. 4-3, a polyimide film is covered on the front surface of the piezoresistor and deep silicon etching is performed to transfer the alignment mark on the photoresist to the silicon substrate. Subsequently, the polyimide film was peeled off and the resist was removed.
4) As shown in fig. 4-4, a 5 μm thick positive photoresist is spin coated on the front side of the SOI and patterned by photolithography to form a secondary boron ion implantation window. Then, the implantation concentration was 2X 1015cm-2Forming a heavily doped ohmic contact.
5) As shown in fig. 4-5, PECVD deposits a layer of 0.5 micron thick silicon oxide as the SOI top silicon layer.
6) As shown in fig. 4-6, a 5 micron thick positive photoresist is spun onto the front side of the SOI and patterned by photolithography to form a silicon oxide etch window. Next, RIE etched the silicon oxide to a depth of 0.5 microns exposing the ion implanted regions and the contact points of the aluminum wire.
7) As shown in fig. 4-7, a layer of 1 micron thick aluminum metal is vapor deposited as the conductive metal layer. Then, a layer of 5 micron thick positive photoresist is spun on the front surface of the SOI and is subjected to photoetching and patterning, and a mask for wet etching of aluminum is formed. And finally, etching the aluminum metal layer by adopting a wet method to form a metal interconnection line and a bonding pad.
8) As shown in fig. 4-8, a 5 micron thick polyimide film was spin-deposited as the polyimide passivation layer.
9) As shown in fig. 4-9, a layer of positive photoresist is spun on and patterned by photolithography to form an etch window for polyimide. Subsequently, RIE etches the polyimide, exposing the window of the aluminum pad and the top silicon layer at the edge of the SOI.
The specific process of step S2 is as follows:
1) as shown in fig. 4-10, a layer of aluminum metal is deposited on the front side of the SOI by high power sputtering as a conductive metal layer of the top silicon and the bottom silicon of the SOI. Then, a layer of positive photoresist with the thickness of 5 microns is coated on the back surface of the SOI in a spinning mode, double-sided alignment photoetching patterning is carried out, and an etching area is exposed. Next, RIE is used to remove the silicon oxide layer.
2) As shown in fig. 4-11, the silicon is etched to the buried oxide layer using DRIE.
3) RIE is used to etch the back oxide layer and buried oxide layer to expose the back silicon layer as shown in fig. 4-12.
4) As shown in fig. 4-13, after polishing the back silicon, back silicon-glass anodic bonding is performed at 300 ℃, 1600V voltage, 20mA current, 1600N pressure for 20 min.
5) As shown in fig. 4-14, the wafer is mechanically diced, releasing individual pressure sensor dies.
Example 2
The monolithic integration preparation method of the wide-range pressure sensor chip comprises the following specific steps:
s1: the method comprises the steps that an SOI (silicon on insulator) is used as a substrate, and micro-processing technologies such as photoetching, ion implantation, Plasma Enhanced Chemical Vapor Deposition (PECVD), Reactive Ion Etching (RIE), spin coating, evaporation deposition, wet etching, stripping and the like are utilized to form plane structures such as piezoresistance (1, 2, 3 and 4), a bonding pad, an interconnecting wire (5) and a passivation layer (7);
s2: and forming a back cavity of the pressure sensor by adopting double-sided alignment photoetching, back deep silicon etching, RIE (reactive ion etching) for etching the buried oxide layer and back silicon-glass anode bonding processes.
The specific process of step S1 is as follows:
16) using an SOI silicon wafer as a substrate, ultrasonically cleaning the SOI wafer in acetone, ethanol and deionized water for 5 minutes, blow-drying the SOI wafer by nitrogen, and baking the SOI wafer on a hot plate at 180 ℃ for 15 minutes.
17) A layer of silicon oxide 300nm thick is deposited as an insulating layer on the front side of the SOI using PECVD.
18) A layer of 200nm thick polysilicon is deposited as an implant layer on the front side of the SOI using LPCVD.
19) Implanting boron ions with the concentration of 4 × 1014cm-2And forming a lightly doped polysilicon piezoresistive structure layer.
20) And spin-coating a layer of positive photoresist with the thickness of 5 microns on the front surface of the SOI, and carrying out photoetching and patterning to form a polysilicon etching mask. Next, four piezoresistive and alignment marks are formed on the front side of the SOI using a deep silicon etch.
21) And spin-coating a layer of positive photoresist with the thickness of 5 microns on the front surface of the SOI, and carrying out photoetching patterning to form a secondary boron ion implantation window.
22) Implanting boron ions with an implantation concentration of 2 × 1015cm-2Forming heavily doped contacts.
23) PECVD deposits a layer of 0.5 micron thick silicon oxide as the SOI top silicon layer.
24) And spin-coating a layer of positive photoresist with the thickness of 5 microns on the front surface of the SOI, and carrying out photoetching and patterning to form a silicon oxide etching window.
25) RIE etches the silicon oxide to a depth of 0.5 microns exposing the ion implanted regions and the aluminum wire contacts.
26) A layer of metallic aluminum 1 micron thick was vapor deposited as the conductive metal layer.
27) And spin-coating a layer of positive photoresist with the thickness of 5 microns on the front surface of the SOI, and carrying out photoetching patterning to form a mask for wet etching of aluminum.
28) And (5) wet etching the aluminum metal layer to form a metal interconnection line and a bonding pad.
29) A layer of polyimide film with the thickness of 5 microns is deposited by spin coating to serve as a polyimide passivation layer.
30) Spin coating a layer of positive photoresist and carrying out photoetching and patterning to form an etching window of the polyimide. Subsequently, RIE etches the polyimide, exposing the window of the aluminum pad and the top silicon layer at the edge of the SOI.
The specific process of step S2 is as follows:
1) and depositing a layer of metallic aluminum on the front surface of the SOI by high-power sputtering to serve as a conductive metal layer of the top silicon and the bottom silicon of the SOI. Then, a layer of positive photoresist with the thickness of 5 microns is coated on the back surface of the SOI in a spinning mode, double-sided alignment photoetching patterning is carried out, and an etching area is exposed. Next, RIE is used to remove the silicon oxide layer.
2) The silicon is etched to the buried oxide layer using DRIE.
3) RIE is used to etch the back oxide layer and the buried oxide layer to expose the back silicon layer.
4) And polishing the back silicon, and then carrying out back silicon-glass anodic bonding at the bonding temperature of 300 ℃, the voltage of 1600V, the current of 20mA, the pressure of 1600N and the time of 20 min.
5) And mechanically cutting the wafer to release the single pressure sensor chip.
The relationship between the pressure and the output voltage of the prepared wide-range pressure sensor chip at room temperature is shown in fig. 5, and it can be seen that the pressure and the output voltage of the pressure sensor can keep a good linear relationship in a pressure range of 0-5 MPa.

Claims (8)

1. A wide-range pressure sensor chip is characterized in that: the sensor chip structure comprises a back glass layer (12), an SOI bottom silicon layer (10), an SOI buried oxide layer (9), an SOI top silicon layer (8) and a polyimide passivation layer (7) which are sequentially stacked from bottom to top, and the sensor chip structure is formed together; the back glass layer (12) and the SOI bottom silicon layer (10) are bonded together through an anodic bonding process and form a vacuum chamber of the pressure sensor; the SOI top silicon layer (8) and the polyimide passivation layer (7) jointly form a pressure sensitive film; four piezoresistors distributed on the SOI top silicon layer (8) form a Wheatstone bridge structure; when the external pressure changes, the deformation of the pressure sensitive membrane causes the resistance values of the four piezoresistors to change and causes the output voltage of the Wheatstone bridge structure to change; the magnitude of the external pressure is calculated by detecting the magnitude of the output voltage.
2. The wide-range pressure sensor chip of claim 1, wherein: the piezoresistance in the SOI top silicon layer (8) is formed by low-concentration boron-doped silicon; before the back glass layer (12) and the SOI bottom silicon layer (10) are bonded through an anodic bonding process, a layer of metal aluminum is sputtered on the edge of the SOI silicon wafer through high power to form a conductive path between the front side and the back side of the SOI silicon wafer, and failure or breakdown piezoresistance in the anodic bonding process is avoided.
3. The wide-range pressure sensor chip of claim 1, wherein: the interconnection lines between the piezoresistors are made of aluminum deposited by evaporation, and conduction is realized by ohmic contact between the aluminum and the doped silicon.
4. The wide-range pressure sensor chip of claim 1, wherein: the length and width of the piezoresistance are 250 micrometers and 20 micrometers respectively; the four piezoresistors are respectively piezoresistors R1, R2, R3 and R4 which are sequentially arranged; the distance between the pressure resistor R1 and the pressure resistor R2 and the distance between the pressure resistor R3 and the pressure resistor R4 are both 140 micrometers; the distance between the pressure resistor R2 and the pressure resistor R3 is 50 microns; the length, width and thickness of the SOI top silicon layer (8) are 900, 450 and 50 microns respectively.
5. The monolithic fabrication method of a wide-range pressure sensor chip of claim 1; the method is characterized by comprising the following specific steps:
s1: the SOI is used as a substrate, and four piezoresistors, a bonding pad, an interconnection line (5) and a plane structure of a passivation layer (7) are formed by utilizing micro-processing technologies such as photoetching, ion implantation, plasma enhanced chemical vapor deposition, reactive ion etching, spin coating, evaporation deposition, wet etching, stripping and the like;
s2: and forming a vacuum chamber (11) of the pressure sensor by adopting double-sided alignment photoetching, back deep silicon etching, RIE etching buried oxide layer and back silicon-glass anodic bonding process.
6. The monolithically integrated manufacturing method of claim 5, wherein: the specific process of step S1 is as follows:
1) using an SOI silicon wafer as a substrate, cleaning, drying and baking the substrate;
2) spin-coating a layer of positive photoresist and carrying out photoetching patterning to form a boron ion injection window;
3) injecting boron ions to form a lightly doped piezoresistive structure;
4) covering the piezoresistive region with polyimide film, and transferring the alignment mark to the silicon substrate by deep silicon etching;
5) spin-coating a layer of positive photoresist and carrying out photoetching patterning to form a secondary boron ion injection window;
6) boron ion implantation is carried out to form a heavily doped contact point and a lead;
7) depositing a layer of silicon oxide by PECVD;
8) spin-coating a layer of positive photoresist and carrying out photoetching patterning to form a silicon oxide etching window;
9) RIE etching the silicon oxide to expose the ion implantation area and the contact point of the aluminum wire;
10) evaporating and depositing a layer of metallic aluminum as a conductive metal layer;
11) spin-coating a layer of positive photoresist and carrying out photoetching and patterning to form a mask for wet etching of aluminum;
12) corroding the aluminum metal layer by a wet method to form a metal interconnection line and a bonding pad;
13) a layer of polyimide film is deposited in a spin coating mode to serve as a polyimide passivation layer (7);
14) spin-coating a layer of positive photoresist and carrying out photoetching patterning to form an etching window of polyimide;
15) RIE etching the polyimide to expose the window of the aluminum bonding pad and the top silicon layer at the edge of the SOI;
16) and evaporating and depositing a layer of metallic aluminum to be used as a conductive metal layer of the SOI top layer silicon and the SOI bottom layer silicon.
7. The monolithically integrated manufacturing method of claim 5, wherein: the specific process of step S1 is as follows:
1) using an SOI silicon wafer as a substrate, cleaning, drying and baking the substrate;
2) depositing a layer of silicon oxide on the front surface of the SOI by PECVD (plasma enhanced chemical vapor deposition) to serve as an insulating layer;
3) depositing a layer of polysilicon on the front surface of the SOI by LPCVD to be used as an injection layer;
4) injecting boron ions to form a lightly doped polysilicon piezoresistive structure layer;
5) spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching patterning to form a polysilicon etching mask; then, forming four piezoresistors and alignment marks on the front surface of the SOI by using deep silicon etching;
6) spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching patterning to form a secondary boron ion implantation window;
7) boron ion implantation to form a heavily doped contact point;
8) depositing a layer of silicon oxide by PECVD;
9) spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching patterning to form a silicon oxide etching window;
10) RIE etching the silicon oxide to expose the ion implantation area and the contact point of the aluminum wire;
11) evaporating and depositing a layer of aluminum as a conductive metal layer;
12) spin-coating a layer of positive photoresist on the front surface of the SOI and carrying out photoetching and patterning to form a mask for wet etching aluminum;
13) corroding the aluminum metal layer by a wet method to form a metal interconnection line and a bonding pad;
14) a layer of polyimide film is deposited in a spin coating mode and serves as a polyimide passivation layer;
15) spin-coating a layer of positive photoresist and carrying out photoetching patterning to form an etching window of polyimide; subsequently, RIE etches the polyimide, exposing the window of the aluminum pad and the top silicon layer at the edge of the SOI.
8. The monolithically integrated manufacturing method of claim 5, wherein: the specific process of step S2 is as follows:
1) spin-coating a layer of positive photoresist on the back surface of the substrate and carrying out double-sided alignment photoetching patterning to expose an etching area;
2) RIE etching silicon oxide, and DRIE etching silicon to the buried oxide layer;
3) RIE etching the back oxide layer and the buried oxide layer;
4) polishing the back silicon, and then carrying out back silicon-glass anodic bonding;
5) and mechanically cutting the wafer to release the single pressure sensor chip.
CN202110593586.7A 2021-05-28 2021-05-28 Wide-range pressure sensor chip and monolithic integration preparation method thereof Pending CN113371674A (en)

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