CN113366372B - Process flow of micro display projector based on mixed TFT - Google Patents

Abstract

For small, high resolution, light Emitting Diode (LED) displays, such as for near-eye displays used in artificial reality headsets, the LEDs are closely spaced together. The back plate may be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the back plate to the LED array. As the pitch between LEDs becomes smaller than the interconnect pitch, thin film circuit layers may be used to reduce the number of interconnects between the back plane and the LED array so that the interconnect pitch may be greater than the LED pitch. This may allow for a denser arrangement of LEDs in the LED display while still allowing for the use of a silicon back plate with driving circuitry to control the operation of the LEDs in the LED display.

Description

Process flow of micro display projector based on mixed TFT

Cross Reference to Related Applications

The present application claims U.S. provisional application No. 62/801,424 entitled "Hybrid Display Architecture" filed on 5/2/2019; U.S. provisional application No. 62/861,254 entitled "Hybrid Display Concept-Hybrid Si and TFT Micro-Display (IGZO)" filed on 6/13 of 2019; U.S. provisional application No. 62/863,659 entitled "uLED Devices and Process For TFT-Based Projector (Hybrid IGZO TFT)" filed on 6/19/2019 and U.S. provisional application No. 62/924,604 entitled "Process Flow For Hybrid TFT-Based Micro Display Projector" filed on 10/22/2019. The present application also claims U.S. patent application Ser. No. 16/660,648 filed on 10/22 of 2019; U.S. patent application Ser. No. 16/660,643 filed on 10/22 of 2019; and priority to U.S. patent application Ser. No. 16/780,486, filed 2/3/2020. These applications are incorporated by reference for all purposes.

Background

Light Emitting Diodes (LEDs) convert electrical energy to light energy and provide a number of advantages over other light sources, such as reduced size, improved durability, and improved efficiency. LEDs can be used as light sources in many display systems, such as televisions, computer monitors, notebook computers, tablet computers, smartphones, projection systems, and wearable electronics. micro-LEDs ("μleds") based on group III-V and group III nitride semiconductors (such as alloys of AlN, gaN, inN and the like) have begun to be developed for various display applications due to their small size (e.g., linear dimensions less than 100 μm, less than 50 μm, less than 10 μm, or less than 5 μm), high packing density (and thus higher resolution), and high brightness. For example, micro-LEDs that emit different colors (e.g., red, green, and blue) may be used to form subpixels of a display system, such as a television or near-eye display system.

SUMMARY

The present disclosure relates generally to micro light emitting diodes (micro-LEDs) for displays. More particularly, the present disclosure relates to integration of display devices with control circuitry. Displays are ubiquitous and are a core component of wearable devices, smart phones, tablet computers, notebook computers, desktop computers, televisions, and display systems. Common display technologies today include Light Emitting Diode (LED) displays.

The display may be created by assembling an array of LED display devices on a back plate. One or more LED display devices in the array of LED display devices may be grouped to form pixels. The display may generate control signals to control each pixel. The back plate may provide structural support for the LED display device and provide electrical connections to transmit control signals to the LED display device. Integration of the LED display device with the back plate can affect the pixel level interconnection and the fabrication of the LED devices on the back plate, all of which can affect the performance of the LED display device.

According to some embodiments, an apparatus includes an array of Light Emitting Diodes (LEDs); a thin film circuit layer deposited over the LED array; and a back plane coupled to the thin film circuit layer using a plurality of metal bonds. The LED array is made of a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer. The LED array is a support structure for the thin film circuit layer. The thin film circuit layer includes circuitry for controlling the operation of the LEDs in the LED array. The back plate has a driving circuit for supplying current to the thin film circuit layer through the plurality of metal bonding pieces. The number of the plurality of metal bonds is less than the number of LEDs in the LED array. In some embodiments, the LED array has a light emitting side and a side opposite the light emitting side, and a thin film circuit layer is deposited on the side of the LED array opposite the light emitting side, and the thin film circuit layer includes transistors and capacitors interconnected to form pixel circuits for controlling operation of LEDs in the LED array; the pixel circuit implements analog, pulse code modulation, or pulse width modulation to control the intensity of the LEDs in the LED array; the storage capacitor of the pixel circuit is configured to be coupled to a data line (dataline) by one or more select signals; the pixel circuits are interconnected to reduce the number of metal bonds between the back plate and the thin film circuit layer; the single pixel circuit is connected to the multi-row selection signal; the backplane is configured to transmit a global signal to the thin film circuit layer through one of the plurality of metal bonds, wherein the global signal comprises one or more of: row data lines, column data lines, analog bias, supply voltage, pulse clock, or test enable features (test enablement features); no transistor in the thin film circuit layer is used to charge/discharge a global network (global net); the thin film circuit layer includes a selector multiplexer; the selector multiplexer includes a common signal line (common signal line) in the thin film circuit layer electrically coupled to the plurality of transistors in the thin film circuit layer and configured to be alternately activated such that current from the common signal line periodically passes through each of the plurality of transistors; the thin film circuit layer includes a memory circuit and a modulator circuit; assigning a unique address to each LED in the LED array, and the control signals include the unique address and an operation signal to control operation of the selected LED in the LED array; the operating signal is configured to control the magnitude of the current flowing through the selected LED, and the operating signal includes a digital signal representing a percentage of time during a period of time that the current flows to the selected LED; and/or the spacing between the centers of the LEDs is no more than 3 microns.

In some embodiments, a method comprises: obtaining a semiconductor structure, wherein the semiconductor structure is a layered epitaxial structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer; depositing a thin film circuit layer over the semiconductor structure; forming a circuit for controlling light emission of the light emitting layer in the thin film circuit layer; obtaining a back plate including a driving circuit for supplying current to the thin film circuit layer through the plurality of metal bonding pieces; forming a plurality of interconnects on the thin film circuit layer or on the back plane; bonding (bond) a back plane to the thin film circuit layer using a plurality of interconnects, wherein the plurality of interconnects become a plurality of metal bonds after bonding; and/or forming a Light Emitting Diode (LED) array from the semiconductor structure, wherein the number of the plurality of metal bonds is less than the number of LEDs in the LED array, the LED array having a light emitting side and a side opposite the light emitting side, and wherein the thin film circuit layer is deposited on the side opposite the light emitting side. In some embodiments, obtaining a backplate includes forming a plurality of CMOS transistors and interconnects in a silicon device layer of a silicon wafer (wafer); forming the LED array includes singulating (singulating) the semiconductor structure, and wherein singulating the semiconductor structure occurs prior to bonding the back plate to the thin film circuit layer; a thin film circuit layer formed on the wafer level semiconductor structure; and/or the back plane includes circuitry formed in the back plane prior to bonding.

According to some embodiments, an apparatus includes an array of Light Emitting Diodes (LEDs); a thin film circuit layer deposited over the LED array; and a back plate coupled to the thin film circuit layer using a plurality of metal bonds. The LED array is made of a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer. The LED array is a support structure for the thin film circuit layer. The thin film circuit layer includes circuitry for controlling the operation of the LEDs in the LED array. The back plate has a driving circuit for supplying current to the thin film circuit layer through the plurality of metal bonding pieces. The number of the plurality of metal bonds is less than the number of LEDs in the LED array. The plurality of metal bonds are made of a material having a melting point or bonding temperature less than 300 degrees celsius to reduce walk-off (walk off) of the thin film circuit layer when bonded to the back plate.

In some embodiments, the plurality of metal bonds comprises nanoporous copper (nanoporous copper); the spacing between metal bonds in the plurality of metal bonds is equal to or greater than 5 microns and equal to or less than 18 microns; the LED array includes a count of LEDs, the plurality of metal bonds corresponds to the count of metal bonds, and the count of metal bonds is at least two orders of magnitude less than the count of LEDs; the LED array occupies a certain occupied area (footprint), and a plurality of metal bonding pieces are scattered on the occupied area; each LED in the LED array is comprised of a crystalline semiconductor structure, and the thin film circuit layer is not lattice matched to the crystalline semiconductor structure of the LED array; the thin film circuit layer includes a semiconductor material having an amorphous (amorphlus) or polycrystalline structure; the thin film circuit layer comprises a material comprising at least one of: c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO), amorphous indium gallium zinc oxide (a-IGZO), low Temperature Polysilicon (LTPS), or amorphous silicon (a-Si); the LED array comprises a material comprising at least one of: gallium nitride (GaN), indium gallium arsenide (InGaAs), indium gallium phosphide (AlInGaP), or gallium arsenide (GaAs); the driving circuit in the backboard is monocrystalline silicon; and/or the drive circuit of the back plate comprises CMOS (complementary metal oxide semiconductor) transistors.

In some embodiments, a method comprises: obtaining a semiconductor structure, wherein the semiconductor structure is a layered epitaxial structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer; depositing a thin film circuit layer over the semiconductor structure; forming a circuit for controlling light emission of the light emitting layer in the thin film circuit layer; obtaining a back plate including a driving circuit for supplying current to the thin film circuit layer through the plurality of metal bonding pieces; forming a plurality of bumps (bumps) on the thin film circuit layer or on the back plate, wherein the bumps are made of a material with a melting point or bonding temperature lower than 300 ℃; bonding the back plate to the thin film circuit layer using a plurality of bumps, wherein the bonding uses a temperature of no more than 300 degrees celsius, and the plurality of bumps become a plurality of metal bonds after bonding; and/or forming a Light Emitting Diode (LED) array from the semiconductor structure, wherein the number of the plurality of metal bonds is less than the number of LEDs in the LED array. In some embodiments, bonding the back plate to the thin film circuit layer uses a temperature of no more than 200 degrees celsius; the plurality of LEDs in the LED array are configured to receive current from the back plate through one of the plurality of metal bonds after bonding the back plate to the thin film circuit layer; the LED array is divided into a plurality of tiles, each tile of the plurality of tiles comprising a plurality of rows of LEDs, and the rows of the plurality of rows are configured to be activated at different times; the spacing between metal bonds in the plurality of metal bonds is equal to or greater than 5 microns and equal to or less than 18 microns; and/or forming circuitry in the thin film circuit layer includes forming a plurality of transistors in the thin film circuit layer and a control line electrically coupled to the plurality of transistors.

According to a particular embodiment, a method includes: obtaining an epitaxial structure, wherein the epitaxial structure is a layered structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer; isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer to form a plurality of Light Emitting Diodes (LEDs); depositing a thin film circuit layer to the epitaxial structure, wherein the thin film circuit layer comprises: a first thin film layer and a second thin film layer; and/or bonding the thin film circuit layer to the back plane. In some embodiments, the first thin film layer includes a plurality of transistors; the second thin film layer includes interconnects for the plurality of transistors; the first doped semiconductor layer is an n-type doped layer; the second doped semiconductor layer is a p-type doped layer; isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer includes etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer; the second doped semiconductor layer is p-doped and the method further comprises: bonding a temporary carrier (temporary carrier) to the second doped semiconductor layer and removing the substrate from the epitaxial structure, wherein the substrate is closer to the first doped semiconductor layer than the second doped semiconductor layer prior to removing the substrate; etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer occurs prior to depositing the thin film circuit layer to the epitaxial structure; etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer occurs after bonding the thin film circuit layer to the backplate; etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer occurs after depositing the first thin film layer and before applying the second thin film layer; etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer includes etching both the first doped semiconductor layer and the second doped semiconductor layer, and further includes etching the first thin film layer; and/or the method may further comprise forming a light extraction element to the epitaxial structure to couple light out of the light emitting layer; bonding a temporary carrier to the epitaxial structure prior to depositing the thin film circuit layer to the epitaxial structure; removing the temporary carrier after bonding the second thin film layer of the thin film circuit layer to the back plate: bonding a temporary carrier to the epitaxial structure, wherein the second doped semiconductor layer is between the first doped semiconductor layer and the temporary carrier, and the first doped semiconductor structure is between the second doped semiconductor structure and the substrate of the epitaxial structure; removing the substrate from the epitaxial structure, wherein isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer comprises: implanting ions into the first doped semiconductor layer to isolate portions of the first doped semiconductor layer prior to depositing the thin film circuit layer on the epitaxial structure; implanting ions in the second doped semiconductor layer prior to bonding the temporary carrier to the epitaxial structure; and/or bonding a temporary carrier to the epitaxial structure prior to removing the substrate from the epitaxial structure, wherein isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer comprises: ions are implanted in the second doped semiconductor layer prior to bonding the temporary carrier to the epitaxial structure.

In a particular embodiment, a method includes: obtaining an epitaxial structure, wherein the epitaxial structure is a layered structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer; applying a thin film circuit layer to the epitaxial structure; isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer to form a plurality of Light Emitting Diodes (LEDs); bonding the thin film circuit layer to the transparent substrate after applying the thin film circuit layer to the epitaxial structure; and/or bonding the back plate to the transparent substrate, wherein: the back plate is electrically coupled to the thin film circuit layer and/or the thin film circuit layer is on the same side of the transparent substrate as the back plate. In some embodiments, isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer to form the plurality of LEDs comprises: etching; ion implantation is used to isolate portions of the first doped semiconductor layer, to isolate portions of the second doped semiconductor layer, or to isolate portions of both the first doped semiconductor layer and the second doped semiconductor layer to form a plurality of LEDs; and/or isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer to form the plurality of LEDs is performed prior to applying the thin film circuit layer to the epitaxial structure.

In a particular embodiment, an apparatus includes a transparent substrate; a plurality of Light Emitting Diodes (LEDs); a thin film circuit layer comprising a plurality of transistors electrically coupled to a plurality of LEDs, wherein: the plurality of transistors are configured to control operation of the plurality of LEDs, and the thin film circuit layer is bonded to the transparent substrate; and/or a back plate bonded to the transparent substrate, wherein: the back plate is electrically coupled to the thin film circuit layer and/or the back plate is on the same side of the transparent substrate as the thin film circuit layer. In some embodiments, the apparatus includes a frame of an augmented reality system, the frame holding a plurality of LEDs, wherein the plurality of LEDs are part of a display for the augmented reality system; and/or traces in the thin film circuit layer electrically couple one bond between the thin film circuit layer and the transparent substrate with a plurality of the plurality of transistors to control operation of a plurality of the plurality of LEDs.

This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this disclosure, any or all of the accompanying drawings, and each claim. The foregoing and other features and examples will be described in more detail below in the attached specification, claims and drawings.

Brief Description of Drawings

Illustrative embodiments are described in detail below with reference to the following drawings.

Fig. 1 is a simplified block diagram of an example of an artificial reality system environment including a near-eye display, according to a particular embodiment.

Fig. 2 is a perspective view of an example of a near-eye display in the form of a Head Mounted Display (HMD) device for implementing some of the examples disclosed herein.

Fig. 3 is a perspective view of an example of a near-eye display in the form of a pair of glasses for implementing some of the examples disclosed herein.

Fig. 4 illustrates an example of an optical see-through augmented reality system (optical seal-through augmented reality system) including a waveguide display, in accordance with certain embodiments.

Fig. 5A illustrates an example of a near-eye display device including a waveguide display, in accordance with certain embodiments.

Fig. 5B illustrates an example of a near-eye display device including a waveguide display, in accordance with certain embodiments.

Fig. 6 illustrates an example of an image source component (image source assembly) in an augmented reality system according to a particular embodiment.

Fig. 7A illustrates an example of a Light Emitting Diode (LED) with a vertical mesa structure in accordance with certain embodiments.

Fig. 7B is a cross-sectional view of an example of an LED with a parabolic mesa structure (parabolic mesa structure a) in accordance with a particular embodiment.

Fig. 8A illustrates an example of a die-to-wafer bonding (die-to-wafer bonding) method for an LED array, in accordance with certain embodiments.

Fig. 8B illustrates an example of a wafer-to-wafer bonding (wafer-to-wafer bonding) method for an LED array, according to a particular embodiment.

Fig. 9A-9D illustrate examples of hybrid bonding methods for LED arrays according to particular embodiments.

Fig. 10 illustrates an example of an LED array having secondary optic fabricated thereon, in accordance with certain embodiments.

Fig. 11 is a side view of an example display.

Fig. 12 is a top view of the example display of fig. 11.

Fig. 13 illustrates an example of a thin film circuit layer deposited over an LED array with a back plate bonded to the thin film circuit layer.

Fig. 14 illustrates an example of a micro LED array.

Fig. 15 illustrates an example of micro bump positioning in relation to a micro LED array.

Fig. 16 illustrates a cross-sectional view of a thin film circuit layer over an LED.

Fig. 17 illustrates a cross-sectional view of an example of a back plate bonded to an LED array.

Fig. 18 illustrates an example architecture of a display device.

Fig. 19-21 illustrate example modulation circuits of a display device.

Fig. 22 illustrates an example of an addressing scheme using one connection per pixel.

Fig. 23 illustrates an example of an addressing scheme using rows and columns.

Fig. 24 illustrates an example circuit for addressing LEDs using two row signals.

Fig. 25 illustrates an example layout for addressing LEDs using multiple row signals.

Fig. 26 is a flow chart of an embodiment of a process of manufacturing a display device.

Fig. 27 illustrates an example sliding scale (sliding scale) for adding complexity and micro-bump reduction of functionality to a thin film circuit layer.

Fig. 28 is a flow chart of an embodiment of a process of manufacturing a micro LED display.

Fig. 29 illustrates an example of an array divided into blocks.

Fig. 30 illustrates an example of a circuit for applying current to rows in a block.

Fig. 31 illustrates an example of bump locations of a tile.

Fig. 32 is an example chart comparing block size with bump pitch.

Fig. 33 is a flow chart of an embodiment of a process of manufacturing an LED display.

Fig. 34 is a simplified cross-section of an embodiment of an epitaxial structure.

Fig. 35 is a simplified cross section of an embodiment of an epitaxial structure with a contact layer and temporary bonding layer deposited thereon.

Fig. 36 is a simplified cross section of an embodiment of an epitaxial structure to which a temporary carrier is bonded.

Fig. 37 is a simplified cross section of an embodiment of an epitaxial structure from which a substrate is removed.

Fig. 38 is a simplified cross section of an embodiment of an epitaxial structure, wherein the epitaxial structure is etched to singulate the epitaxial structure.

Fig. 39 is a simplified cross-section of an embodiment of a thin film circuit layer deposited on an epitaxial structure.

Figure 40 is a simplified cross-section of an embodiment of a thin film circuit layer bonded to a back plate.

Fig. 41 is a simplified cross-section of an embodiment with temporary carrier removed after bonding.

Fig. 42 is a simplified cross-section of an embodiment of adding light extraction elements to an epitaxial structure.

Fig. 43 is a simplified cross-section of an embodiment of depositing a thin film circuit layer to an epitaxial structure prior to etching the epitaxial structure.

Figure 44 is a simplified cross-section of an embodiment of bonding a thin film circuit layer to a back plate.

Fig. 45 is a simplified cross-section of an embodiment of the temporary carrier removed after bonding.

Fig. 46 is a simplified cross-section of an embodiment of etching an epitaxial structure after removal of the temporary carrier.

Fig. 47 is a simplified cross-section of an embodiment of adding light extraction elements to an epitaxial structure.

Fig. 48 is a simplified cross-section of an embodiment of depositing a first thin film layer of a thin film circuit layer to an epitaxial structure.

Fig. 49 is a simplified cross-section of an embodiment etched through the first thin film layer and the epitaxial structure.

Figure 50 is a simplified cross-section of an embodiment of depositing a second thin film layer of a thin film circuit layer to a first thin film layer after etching the first thin film layer and the epitaxial structure.

Figure 51 is a simplified cross-section of an embodiment of bonding a thin film circuit layer to a back plate.

Fig. 52 is a simplified cross-section of an embodiment with temporary carrier removed after bonding.

Fig. 53 is a simplified cross-section of an embodiment of adding light extraction elements to an epitaxial structure.

Figure 54 is a flow chart of an embodiment of a process of etching to isolate portions of an epitaxial structure.

Fig. 55 is a simplified cross-section of an embodiment of an epitaxial structure.

Fig. 56 is a simplified cross-section of an embodiment of p-side isolation of an external structure by ion implantation.

Fig. 57 is a simplified cross section of an embodiment of an epitaxial structure with a contact layer and temporary bonding layer deposited thereon.

Fig. 58 is a simplified cross section of an embodiment of an epitaxial structure to which a temporary carrier is bonded.

Fig. 59 is a simplified cross-section of an embodiment of etching an epitaxial structure from which a substrate is removed.

Fig. 60 is a simplified cross-section of an embodiment of n-side isolation of an external structure by ion implantation.

Fig. 61 is a simplified cross-section of an embodiment of a thin film circuit layer deposited on an epitaxial structure.

Figure 62 is a simplified cross-section of an embodiment of a thin film circuit layer bonded to a back plate.

Fig. 63 is a simplified cross-section of an embodiment of the temporary carrier removed after bonding.

Fig. 64 is a simplified cross-section of an embodiment of adding light extraction elements to an epitaxial structure.

Figure 65 is a flow chart of an embodiment of a process for isolating portions of an epitaxial structure using ion implantation.

Figure 66 is a flow chart of an embodiment of a process of isolating portions of an epitaxial structure.

Fig. 67 is a simplified cross-section of an embodiment of an epitaxial structure bonded to a transparent substrate.

Fig. 68 is a simplified illustration of traces of an LED array bonded to a transparent substrate.

Fig. 69 is a flow chart of an embodiment for bonding an LED array to a transparent substrate.

Fig. 70 is a simplified block diagram of an electronic system of an example of a near-eye display in accordance with certain embodiments.

The figures depict embodiments of the present disclosure for purposes of illustration only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the illustrated structures and methods may be employed without departing from the principles or advantages of the present disclosure.

In the drawings, similar components and/or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

Detailed Description

The present disclosure relates generally to Light Emitting Diodes (LEDs). More particularly, and without limitation, techniques for integrating circuitry with an LED display are disclosed herein. Various inventive embodiments are described herein, including apparatuses, systems, methods, materials, and the like.

Common display technologies today range from Liquid Crystal Displays (LCDs) to newer Organic Light Emitting Diode (OLED) displays and Active Matrix Organic Light Emitting Diode (AMOLED) displays. Inorganic Light Emitting Diodes (ILED) are becoming third generation flat display image generators based on excellent battery performance and enhanced brightness. "μLED", "uLED", "micro-LED" or "micro-LED" as described herein refers to a light emitting diode having a small effective light emitting area (e.g., less than 2,000 μm) ² ) And in some examples, directed light can be generated to increase the brightness level of light emitted from a small effective light emitting area. In some examples, micro LEDs may refer to LEDs having an effective light emitting thickness of less than 50 μm, less than 20 μm, or less than 10 μm. In some examples, the linear dimension may be as small as 2 μm or 4 μm. For the remainder of this disclosure, "LED" may refer to μ LED, ILED, OLED or other types of LED devices.

ILED displays may be manufactured using a different process than OLED displays. For example, OLED devices are fabricated directly on display substrates. In contrast, ILED devices are manufactured separately from the display substrate. The base material (base material) of the ILED devices may be grown on a crystalline substrate to form an LED starter wafer (LED starter wafer). The LED starter wafer may be processed through various steps to produce individual LED dies (die), each of which includes an LED device. Once fabricated, the LED die may be transferred from the carrier substrate to the back plate. The back panel may be a display back panel of a display device. The LED devices of the display device may be divided to form pixels. Each pixel may receive control signals from a control circuit to set, for example, the intensity and color of the pixel display. The back plate may also include signal lines to transmit control signals to the LED devices. The back plate may include bumps or other interconnect structures to provide electrical connection between the LED devices and the signal lines.

In some examples, the back plate may include bumps, one for each LED device or for each pixel (each pixel may include one or more LED devices), such that each pixel may receive the control signal individually. However, this arrangement results in a large number of bumps being placed on the back plate. For example, a display comprising one million pixels may include one million bumps. The large number of bumps and associated signal lines can reduce the tight integration between the LED device and the control circuitry and the quality of the manufacture of the LED device, which can affect the performance of the display.

Examples of the present disclosure provide a display device. The display apparatus may include a Light Emitting Diode (LED) device, a transistor layer, and a back plate. The transistor layer is electrically connected with the LED device and includes: (a) A set of transistors, and (b) a common signal line electrically connected to and shared between the set of transistors. Each set of transistors corresponds to each of the LED devices and includes a transistor configured to control operation of the corresponding LED device based on a control signal received from the common signal line. The back plate may include bumps, each bump being electrically connected to one or more common signal lines. The back plate may also include a controller configured to generate a control signal and transmit the control signal to the bumps.

In some examples, the transistor layer may include a Thin Film Transistor (TFT) formed on a back-end (back-end) of each LED device forming the pixel. Where the controller is internal to the backplate, the backplate may comprise a silicon substrate integrating a silicon Complementary Metal Oxide Semiconductor (CMOS) controller. The controller may drive the TFT of each pixel via the bump. The bump is connected to a common signal line of the transistor layer, sharing the bump and the common line between TFTs of the pixels. The common signal line may carry a selection signal (e.g., a pixel address including a row selection and/or a column selection signal) for selecting a pixel and an operation signal for selecting a color and/or an output intensity of the pixel. To drive a pixel, the controller may transmit a selection signal and an operation signal for the pixel to the bump. The TFT of the pixel may receive a signal from the common signal line, but only the TFT of the target pixel is selected according to the selection signal in response to the operation signal.

With the disclosed techniques, the number of bumps (or other types of interconnect structures) formed on the backplate can be significantly reduced. Instead of providing control signals to individual pixels, bumps may be used to provide common control signals that are shared between some or all of the pixels. Further, since the controller is electrically connected with a smaller number of bumps and signal lines, the controller can be made more compact and can operate at a higher speed, which can relax the performance requirements for the TFT and can reduce power. Furthermore, the disclosed technology also enables the monolithic fabrication of the TFTs of the LED devices on a single wafer/substrate, which not only allows for a tight integration of the LED devices and the TFTs controlling the LED devices, but also facilitates the optimization of the LED devices. All of which can improve the performance of the LED device and the display apparatus.

The micro LEDs described herein may be used in conjunction with a variety of technologies, such as artificial reality systems. An artificial reality system, such as a head-mounted display (HMD) or head-up display (HUD) system, typically includes a display configured to present an artificial image depicting an object in a virtual environment. As in Virtual Reality (VR), augmented Reality (AR), or Mixed Reality (MR) applications, the display may present virtual objects or combine images of real objects with virtual objects. For example, in an AR system, a user may view both a displayed image of a virtual object (e.g., a Computer Generated Image (CGI)) and the surrounding environment by, for example, viewing through transparent display glasses or lenses (commonly referred to as optical perspectives) or viewing a displayed image of the surrounding environment captured by a camera (commonly referred to as video perspectives). In some AR systems, an LED-based display subsystem may be used to present the artificial image to the user.

As used herein, the term "Light Emitting Diode (LED)" refers to a light source including at least an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting region (i.e., an active region) between the n-type semiconductor layer and the p-type semiconductor layer. The light emitting region may include one or more semiconductor layers forming one or more heterostructures, such as quantum wells. In some embodiments, the light emitting region may include a plurality of semiconductor layers forming one or more Multiple Quantum Wells (MQWs), each multiple quantum well including a plurality (e.g., about 2 to 6) of quantum wells.

As used herein, the term "micro LED" or "μled" refers to an LED having a chip with a linear dimension of less than about 200 μm, such as less than 100 μm, less than 50 μm, less than 20 μm, less than 10 μm, or less. For example, the linear dimensions of the micro-LEDs may be as small as 6 μm, 5 μm, 4 μm, 2 μm or less. Some micro LEDs may have a linear dimension (e.g., length or diameter) comparable to a minority carrier (carrier) diffusion length. However, the disclosure herein is not limited to micro LEDs, but may also be applied to mini LEDs (mini-LEDs) and large LEDs.

As used herein, the term "bonding" may refer to various methods for physically and/or electrically connecting two or more devices and/or wafers, such as adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, soldering, under bump metallization, and the like. For example, adhesive bonding may use a curable adhesive (e.g., epoxy) to physically bond two or more devices and/or wafers by adhesion. Metal-to-metal bonding may include wire bonding (wire bonding) or flip chip bonding (flip chip bonding) using, for example, a solder interface (e.g., pad or ball), conductive adhesive or solder joint between metals. Metal oxide bonding may form a pattern of metal and oxide on each surface, bonding the oxide portions together, and then bonding the metal portions together to form a conductive path. Wafer-to-wafer bonding may bond two wafers (e.g., silicon wafers or other semiconductor wafers) without any intervening layers and is based on chemical bonds between the surfaces of the two wafers. Wafer-to-wafer bonding may include wafer cleaning and other pre-treatments, alignment and pre-bonding at room temperature, and annealing at elevated temperatures (such as about 250 ℃ or higher). Die-to-wafer bonding may use bumps on one wafer to align the features of the pre-die with the driver of the wafer. Hybrid bonding may include, for example, wafer cleaning, high precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials within the wafer at room temperature, and metal bonding of contacts by annealing, for example, at 250-300 ℃ or higher. As used herein, the term "bump" may generally refer to a metal interconnect, such as a metal pad, that is used or formed during bonding. The disclosed technique is applicable to so-called bump-less (bump-less) bonding processes.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present disclosure. It may be evident, however, that the various examples may be practiced without these specific details. For example, devices, systems, structures, components, methods, and other components may be shown in block diagram form in order to avoid obscuring the examples in unnecessary detail. In other instances, well-known devices, processes, systems, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the examples. The drawings and description are not intended to be limiting. The terms and expressions which have been employed in the present disclosure are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions thereof. The term "exemplary" as used herein means "serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

Fig. 1 is a simplified block diagram of an example of an artificial reality system environment 100 including a near-eye display 120, according to a particular embodiment. The artificial reality system environment 100 shown in fig. 1 may include a near-eye display 120, an optional external imaging device 150, and an optional input/output interface 140, each of which may be coupled to an optional console 110. Although fig. 1 illustrates an example of an artificial reality system environment 100 including a near-eye display 120, an external imaging device 150, and an input/output interface 140, any number of these components may be included in the artificial reality system environment 100, or any of these components may be omitted. For example, there may be a plurality of near-eye displays 120 monitored by one or more external imaging devices 150 in communication with the console 110. In some configurations, the artificial reality system environment 100 may not include an external imaging device 150, an optional input/output interface 140, and an optional console 110. In alternative configurations, different or additional components may be included in the artificial reality system environment 100.

Near-eye display 120 may be a head-mounted display that presents content to a user. Examples of content presented by near-eye display 120 include one or more of the following: image, video, audio, or any combination thereof. In some embodiments, the audio may be presented via an external device (e.g., a speaker and/or headphones) that receives audio information from near-eye display 120, console 110, or both near-eye display 120 and console 110 and presents audio data based on the audio information. The near-eye display 120 may include one or more rigid bodies, which may be rigidly or non-rigidly coupled to each other. The rigid coupling between the rigid bodies may be such that the coupled rigid bodies act as a single rigid entity. The non-rigid coupling between the rigid bodies may allow the rigid bodies to move relative to one another. In various embodiments, the near-eye display 120 may be implemented in any suitable form factor, including a pair of glasses. Some embodiments of near-eye display 120 are further described below with reference to fig. 2 and 3. Furthermore, in various embodiments, the functionality described herein may be used in a head-mounted device (head set) that combines images of the environment external to the near-eye display 120 and artificial reality content (e.g., computer generated images). Thus, the near-eye display 120 may augment images of the physical, real-world environment external to the near-eye display 120 with generated content (e.g., images, video, sound, etc.) to present augmented reality to the user.

In various embodiments, the near-eye display 120 may include one or more of the following: display electronics 122, display optics 124, and eye tracking unit 130. In some embodiments, the near-eye display 120 may also include one or more positioners 126, one or more position sensors 128, and an Inertial Measurement Unit (IMU) 132. In various embodiments, near-eye display 120 may omit any of the following: an eye tracking unit 130, a locator 126, a position sensor 128, and an IMU 132, or may include additional elements. Further, in some embodiments, near-eye display 120 may include elements that combine the functions of the various elements described in connection with fig. 1.

Display electronics 122 may display images to a user or facilitate display of images to a user based on data received from, for example, console 110. In various embodiments, display electronics 122 may include one or more display panels, such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Inorganic Light Emitting Diode (ILED) display, a micro light emitting diode (μled) display, an active matrix OLED display (AMOLED), a transparent OLED display (TOLED), or some other display. For example, in one embodiment of the near-eye display 120, the display electronics 122 may include a front TOLED panel, a rear display panel, and an optical component (e.g., an attenuator, polarizer, or diffractive or spectral film) between the front display panel and the rear display panel. The display electronics 122 may include pixels to emit light having a primary color (predominant color) such as red, green, blue, white, or yellow. In some implementations, the display electronics 122 may display a three-dimensional (3D) image through a stereoscopic effect produced by a two-dimensional panel to create a subjective perception of image depth. For example, display electronics 122 may include left and right displays positioned in front of the left and right eyes, respectively, of the user. The left and right displays may present copies of the image horizontally offset (shifted) relative to each other to create a stereoscopic effect (i.e., the perception of image depth by a user viewing the image).

In particular embodiments, display optics 124 may optically display image content or amplify image light received from display electronics 122 (e.g., using an optical waveguide and coupler), correct optical errors associated with the image light, and present the corrected image light to a user of near-eye display 120. In various embodiments, display optics 124 may include one or more optical elements, such as a substrate, an optical waveguide, an aperture, a fresnel lens, a convex lens, a concave lens, a filter, an input/output coupler, or any other suitable optical element that may affect image light emitted from display electronics 122. Display optics 124 may include a combination of different optical elements and mechanical coupling to maintain the relative spacing and orientation of the optical elements in the combination. One or more optical elements in display optics 124 may have an optical coating, such as an anti-reflective coating, a filter coating, or a combination of different optical coatings.

The magnification of the image light by the display optics 124 may allow the display electronics 122 to be physically smaller, lighter in weight, and consume less power than larger displays. In addition, magnification may increase the field of view of the display content. The magnification of the image light by the display optics 124 may be changed by adjusting, adding optical elements, or removing optical elements from the display optics 124. In some embodiments, display optics 124 may project the displayed image to one or more image planes that may be farther from the user's eye than near-eye display 120.

The display optics 124 may also be designed to correct one or more types of optical errors, such as two-dimensional optical errors, three-dimensional optical errors, or any combination thereof. The two-dimensional error may include an optical aberration (optical aberration) occurring in two dimensions. Example types of two-dimensional errors may include barrel distortion, pincushion distortion (pincushion distortion), longitudinal chromatic aberration, and lateral chromatic aberration. The three-dimensional error may include an optical error that occurs in three dimensions. Example types of three-dimensional errors may include spherical aberration (spherical aberration), coma (comatic aberration), field curvature (field curvature), and astigmatism (astigmatism).

The localizers 126 may be objects that are located at specific locations on the near-eye display 120 relative to each other and relative to a reference point on the near-eye display 120. In some implementations, the console 110 may identify the locator 126 in an image captured by the external imaging device 150 to determine the location, orientation, or both the location and orientation of the artificial reality headset. The locator 126 may be an LED, a pyramidal prism (corner cube reflector), reflective markers, a light source that contrasts with the environment in which the near-eye display 120 operates, or any combination thereof. In embodiments where the locator 126 is an active component (e.g., an LED or other type of light emitting device), the locator 126 may emit light in the visible light band (e.g., about 380nm to 750 nm), in the Infrared (IR) band (e.g., about 750nm to 1 mm), in the ultraviolet band (e.g., about 10nm to about 380 nm), in another portion of the electromagnetic spectrum, or in any combination of portions of the electromagnetic spectrum.

The external imaging device 150 may include one or more cameras, one or more video cameras, any other device capable of capturing images including one or more positioners 126, or any combination thereof. Further, the external imaging device 150 may include one or more filters (e.g., to increase signal-to-noise ratio). The external imaging device 150 may be configured to detect light emitted or reflected from the locator 126 in the field of view of the external imaging device 150. In embodiments where the locators 126 include passive elements (e.g., retroreflectors), the external imaging device 150 may include a light source that illuminates some or all of the locators 126, which may retroreflect light to the light source in the external imaging device 150. The slow calibration data may be transmitted from the external imaging device 150 to the console 110, and the external imaging device 150 may receive one or more calibration parameters from the console 110 to adjust one or more imaging parameters (e.g., focal length, focus, frame rate, sensor temperature, shutter speed, aperture, etc.).

The position sensor 128 may generate one or more measurement signals in response to movement of the near-eye display 120. Examples of the position sensor 128 may include an accelerometer, a gyroscope, a magnetometer, other motion detection or error correction sensors, or any combination thereof. For example, in some embodiments, the position sensor 128 may include a plurality of accelerometers for measuring translational (e.g., forward/backward, up/down, or left/right) motion and a plurality of gyroscopes for measuring rotational motion (e.g., pitch, yaw, or roll). In some embodiments, the individual position sensors may be oriented orthogonal to each other.

The IMU 132 may be an electronic device that generates fast calibration data based on measurement signals received from one or more position sensors 128. The position sensor 128 may be located external to the IMU 132, internal to the IMU 132, or any combination thereof. Based on one or more measurement signals from the one or more position sensors 128, the IMU 132 may generate rapid calibration data indicative of an estimated position of the near-eye display 120 relative to an initial position of the near-eye display 120. For example, IMU 132 may integrate the measurement signals received from the accelerometer over time to estimate a velocity vector and integrate the velocity vector over time to determine an estimated location of a reference point on near-eye display 120. Alternatively, the IMU 132 may provide sampled measurement signals to the console 110, and the console 110 may determine quick calibration data. While the reference point may generally be defined as a point in space, in various embodiments, the reference point may also be defined as a point within the near-eye display 120 (e.g., the center of the IMU 132).

The eye tracking unit 130 may comprise one or more eye tracking systems. Eye tracking may refer to determining the position of the eye relative to the near-eye display 120, including the orientation and positioning of the eye. The eye tracking system may include an imaging system that images one or more eyes, and may optionally include a light emitter that may generate light directed toward the eyes such that light reflected by the eyes may be captured by the imaging system. For example, the eye tracking unit 130 may include an incoherent or coherent light source (e.g., a laser diode) that emits light in the visible or infrared spectrum and a camera that captures light reflected by the user's eye. As another example, eye tracking unit 130 may capture reflected radio waves emitted by a miniature radar unit. The eye tracking unit 130 may use low power light emitters that emit light at a frequency and intensity that does not harm the eye or cause physical discomfort. The eye tracking unit 130 may be arranged to increase the contrast of the eye image captured by the eye tracking unit 130 while reducing the total power consumed by the eye tracking unit 130 (e.g. reducing the power consumed by the light emitters and imaging systems included in the eye tracking unit 130). For example, in some embodiments, the eye tracking unit 130 may consume less than 100 milliwatts of power.

For example, near-eye display 120 may use the orientation of the eye to: determining the user's inter-pupillary distance (IPD), determining gaze direction, introducing depth cues (e.g., blurring images outside of the user's main line of sight), collecting heuristic information (heuristics) about user interactions in VR media (e.g., time spent on any particular subject, object, or frame according to the stimulus experienced), some other function based at least in part on the orientation of at least one user's eyes, or any combination thereof. Because the orientation may be determined for both eyes of the user, the eye tracking unit 130 may determine where the user is looking. For example, determining the direction of the user gaze may include determining a rendezvous point (point of convergence) based on the determined orientations of the left and right eyes of the user. The collection point may be the point at which two foveal axes (foveal axes) of the user's eyes intersect. The direction of the user's gaze may be a direction of a line passing through the integration point and the midpoint between the pupils of the user's eyes.

The input/output interface 140 may be a device that allows a user to send an action request to the console 110. An action request may be a request to perform a particular action. For example, an action request may be to start or end an application or to perform a particular action within an application. Input/output interface 140 may include one or more input devices. Example input devices may include a keyboard, mouse, game controller, glove, button, touch screen, or any other suitable device for receiving action requests and transmitting the received action requests to console 110. The action request received by the input/output interface 140 may be transmitted to the console 110, and the console 110 may perform an action corresponding to the requested action. In some embodiments, the input/output interface 140 may provide haptic feedback to the user in accordance with instructions received from the console 110. For example, the input/output interface 140 may provide haptic feedback when an action request is received, or when the console 110 has performed a requested action and transmitted instructions to the input/output interface 140. In some embodiments, the external imaging device 150 may be used to track the input/output interface 140, such as a tracking controller (which may include, for example, an IR light source) or the position or location of the user's hand to determine the user's actions. In some embodiments, the near-eye display 120 may include one or more imaging devices to track the input/output interface 140, such as tracking the position or location of the controller or the user's hand to determine the user's motion.

The console 110 may provide content to the near-eye display 120 for presentation to a user based on information received from one or more of the external imaging device 150, the near-eye display 120, and the input/output interface 140. In the example shown in fig. 1, the console 110 may include an application store 112, a headset tracking module 114, an artificial reality engine 116, and an eye tracking module 118. Some embodiments of console 110 may include different or additional modules than those described in connection with fig. 1. The functions described further below may be distributed among the components of console 110 in a manner different from that described herein.

In some embodiments, the console 110 may include a processor and a non-transitory computer readable storage medium storing instructions executable by the processor. A processor may include multiple processing units that execute instructions in parallel. The non-transitory computer readable storage medium may be any memory, such as a hard disk drive, removable memory, or solid state drive (e.g., flash memory or Dynamic Random Access Memory (DRAM)). In various embodiments, the modules of console 110 described in connection with fig. 1 may be encoded as instructions in a non-transitory computer-readable storage medium that, when executed by a processor, cause the processor to perform the functions described further below.

The application storage 112 may store one or more applications for execution by the console 110. The application may include a set of instructions that, when executed by the processor, generate content for presentation to a user. The application-generated content may be responsive to input received from a user via movement of the user's eyes or input received from the input/output interface 140. Examples of applications may include: a gaming application, a conferencing application, a video playback application, or other suitable application.

The headset tracking module 114 may use slow calibration information from the external imaging device 150 to track the movement of the near-eye display 120. For example, the headset tracking module 114 may use the observed locator from the slow calibration information and a model of the near-eye display 120 to determine the location of the reference point of the near-eye display 120. The headset tracking module 114 may also use position information from the quick calibration information to determine the position of the reference point of the near-eye display 120. Additionally, in some embodiments, the headset tracking module 114 may use portions of the fast calibration information, the slow calibration information, or any combination thereof to predict the future position of the near-eye display 120. The headset tracking module 114 may provide the estimated or predicted future position of the near-eye display 120 to the artificial reality engine 116.

The artificial reality engine 116 may execute an application within the artificial reality system environment 100 and receive the position information of the near-eye display 120, the acceleration information of the near-eye display 120, the velocity information of the near-eye display 120, the predicted future position of the near-eye display 120, or any combination thereof from the headset tracking module 114. The artificial reality engine 116 may also receive estimated eye position and orientation information from the eye tracking module 118. Based on the received information, the artificial reality engine 116 may determine content provided to the near-eye display 120 for presentation to the user. For example, if the received information indicates that the user has seen to the left, the artificial reality engine 116 may generate content for the near-eye display 120 that reflects (mirror) the movement of the user's eyes in the virtual environment. In addition, the artificial reality engine 116 may perform actions within applications executing on the console 110 in response to action requests received from the input/output interface 140 and provide feedback to the user indicating that the actions have been performed. The feedback may be visual or audible feedback via the near-eye display 120, or tactile feedback via the input/output interface 140.

The eye tracking module 118 may receive eye tracking data from the eye tracking unit 130 and determine a position of the user's eye based on the eye tracking data. The position of the eye may include an orientation, a position, or both an orientation and a position of the eye relative to the near-eye display 120 or any element thereof. Because the rotational axis of the eye changes according to the positioning of the eye in its orbital, determining the positioning of the eye in its orbital may allow the eye tracking module 118 to more accurately determine the orientation of the eye.

Fig. 2 is a perspective view of an example of a near-eye display in the form of an HMD device 200 for implementing some of the examples disclosed herein. The HMD device 200 may be part of, for example, a VR system, an AR system, an MR system, or any combination thereof. HMD device 200 may include a body 220 and a headband 230. Fig. 2 shows the bottom side 223, front side 225, and left side 227 of the body 220 in perspective. Headband 230 may have an adjustable or extendable length. There may be sufficient space between the body 220 and the headband 230 of the HMD device 200 to allow a user to mount the HMD device 200 to the user's head. In various embodiments, HMD device 200 may include additional, fewer, or different components. For example, in some embodiments, the HMD device 200 may include, for example, temples (eye temples) and temple ends (temples tips) as shown below in fig. 3, instead of the headband 230.

The HMD device 200 may present media to a user that includes virtual and/or enhanced views of a physical, real-world environment with computer-generated elements. Examples of media presented by the HMD device 200 may include images (e.g., two-dimensional (2D) or three-dimensional (3D) images), video (e.g., 2D or 3D video), audio, or any combinations thereof. The images and video may be presented to each eye of the user through one or more display components (not shown in fig. 2) encapsulated in the body 220 of the HMD device 200. In various embodiments, the one or more display components may include a single electronic display panel or multiple electronic display panels (e.g., one display panel for each eye of a user). For example, examples of electronic display panels may include an LCD, an OLED display, an ILED display, a μled display, an AMOLED, a TOLED, some other display, or any combination thereof. The HMD device 200 may include two window (eye box) areas.

In some implementations, the HMD device 200 may include various sensors (not shown), such as a depth sensor, a motion sensor, a position sensor, and an eye tracking sensor. Some of these sensors may use structured light patterns for sensing. In some implementations, the HMD device 200 may include an input/output interface for communicating with a console. In some implementations, the HMD device 200 may include a virtual reality engine (not shown) that may execute applications within the HMD device 200 and receive depth information, position information, acceleration information, velocity information, predicted future positions, or any combinations thereof, of the HMD device 200 from various sensors. In some implementations, information received by the virtual reality engine can be used to generate signals (e.g., display instructions) to one or more display components. In some implementations, the HMD device 200 may include locators (not shown, such as the locator 126) that are fixed positions on the body 220 relative to each other and relative to a reference point. Each locator may emit light that is detectable by an external imaging device.

Fig. 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. Near-eye display 300 may be a particular embodiment of near-eye display 120 of fig. 1 and may be configured to operate as a virtual reality display, an augmented reality display, and/or a mixed reality display. Near-eye display 300 may include a frame 305 and a display 310. The display 310 may be configured to present content to a user. In some embodiments, display 310 may include display electronics and/or display optics. For example, as described above with respect to near-eye display 120 of fig. 1, display 310 may include an LCD display panel, an LED display panel, or an optical display panel (e.g., a waveguide display assembly).

The near-eye display 300 may also include various sensors 350a, 350b, 350c, 350d, and 350e on the frame 305 or within the frame 305. In some embodiments, the sensors 350a-350e may include one or more depth sensors, motion sensors, position sensors, inertial sensors, or ambient light sensors. In some embodiments, the sensors 350a-350e may include one or more image sensors configured to generate image data representing different fields of view in different directions. In some embodiments, the sensors 350a-350e may be used as input devices to control or affect the display content of the near-eye display 300 and/or to provide an interactive VR/AR/MR experience to a user of the near-eye display 300. In some embodiments, the sensors 350a-350e may also be used for stereoscopic imaging.

In some embodiments, the near-eye display 300 may also include one or more illuminators 330 to project light into the physical environment. The projected light may be associated with different frequency bands (e.g., visible light, infrared light, ultraviolet light, etc.), and may be used for various purposes. For example, illuminator 330 may project light in a dark environment (or in an environment with low intensity infrared light, ultraviolet light, etc.) to help sensors 350a-350e capture images of different objects within the dark environment. In some embodiments, the illuminator 330 may be used to project a particular light pattern onto an object within the environment. In some embodiments, illuminator 330 may be used as a locator, such as locator 126 described above with reference to fig. 1.

In some embodiments, the near-eye display 300 may also include a high resolution camera 340. The camera 340 may capture an image of the physical environment in the field of view. For example, the captured image may be processed by a virtual reality engine (e.g., artificial reality engine 116 of fig. 1) to add virtual objects to the captured image or modify physical objects in the captured image, and the processed image may be displayed to a user by display 310 for an AR or MR application.

Fig. 4 illustrates an example of an optical perspective augmented reality system 400 including a waveguide display, in accordance with certain embodiments. The augmented reality system 400 may include a projector 410 and a combiner 415. Projector 410 may include a light source or image source 412 and projector optics 414. In some embodiments, the light source or image source 412 may include one or more of the micro LED devices described above. In some embodiments, the image source 412 may include a plurality of pixels, such as an LCD display panel or an LED display panel, that display the virtual object. In some embodiments, the image source 412 may include a light source that generates coherent or partially coherent light. For example, the image source 412 may include a laser diode, a vertical cavity surface emitting laser, an LED, and/or micro LEDs described above. In some embodiments, the image source 412 may include a plurality of light sources (e.g., micro LED arrays described above), each light source emitting monochromatic image light corresponding to a primary color (e.g., red, green, or blue). In some embodiments, the image source 412 may include three two-dimensional arrays of micro-LEDs, where each two-dimensional array of micro-LEDs may include micro-LEDs configured to emit primary (e.g., red, green, or blue) light. In some embodiments, the image source 412 may include an optical pattern generator, such as a spatial light modulator. Projector optics 414 may include one or more optical components that may condition light from image source 412, such as expanding, collimating, scanning light from image source 412, or projecting light from image source 412 to combiner 415. For example, the one or more optical components may include one or more lenses, liquid lenses, mirrors, apertures, and/or gratings. For example, in some embodiments, the image source 412 may include one or more one-dimensional arrays or elongated two-dimensional arrays of micro-LEDs, and the projector optics 414 may include one or more one-dimensional scanners (e.g., micro-mirrors or prisms) configured to scan the one-dimensional arrays or elongated two-dimensional arrays of micro-LEDs to generate image frames. In some embodiments, projector optics 414 may include a liquid lens (e.g., a liquid crystal lens) having a plurality of electrodes that allow scanning of light from image source 412.

Combiner 415 may include an input coupler 430 for coupling light from projector 410 into a substrate 420 of combiner 415. Combiner 415 may transmit at least 50% of light in the first wavelength range and reflect at least 25% of light in the second wavelength range. For example, the first wavelength range may be visible light from about 400nm to about 650nm, while the second wavelength range may be in the infrared band, e.g., from about 800nm to about 1000nm. The input coupler 430 may include a volume holographic grating, a Diffractive Optical Element (DOE) (e.g., a surface relief grating), an angled surface of the substrate 420, or a refractive coupler (e.g., a wedge (wedge) or prism). The input coupler 430 may have a coupling efficiency for visible light of greater than 30%, 50%, 75%, 90% or more. Light coupled into the substrate 420 may propagate within the substrate 420 by, for example, total Internal Reflection (TIR). The substrate 420 may be in the form of a lens of a pair of eyeglasses. The substrate 420 may have a flat or curved surface and may include one or more types of dielectric materials such as glass, quartz, plastic, polymer, polymethyl methacrylate (PMMA), crystal, or ceramic. The thickness of the substrate may be in the range of, for example, less than about 1mm to about 10mm or more. The substrate 420 may be transparent to visible light.

The substrate 420 may include or may be coupled to a plurality of output couplers 440, the plurality of output couplers 440 configured to extract at least a portion of the light guided by the substrate 420 and propagating within the substrate 420 from the substrate 420 and to guide the extracted light 460 to an eye 490 of a user of the augmented reality system 400. Like input coupler 430, output coupler 440 may include a grating coupler (e.g., a volume hologram grating or a surface relief grating), other DOEs, prisms, and the like. The output coupler 440 may have different coupling (e.g., diffraction) efficiencies at different locations. The substrate 420 may also allow light 450 from the environment in front of the combiner 415 to pass through with little or no loss. The output coupler 440 may also allow light 450 to pass through with little loss. For example, in some embodiments, the output coupler 440 may have a low diffraction efficiency for the light 450 such that the light 450 may be refracted or otherwise pass through the output coupler 440 with little loss, and thus may have a higher intensity than the extracted light 460. In some implementations, the output coupler 440 may have a high diffraction efficiency for the light 450 and may diffract the light 450 into a particular desired direction (i.e., diffraction angle) with little loss. Thus, the user may view the combined image of the environment in front of combiner 415 and the virtual object projected by projector 410.

Fig. 5A illustrates an example of a near-eye display (NED) device 500 including a waveguide display 530, in accordance with certain embodiments. NED device 500 may be an example of a near-eye display 120, an augmented reality system 400, or another type of display device. NED device 500 may include a light source 510, projection optics 520, and a waveguide display 530. The light source 510 may include multiple light emitter panels for different colors, such as a red light emitter 512 panel, a green light emitter 514 panel, and a blue light emitter 516 panel. Red light emitters 512 are organized into an array; the green light emitters 514 are organized into an array; and blue light emitters 516 are organized in an array. The size and spacing of the light emitters in the light source 510 may be small. For example, each light emitter may have a diameter of less than 2 μm (e.g., about 1.2 μm) and the pitch may be less than 2 μm (e.g., about 1.5 μm). Accordingly, the number of light emitters in each of red light emitter 512, green light emitter 514, and blue light emitter 516 may be equal to or greater than the number of pixels in the display image, such as 960×720, 1280×720, 1440×1080, 1920×1080, 2160×1080, or 2560×1080 pixels. Thus, the display images may be generated simultaneously by the light sources 510. No scanning element may be used in NED device 500.

The light emitted by the light source 510 may be conditioned by projection optics 520 before reaching the waveguide display 530, and the projection optics 520 may include a lens array. Projection optics 520 may collimate or focus light emitted by light source 510 into waveguide display 530, and waveguide display 530 may include coupler 532, coupler 532 for coupling light emitted by light source 510 into waveguide display 530. Light coupled into waveguide display 530 may propagate within waveguide display 530 by, for example, total internal reflection as described above with reference to fig. 4. Coupler 532 may also couple out a portion of the light propagating within waveguide display 530 from waveguide display 530 and toward user's eye 590.

Fig. 5B illustrates an example of a near-eye display (NED) device 550 including a waveguide display 580, according to a particular embodiment. In some embodiments, NED device 550 may use scanning mirror 570 to project light from light source 540 to an image field in which user eye 590 may be located. NED device 550 may be an example of a near-eye display 120, an augmented reality system 400, or another type of display device. The light sources 540 may include one or more rows or one or more columns of differently colored light emitters, such as a plurality of rows of red light emitters 542, a plurality of rows of green light emitters 544, and a plurality of rows of blue light emitters 546. For example, red light emitter 542, green light emitter 544, and blue light emitter 546 may each include N rows, each row including, for example, 2560 light emitters (pixels). Red light emitters 542 are organized into an array; the green light emitters 544 are organized into an array; and blue light emitters 546 are organized into an array. In some embodiments, the light source 540 may include a single row of light emitters for each color. In some embodiments, the light source 540 may include multiple columns of light emitters for each of the colors red, green, and blue, where each column may include, for example, 1080 light emitters. In some embodiments, the size and/or spacing of the light emitters in light source 540 may be relatively large (e.g., about 3 μm-5 μm), and thus light source 540 may not include enough light emitters for generating a complete display image simultaneously. For example, the number of light emitters for a single color may be less than the number of pixels in the display image (e.g., 2560×1080 pixels). The light emitted by the light source 540 may be a set of collimated or divergent light beams.

The light emitted by the light source 540 may be modulated by various optics, such as a collimating lens or free-form surface optical element (freeform optical element) 560, before reaching the scanning mirror 570. The freeform optical element 560 may include, for example, a faceted prism or another light folding element that may direct light emitted by the light source 540 toward the scanning mirror 570, such as to change the direction of propagation of the light emitted by the light source 540, for example, by about 90 ° or more. In some embodiments, the free-form surface optical element 560 may be rotatable to scan light. The scanning mirror 570 and/or the freeform optical element 560 may reflect and project light emitted by the light source 540 to the waveguide display 580, and the waveguide display 580 may include a coupler 582, the coupler 582 being configured to couple light emitted by the light source 540 into the waveguide display 580. Light coupled into waveguide display 580 may propagate within waveguide display 580 by total internal reflection, such as described above with reference to fig. 4. Coupler 582 may also couple a portion of the light propagating within waveguide display 580 out of waveguide display 580 and toward user's eye 590.

Scanning mirror 570 may comprise a microelectromechanical system (MEMS) mirror or any other suitable mirror. The scanning mirror 570 may be rotated to scan in one or two dimensions. As the scanning mirror 570 rotates, light emitted by the light source 540 may be directed to different areas of the waveguide display 580 such that a complete display image may be projected onto the waveguide display 580 and directed by the waveguide display 580 to the user's eye 590 during each scanning cycle. For example, in embodiments where light source 540 includes light emitters for all pixels in one or more rows or one or more columns, scanning mirror 570 may be rotated in a column or row direction (e.g., x or y direction) to scan an image. In embodiments where light source 540 includes light emitters for some, but not all, of the pixels in one or more rows or one or more columns, scanning mirror 570 may be rotated in both the row and column directions (e.g., both the x and y directions) to project a display image (e.g., using a raster scan pattern (ras-type scanning pattern)).

NED device 550 may operate in a predefined display period. A display period (e.g., a display cycle) may refer to the duration in which a complete image is scanned or projected. For example, the display period may be the inverse of the desired frame rate. In NED device 550, which includes scanning mirror 570, the display period may also be referred to as a scanning period or scanning cycle. The light generated by the light source 540 may be synchronized with the rotation of the scanning mirror 570. For example, each scanning cycle may include multiple scanning steps, wherein the light source 540 may generate a different light pattern in each respective scanning step.

During each scan cycle, a display image may be projected onto waveguide display 580 and user's eye 590 as scan mirror 570 rotates. The actual color value and light intensity (e.g., brightness) of a given pixel location of a display image may be the average of the light beams of the three colors (e.g., red, green, and blue) illuminating that pixel location during the scan period. After one scan cycle is completed, the scan mirror 570 may be returned to the original position to project light for the first few lines of the next display image, or may be rotated or scanned in reverse to project light for the next display image, wherein a new set of drive signals may be fed to the light sources 540. The same process may be repeated as the scanning mirror 570 rotates in each scanning cycle. Thus, different images may be projected onto the user's eye 590 in different scan cycles.

Fig. 6 illustrates an example of an image source component 610 in a near-eye display system 600, in accordance with certain embodiments. For example, the image source component 610 may include: a display panel 640 that can generate a display image to be projected to the eyes of a user; and projector 650 that can project a display image generated by display panel 640 onto a waveguide display as described above with reference to fig. 4-5B. The display panel 640 may include a light source 642 and a driver circuit 644 for the light source 642. For example, light source 642 may comprise light source 510 or 540. For example, projector 650 may include free-form surface optics 560, scanning mirror 570, and/or projection optics 520 described above. The near-eye display system 600 may also include a controller 620 that synchronously controls the light source 642 and the projector 650 (e.g., scanning mirror 570). The image source component 610 may generate and output image light to a waveguide display (not shown in fig. 6), such as waveguide display 530 or 580. As described above, the waveguide display may receive image light at one or more input coupling elements and direct the received image light to one or more output coupling elements. The input and output coupling elements may comprise, for example, diffraction gratings, holographic gratings, prisms, or any combination thereof. The input coupling element may be selected such that total internal reflection occurs for the waveguide display. The output coupling element may couple out a portion of the totally internally reflected image light from the waveguide display.

As described above, the light source 642 may include a plurality of light emitters arranged in an array or matrix. Each light emitter may emit monochromatic light, such as red, blue, green, infrared, etc. Although RGB colors are often discussed in this disclosure, the embodiments described herein are not limited to using red, green, and blue as primary colors. Other colors may also be used as primary colors for the near-eye display system 600. In some embodiments, the display panel according to an embodiment may use more than three primary colors. Each pixel in the light source 642 may include three sub-pixels including a red micro LED, a green micro LED, and a blue micro LED. Semiconductor LEDs typically include an active light emitting layer within multiple layers of semiconductor material. The multiple layers of semiconductor material may comprise different composite materials or the same base material with different dopants and/or different doping densities. For example, the multi-layer semiconductor material may include an n-type material layer, an active region that may include a heterostructure (e.g., one or more quantum wells), and a p-type material layer. Multiple layers of semiconductor material may be grown on the surface of a substrate having a particular orientation. In some embodiments, to increase light extraction efficiency, mesas may be formed that include at least some layers of semiconductor material.

The controller 620 may control image rendering operations of the image source component 610, such as operations of the light sources 642 and/or the projector 650. For example, the controller 620 may determine instructions for the image source component 610 to render one or more display images. The instructions may include display instructions and scan instructions. In some embodiments, the display instructions may include image files (e.g., bitmap files). For example, the display instructions may be received from a console (such as console 110 described above with reference to FIG. 1). The image source component 610 can generate image light using the scan instructions. For example, the scan instructions may specify the type of image light source (e.g., monochromatic or polychromatic), the scan rate, the orientation of the scanning device, one or more illumination parameters, or any combination thereof. The controller 620 may include a combination of hardware, software, and/or firmware that is not shown here to avoid obscuring other aspects of the disclosure.

In some embodiments, the controller 620 may be a Graphics Processing Unit (GPU) of the display device. In other embodiments, the controller 620 may be other kinds of processors. Operations performed by the controller 620 may include retrieving content for display and dividing the content into discrete portions. The controller 620 may provide scan instructions to the light sources 642 including addresses of individual source elements corresponding to the light sources 642 and/or electrical bias applied to the individual source elements. The controller 620 may instruct the light sources 642 to sequentially present discrete portions using light emitters corresponding to one or more rows of pixels in an image that is ultimately displayed to a user. The controller 620 may also instruct the projector 650 to perform different adjustments to the light. For example, the controller 620 may control the projector 650 to scan the discrete portions to different regions of the coupling element of the waveguide display (e.g., waveguide display 580) as described above with reference to fig. 5B. Thus, at the exit pupil (exit pupil) of the waveguide display, each discrete portion is presented at a different respective position. Although each discrete portion is presented at a different respective time, the presentation and scanning of the discrete portions occurs fast enough that the user's eyes can integrate the different portions into a single image or a series of images.

The image processor 630 may be a general purpose processor and/or one or more special purpose circuits dedicated to performing the features described herein. In one embodiment, a general purpose processor may be coupled to a memory to execute software instructions that cause the processor to perform the specific processes described herein. In another embodiment, image processor 630 may be one or more circuits dedicated to performing particular features. Although the image processor 630 in fig. 6 is shown as a separate unit from the controller 620 and the driver circuit 644, in other embodiments, the image processor 630 may be a subunit of the controller 620 or the driver circuit 644. In other words, in these embodiments, the controller 620 or the driver circuit 644 may perform various image processing functions of the image processor 630. The image processor 630 may also be referred to as an image processing circuit.

In the example shown in fig. 6, the light source 642 may be driven by a driver circuit 644 based on data or instructions (e.g., display and scan instructions) sent from the controller 620 or the image processor 630. In one embodiment, the driver circuit 644 may include a circuit board connected to and mechanically holding the individual light emitters of the light sources 642. The light sources 642 may emit light according to one or more illumination parameters set by the controller 620 and potentially adjusted by the image processor 630 and driver circuit 644. The light source 642 may use illumination parameters to generate light. For example, the illumination parameters may include a source wavelength, a pulse rate, a pulse amplitude, a beam type (continuous or pulsed), one or more other parameters that may affect the emitted light, or any combination thereof. In some embodiments, the source light generated by light source 642 may include multiple beams of red, green, and blue light, or any combination thereof.

Projector 650 may perform a set of optical functions such as focusing, combining, adjusting, or scanning image light generated by light source 642. In some embodiments, projector 650 may include a combination assembly, a light conditioning assembly, or a scanning mirror assembly. Projector 650 may include one or more optical components that optically condition and potentially redirect light from light source 642. One example of an adjustment of the light may include adjusting the light, such as expanding, collimating, correcting one or more optical errors (e.g., field curvature, chromatic aberration, etc.), some other adjustment of the light, or any combination thereof. For example, the optical components of projector 650 may include lenses, mirrors, apertures, gratings, or any combination thereof.

Projector 650 may redirect image light via one or more reflective and/or refractive portions thereof such that the image light is projected in a particular orientation toward a waveguide display. The location toward which the image light is redirected may depend on the particular orientation of the one or more reflective and/or refractive portions. In some embodiments, projector 650 includes a single scanning mirror that scans in at least two dimensions. In other embodiments, projector 650 may include multiple scanning mirrors, each scanning in a direction orthogonal to each other. Projector 650 may perform (horizontal or vertical) raster scanning, dual resonance scanning, or any combination thereof. In some embodiments, projector 650 may perform controlled vibrations in horizontal and/or vertical directions at a particular oscillation frequency to scan in two dimensions and generate a two-dimensional projection image of the media presented to the user's eyes. In other embodiments, projector 650 may include a lens or prism that may be used for similar or identical functions as one or more scanning mirrors. In some embodiments, image source assembly 610 may not include a projector, where light emitted by light source 642 may be directly incident on a waveguide display.

Fig. 7A illustrates an example of an LED 700 with a vertical mesa structure. LED 700 may be a light emitter in light source 510, 540, or 642. The LED 700 may be a micro LED made of an inorganic material such as a multi-layered semiconductor material. The layered semiconductor light emitting device may include multiple layers of III-V semiconductor materials. The group III-V semiconductor material may include one or more group III elements, such As aluminum (Al), gallium (Ga), or indium (In), in combination with a group V element, such As nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). When the group V element of the group III-V semiconductor material includes nitrogen, the group III-V semiconductor material is referred to as a group III nitride material. The layered semiconductor light emitting device may be manufactured by growing a plurality of epitaxial layers on a substrate using a technique such as Vapor Phase Epitaxy (VPE), liquid Phase Epitaxy (LPE), molecular Beam Epitaxy (MBE), or Metal Organic Chemical Vapor Deposition (MOCVD). For example, the substrate may be in a particular lattice orientation (e.g., polar, nonpolar, or semipolar orientation), such as a GaN, gaAs, or GaP substrate, or in a substrate including, but not limited to, sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate (lithium gallate), partially substituted spinel, or shared β -LiAlO ₂ Growing a semiconductor material layer by layer on a substrate of a quaternary tetragonal oxide (quaternary tetragonal oxides) of the structure, whereinThe substrate may be cut in a specific direction to expose a specific plane as a growth surface.

In the example shown in fig. 7A, the LED 700 may include a substrate 710, which may include, for example, a sapphire substrate or a GaN substrate. The semiconductor layer 720 may be grown on the substrate 710. The semiconductor layer 720 may include a group III-V material (such as GaN) and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One or more active layers 730 may be grown on the semiconductor layer 720 to form an active region. The active layer 730 may include a III-V material (such as one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers) that may form one or more heterostructures, such as one or more quantum wells or MQWs. The semiconductor layer 740 may be grown on the active layer 730. The semiconductor layer 740 may include a group III-V material (such as GaN) and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One of the semiconductor layer 720 and the semiconductor layer 740 may be a p-type layer and the other may be an n-type layer. The semiconductor layer 720 and the semiconductor layer 740 sandwich the active layer 730 to form a light emitting region. For example, the LED 700 may include an InGaN layer between a p-type GaN layer doped with magnesium and an n-type GaN layer doped with silicon or oxygen. In some embodiments, the LED 700 may include an AlInGaP layer between a p-type AlInGaP layer doped with zinc or magnesium and an n-type AlInGaP layer doped with selenium, silicon, or tellurium.

In some embodiments, an Electron Blocking Layer (EBL) (not shown in fig. 7A) may be grown to form a layer between the active layer 730 and at least one of the semiconductor layer 720 or the semiconductor layer 740. The EBL may reduce electron leakage current and increase the efficiency of the LED. In some embodiments, heavily doped semiconductor layer 750 (such as P ⁺ Or P ⁺⁺ A semiconductor layer) may be formed on the semiconductor layer 740 and act as a contact layer for forming ohmic contacts and reducing the contact resistance of the device. In some embodiments, conductive layer 760 may be formed on heavily doped semiconductor layer 750. The conductive layer 760 may include, for example, indium Tin Oxide (ITO) or an Al/Ni/Au film. In one example, conductive layer 760 may beTo include a transparent ITO layer.

In order to contact the semiconductor layer 720 (e.g., n-GaN layer) and more efficiently extract light emitted by the active layer 730 from the LED 700, the semiconductor material layers (including the heavily doped semiconductor layer 750, the semiconductor layer 740, the active layer 730, and the semiconductor layer 720) may be etched to expose the semiconductor layer 720 and form a mesa structure including the layers 720-760. The mesa structure may confine carriers within the device. Etching the mesa structure may result in formation of mesa sidewalls 732 that may be orthogonal to the growth plane. A passivation layer 770 may be formed on the sidewalls 732 of the mesa structure. The passivation layer 770 may include an oxide layer, such as SiO ₂ A layer, and may act as a reflector to reflect emitted light away from LED 700. The contact layer 780 may include a metal layer (such as Al, au, ni, ti or any combination thereof), and the contact layer 780 may be formed on the semiconductor layer 720 and may serve as an electrode of the LED 700. In addition, another contact layer 790 (such as an Al/Ni/Au metal layer) may be formed on the conductive layer 760 and may serve as another electrode of the LED 700.

When a voltage signal is applied to the contact layers 780 and 790, electrons and holes may recombine in the active layer 730, wherein the recombination of electrons and holes may cause photon emission. The wavelength and energy of the emitted photons may depend on the band gap between the valence and conduction bands in the active layer 730. For example, the InGaN active layer may emit green light or blue light, the AlGaN active layer may emit blue to ultraviolet light, and the AlInGaP active layer may emit red, orange, yellow, or green light. The emitted photons may be reflected by the passivation layer 770 and may exit the LED700 from the top (e.g., conductive layer 760 and contact layer 790) or the bottom (e.g., substrate 710).

In some embodiments, the LED700 may include one or more other components (such as lenses) on a light emitting surface (such as the substrate 710) to focus or collimate the emitted light or couple the emitted light into a waveguide. In some embodiments, the LED may include a mesa of another shape (such as planar, conical, semi-parabolic, or parabolic), and the base area (base area) of the mesa may be circular, rectangular, hexagonal, or triangular. For example, the LEDs may include mesas of curved shape (e.g., parabolic shape) and/or non-curved shape (e.g., conical shape). The mesa may be truncated or not.

Fig. 7B is a cross-sectional view of an example of an LED 705 having a parabolic mesa structure. Similar to LED 700, LED 705 may include multiple layers of semiconductor material, such as multiple layers of group III-V semiconductor material. A layer of semiconductor material may be epitaxially grown on a substrate 715, such as a GaN substrate or a sapphire substrate. For example, semiconductor layer 725 may be grown on substrate 715. Semiconductor layer 725 may comprise a group III-V material (such as GaN) and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One or more active layers 735 may be grown on semiconductor layer 725. The active layer 735 may include a III-V material (such as one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers) that may form one or more heterostructures, such as one or more quantum wells. Semiconductor layer 745 may be grown on active layer 735. Semiconductor layer 745 may comprise a group III-V material such as GaN and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One of semiconductor layer 725 and semiconductor layer 745 may be a p-type layer and the other may be an n-type layer.

In order to contact the semiconductor layer 725 (e.g., an n-type GaN layer) and more efficiently extract light emitted by the active layer 735 from the LED 705, the semiconductor layer may be etched to expose the semiconductor layer 725 and form a mesa structure including layers 725-745. The mesa structure may confine carriers within the injection region of the device. Etching the mesa structure may result in formation of mesa sidewalls (also referred to herein as facets) that may be non-parallel, or in some cases orthogonal, to the growth planes associated with the crystal growth of layers 725-745.

As shown in fig. 7B, LED 705 may have a mesa structure that includes a mesa. Dielectric layer 775 (e.g., siO ₂ Or SiN _x ) May be formed on the facets of the mesa structure. In some embodiments, the dielectric layer 775 may comprise multiple layers of dielectric material. In some embodiments, metal layer 795 may be formed on the dielectric layer 775. The metal layer 795 may include one or more metals or metal alloy materials, such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), copper (Cu), or any combination thereof. The dielectric layer 775 and the metal layer 795 may form a mesa reflector that may reflect light emitted by the active layer 735 toward the substrate 715. In some embodiments, the mesa reflector may be parabolic in shape to act as a parabolic reflector that may at least partially collimate the emitted light.

Electrical contacts 765 and 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to act as electrodes. The electrical contacts 765 and 785 may each comprise an electrically conductive material, such as Al, au, pt, ag, ni, ti, cu or any combination thereof (e.g., ag/Pt/Au or Al/Ni/Au), and may serve as electrodes for the LED 705. In the example shown in fig. 7B, electrical contact 785 may be an n-type contact and electrical contact 765 may be a p-type contact. The electrical contact 765 and the semiconductor layer 745 (e.g., p-type semiconductor layer) may form a back reflector (back reflector) for reflecting light emitted by the active layer 735 toward the substrate 715. In some embodiments, the electrical contact 765 and the metal layer 795 comprise the same material(s) and may be formed using the same process. In some embodiments, an additional conductive layer (not shown) may be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layer.

When a voltage signal is applied across contacts 765 and 785, electrons and holes may recombine in active layer 735. Recombination of electrons and holes may cause photon emission, thereby generating light. The wavelength and energy of the emitted photons may depend on the band gap between the valence and conduction bands in the active layer 735. For example, the InGaN active layer may emit green light or blue light, while the AlInGaP active layer may emit red, orange, yellow, or green light. The emitted photons may propagate in many different directions and may be reflected by the mesa reflector and/or back reflector and may exit the LED 705, for example, from the bottom side (e.g., substrate 715) as shown in fig. 7B. One or more other secondary optical components, such as lenses or gratings, may be formed on the light emitting surface, such as substrate 715, to focus or collimate the emitted light and/or couple the emitted light into a waveguide.

A one-dimensional or two-dimensional array of the LEDs described above may be fabricated on a wafer to form a light source (e.g., light source 642). The driver circuits (e.g., driver circuit 644) may be fabricated on a silicon wafer, for example, using a CMOS process. The LEDs and driver circuits on the wafer may be diced and then bonded together, or may be bonded at the wafer level and then diced. Various bonding techniques may be used to bond the LEDs and driver circuits, such as adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, and the like.

Fig. 8A illustrates an example of a die-to-wafer bonding method for an LED array, according to particular embodiments. In the example shown in fig. 8A, the LED array 801 may include a plurality of LEDs 807 on a carrier substrate 805. The carrier substrate 805 may comprise various materials, such as GaAs, inP, gaN, alN, sapphire, siC, si, and the like. The LED 807 may be fabricated by, for example, growing various epitaxial layers, forming mesa structures, and forming electrical contacts or electrodes prior to performing bonding. The epitaxial layers may include various materials such as GaN, inGaN, (AlGaIn) P, (AlGaIn) AsP, (AlGaIn) AsN, (AlGaIn) Pas, (Eu: inGa) N, (AlGaIn) N, and the like, and may include an N-type layer, a P-type layer, and an active layer including one or more heterostructures such as one or more quantum wells or MQWs. The electrical contacts may comprise various electrically conductive materials, such as metals or metal alloys.

The wafer 803 may include a base layer 809 having passive or active integrated circuits (e.g., driver circuits 811) fabricated thereon. The base layer 809 may comprise, for example, a silicon wafer. A driver circuit 811 may be used to control the operation of the LED 807. For example, the driver circuit for each LED 807 may include a 2T1C pixel structure having two transistors and one capacitor. Wafer 803 may also include a bonding layer 813. The bonding layer 813 may include various materials such as metal, oxide, dielectric, cuSn, auTi, and the like. In some embodiments, a patterned layer 815 may be formed on a surface of the bonding layer 813, wherein the patterned layer 815 may include a metal grid (metal grid) made of a conductive material such as Cu, ag, au, al.

The LED array 801 may be bonded to the wafer 803 via a bonding layer 813 or a patterning layer 815. For example, patterned layer 815 may include metal pads or bumps made of various materials (such as CuSn, auSn, or nanoporous Au) that may be used to align LEDs 807 in LED array 801 with corresponding driver circuits 811 on wafer 803. In one example, the LED array 801 may be oriented toward the wafer 803 until the LEDs 807 contact corresponding metal pads or bumps corresponding to the driver circuitry 811. Some or all of the LEDs 807 may be aligned with the driver circuitry 811 and then bonded to the wafer 803 via the patterned layer 815 by various bonding techniques, such as metal-to-metal bonding. After the LEDs 807 have been bonded to the wafer 803, the carrier substrate 805 may be removed from the LEDs 807.

Fig. 8B illustrates an example of a wafer-to-wafer bonding method for an LED array, according to particular embodiments. As shown in fig. 8B, the first wafer 802 may include a substrate 804, a first semiconductor layer 806, an active layer 808, and a second semiconductor layer 810. The substrate 804 may include various materials such as GaAs, inP, gaN, alN, sapphire, siC, si, and the like. The first semiconductor layer 806, the active layer 808, and the second semiconductor layer 810 may include various semiconductor materials, such as GaN, inGaN, (AlGaIn) P, (AlGaIn) AsP, (AlGaIn) AsN, (AlGaIn) Pas, (Eu: inGa) N, (AlGaIn) N, and the like. In some embodiments, the first semiconductor layer 806 may be an n-type layer and the second semiconductor layer 810 may be a p-type layer. For example, the first semiconductor layer 806 may Be an n-type doped GaN layer (e.g., doped with Si or Ge), and the second semiconductor layer 810 may Be a p-type doped GaN layer (e.g., doped with Mg, ca, zn, or Be). For example, the active layer 808 may include one or more GaN layers, one or more InGaN layers, one or more AlInGaP layers, etc., and the active layer 808 may form one or more heterostructures, such as one or more quantum wells or MQWs.

In some embodiments, the first wafer 802 may also include a bonding layer. The bonding layer 812 may include various materials such as metals, oxides, dielectrics, cuSn, auTi, and the like. In one example, bonding layer 812 may include p-type contacts and/or n-type contacts (not shown). In some embodiments, other layers may also be included on the first wafer 802, such as a buffer layer between the substrate 804 and the first semiconductor layer 806. The buffer layer may include various materials such as polycrystalline GaN or AlN. In some embodiments, a contact layer may be between the second semiconductor layer 810 and the bonding layer 812. The contact layer may comprise any suitable material for providing electrical contact to the second semiconductor layer 810 and/or the first semiconductor layer 806.

The first wafer 802 may be bonded to a wafer 803 including a driver circuit 811 and a bonding layer 813 as described above via the bonding layer 813 and/or the bonding layer 812. The bonding layer 812 and the bonding layer 813 may be made of the same material or different materials. The bonding layer 813 and the bonding layer 812 may be substantially planar. The first wafer 802 may be bonded to the wafer 803 by various methods, such as metal-to-metal bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermocompression bonding, ultraviolet (UV) bonding, and/or fusion bonding.

As shown in fig. 8B, the first wafer 802 may be bonded to the wafer 803 with the p-side of the first wafer 802 (e.g., the second semiconductor layer 810) facing downward (i.e., toward the wafer 803). After bonding, the substrate 804 may be removed from the first wafer 802, and then the first wafer 802 may be processed from the n-side. For example, the process may include forming a particular mesa shape for an individual LED, and forming an optical component corresponding to the individual LED.

Fig. 9A-9D illustrate examples of hybrid bonding methods for LED arrays according to particular embodiments. Hybrid bonding may generally include wafer cleaning and activation, high precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric material at the wafer surface at room temperature, and metal bonding of contacts by annealing at elevated temperatures. Fig. 9A shows a substrate 910 with passive or active circuitry 920 fabricated thereon. As described above with reference to fig. 8A-8B, the substrate 910 may comprise, for example, a silicon wafer. The circuit 920 may include a circuit for an array of LEDs and each A driver circuit for an electrical interconnect. The bonding layer may include dielectric regions 940 and contact pads 930 connected to circuitry 920 through electrical interconnects. The contact pads 930 may include, for example, cu, ag, au, al, W, mo, ni, ti, pt, pd, etc. The dielectric material in dielectric region 940 may include SiCN, siO ₂ 、SiN、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ 、Ta ₂ O ₅ Etc. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, wherein the planarization or polishing may cause recesses (bowl-like profile) in the contact pads. The surface of the bonding layer may be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., ar) beam 905. The activated surface may be atomically clean and may be reactive when the wafers are contacted, for example, at room temperature, for forming direct bonds between the wafers.

Fig. 9B illustrates a wafer 950 including an array of micro LEDs 970 fabricated thereon as described above with reference to, for example, fig. 7A-8B. Wafer 950 may be a carrier wafer and may include, for example, gaAs, inP, gaN, alN, sapphire, siC, si, etc. micro-LEDs 970 may include an n-type layer, an active region, and a p-type layer epitaxially grown on wafer 950. The epitaxial layer may comprise the various III-V semiconductor materials described above, and may be processed from the p-type layer side to etch mesa structures such as substantially vertical structures, parabolic structures, conical structures, etc. in the epitaxial layer. A passivation layer and/or a reflective layer may be formed on sidewalls of the mesa structure. The p-type contacts 980 and the n-type contacts 982 may be formed in a layer of dielectric material 960 deposited over the mesa structure, and electrical contacts may be made to the p-type layer and the n-type layer, respectively. The dielectric material in dielectric material layer 960 may include, for example, siCN, siO ₂ 、SiN、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ 、Ta ₂ O ₅ Etc. The p-type contacts 980 and n-type contacts 982 may include, for example, cu, ag, au, al, W, mo, ni, ti, pt, pd, etc. The top surfaces of the p-type contacts 980, the n-type contacts 982, and the layer of dielectric material 960 may form a bonding layer. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, wherein polishing may cause the p-type contacts 980 and n-type contacts 982 to be polishedIs formed by the recess of the mold. The bonding layer may then be cleaned and activated by, for example, ion (e.g., plasma) or fast atom (e.g., ar) beam 915. The activated surface may be atomically clean and may be reactive when the wafers are contacted, for example, at room temperature, for forming direct bonds between the wafers.

Fig. 9C illustrates a room temperature bonding process for bonding a dielectric material in a bonding layer. For example, after the bonding layer including dielectric region 940 and contact pad 930 and the bonding layer including p-type contact 980, n-type contact 982, and dielectric material layer 960 are surface activated, wafer 950 and micro-LEDs 970 may be inverted and brought into contact with substrate 910 and the circuitry formed thereon. In some embodiments, compressive pressure 925 may be applied to substrate 910 and wafer 950 such that the bonding layers press against each other. Due to surface activation and dishing in the contacts, dielectric region 940 and dielectric material layer 960 may be in direct contact due to surface attraction forces and may react and form chemical bonds between them, as surface atoms may have dangling bonds and may be in an unstable energy state after activation. Thus, the dielectric materials in dielectric region 940 and dielectric material layer 960 may be bonded together with or without heat treatment or pressure.

Fig. 9D illustrates an annealing process of contacts bonded in the bonding layer after the dielectric material is bonded in the bonding layer. For example, contact pad 930 and p-type contact 980 or n-type contact 982 may be bonded together by annealing at a temperature of, for example, about 200-400 ℃ or higher. During the annealing process, heat 935 may cause the contacts to expand more than the dielectric material (due to the different coefficients of thermal expansion), and thus may close the recessed gaps between the contacts, so that contact pads 930 and p-type contacts 980 or n-type contacts 982 may contact and may form a direct metal bond at the activated surface.

In some embodiments where the two bonded wafers include materials having different Coefficients of Thermal Expansion (CTE), the dielectric material bonded at room temperature may help reduce or prevent misalignment of the contact pads caused by the different thermal expansion. In some embodiments, to further reduce or avoid misalignment of the contact pads at high temperatures during annealing, trenches may be formed between micro LEDs, between groups of micro LEDs, through part or all of the substrate, etc., prior to bonding.

After the micro-LEDs are bonded to the driver circuitry, the substrate on which the micro-LEDs are fabricated may be thinned or removed, and various secondary optical components may be fabricated on the light emitting face of the micro-LEDs, for example, to extract, collimate, and redirect light emitted from the active region of the micro-LEDs. In one example, microlenses may be formed over the micro-LEDs, where each microlens may correspond to a respective micro-LED and may help to increase light extraction efficiency and collimate light emitted by the micro-LED. In some embodiments, the secondary optic may be fabricated in the substrate or n-type layer of the micro LED. In some embodiments, the secondary optic may be fabricated in a dielectric layer deposited on the n-type side of the micro LED. Examples of secondary optical components may include lenses, gratings, anti-reflection (AR) coatings, prisms, photonic crystals, and the like.

Fig. 10 illustrates an example of an LED array 1000 with secondary optic fabricated thereon, in accordance with certain embodiments. The LED array 1000 may be fabricated by bonding LED chips or wafers to silicon wafers including circuitry fabricated thereon using any suitable bonding technique described above with reference to, for example, fig. 8A-9D. In the example shown in fig. 10, the LED array 1000 may be bonded using wafer-to-wafer hybrid bonding techniques as described above with reference to fig. 9A-9D. The LED array 1000 may include a substrate 1010, which may be, for example, a silicon wafer. An integrated circuit 1020, such as an LED driver circuit, may be fabricated on the substrate 1010. The integrated circuit 1020 may be connected to the p-type contact 1074 and the n-type contact 1072 of the micro LED 1070 through a contact pad 1030, wherein the contact pad 1030 may form a metal bond with the p-type contact 1074 and the n-type contact 1072. The dielectric layer 1040 on the substrate 1010 may be bonded to the dielectric layer 1060 by fusion bonding.

The substrate (not shown) of the LED chip or wafer may be thinned or may be removed to expose the n-type layer 1050 of the micro LED 1070. Various secondary optical components (such as spherical microlenses 1082, gratings 1084, microlenses 1086, An anti-reflective layer 1088, etc.) may be formed in or on top of n-type layer 1050. For example, a gray scale mask and a photoresist having a linear response to exposure light (exposure light), or an etch mask formed by thermal reflow (thermal reflowing) of a patterned photoresist layer may be used to etch the spherical microlens array in the semiconductor material of the micro LED 1070. Similar photolithographic techniques or other techniques may also be used to etch the secondary optic in the dielectric layer deposited over n-type layer 1050. For example, the microlens array may be formed in the polymer layer by thermal reflow of the polymer layer patterned using a binary mask. The microlens array in the polymer layer may be used as a secondary optic or may be used as an etch mask to transfer the contours of the microlens array into the dielectric or semiconductor layer. The dielectric layer may comprise SiCN, siO, for example ₂ 、SiN、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ 、Ta ₂ O ₅ Etc. In some embodiments, micro-LEDs 1070 may have a plurality of corresponding secondary optical components such as micro-lenses and anti-reflective coatings, micro-lenses etched in semiconductor material and micro-lenses etched in dielectric material layers, micro-lenses and gratings, spherical lenses and aspherical lenses, and the like. Three different secondary optic are illustrated in fig. 10 to show some examples of secondary optic that may be formed on micro LEDs 1070, which does not mean that different secondary optic are used simultaneously for each LED array.

Referring next to fig. 11 and 12, a side view of the display device 1100 is shown in fig. 11, and a top view of the display device 1100 is shown in fig. 12. The display device 1100 may be part of a light source (e.g., light source 412, 410, 540, or 642) of a near-eye display. The display device 1100 includes a plurality of LEDs. The plurality of LEDs may be micro LEDs. Although the examples in fig. 11 and 12 are based on micro LED devices, it should be understood that the examples in fig. 11 and 12 are also applicable to other types of light emitters (e.g., semiconductor lasers and LEDs).

As shown in fig. 11, the display device 1100 may include an array of LED die 1102, including, for example, LED die 1102-a, LED die 1102-b, and LED die 1102-c assembled on a back plate 1104. The back plate 1104 may include structure for attaching the plurality of LED die 1102 to provide electrical connection and/or structural support for the plurality of LED die 1102. As used herein, a "back plate" may refer to a structure that provides a surface (which may be planar, curved, etc.) for attaching a plurality of LED devices (which may include a μled device) and/or for providing electrical signals to the plurality of LED devices. The backplane 1104 may be configured to display the backplane to form a display device. For example, the backplane 1104 may hold an assembly of LED devices forming a display element, and the backplane 1104 may also include traces that provide electrical signals to the LED devices to control the information displayed by the display element. The backplane 1104 may include traces that may be connected to other components. The backplane 1104 may also include electrical contacts, such as metal pads, that may provide access to the traces. For example, as shown in FIGS. 11 and 12, the backplane 1104 includes electrical traces 1106-a, 1106-b, and 1106-c to electrically connect with the μLED die 1102-a, the μLED die 1102-b, and the μLED die 1102-c, respectively. The electrical traces 1106-a, 1106-b, and 1106-c allow each of the μled die 1102-a, μled die 1102-b, and μled die 1102-c to be controlled individually by applying different signals to different μled die 1102. The back plane 1104 also includes electrical traces 1108 to act as return current paths for each of the μled die 1102-a, 1102-b, and 1102-c. The back plate 1104 may include different kinds of materials such as Thin Film Transistor (TFT) layers, glass substrates, polymers, polychlorinated biphenyls (PCBs), and the like. While fig. 11 shows the back plate 1104 as having a rectangular shape, it should be understood that the back plate 1104 may have various shapes and sizes. In some embodiments, a single ul led die 1102 may have a single ul led device. In some embodiments, a single ul led wafer 1102 may have multiple ul led devices. For example, the ul led wafer 1102 may have 2,073,600 ul led devices (e.g., 1920x 1080).

Each of the LED die 1102-a, 1102-b, and 1102-c may have a structure similar to the LED 700 of fig. 7A or other LEDs described or referenced. Each of the LED dies in fig. 11 and 12 can have an active region 1110 (e.g., formed by active layer 730) and a contact 1112. While fig. 11 and 12 illustrate the contacts 1112 as rectangular in shape, it should be understood that the contacts may take other shapes including, for example, circular, dome-shaped, etc. One contact 1112 of the LED die 1102 may be connected to a p-type contact pad and the other contact 1112 of the LED die 1102 may be connected to an n-type contact pad.

Bumps 1114 may be used to secure the LED die 1102 to the back plate 1104. Bumps 1114 may provide electrical connection between the LED die 1102 (e.g., contacts 1112) and the back plate 1104. In some embodiments, the bumps 1114 are solder bumps attached or deposited on the under bump metallization structures (e.g., pads on the back plane 1104 and/or on the μled wafer 1102 may also be used for under bump metallization). The under bump metallization may be used to provide good adhesion of the interconnect bumps and/or act as a diffusion barrier. The under bump metallization may comprise one or more metal layers.

In the example of fig. 11 and 12, the backplane 1104 has a separate bump 1114 (e.g., for each trace 1106) for each LED die 1102 to transmit control signals to each LED die 1102, respectively. Such an arrangement, while allowing each μled die 1102 to be controlled individually, may result in a large number of bumps 1114 being placed on the backplane 1104 when the display device 1100 includes a large number of pixels (e.g., with a large number of pixels and/or densely packed pixels to achieve higher resolution). For example, the display includes one million μleds with one million pairs of bumps 1114 (e.g., the first bump 1114-1 and the second bump 1114-2, both of which contact the first μled die 1102-a, are considered to be one pair) disposed on the backplane 1104 to provide electrical connections to each of the one million μleds. In another example, one million μleds use one million plus one bump (e.g., one million bumps for p-type contacts plus one bump for common (distal) n-type contacts, where the n-type contacts are located at the periphery of the μled). Additional traces 1106 and 1108 are also used on the backplane 1104 to provide electrical connection to the bumps 1114.

The large number of bumps and associated wiring can reduce the tight integration between the LED device and the control circuitry. For example, additional back plane space may be required to place bumps, which may increase the distance between the LED device and the control circuitry. As the signal propagates through longer distances, the operating speed of the LED device and/or control circuit may also be reduced.

Fig. 13 illustrates an embodiment of a display device 1300. The display apparatus 1300 has a device layer 1302 with a thin film circuit layer 1304 deposited on the device layer 1302. The display device 1300 includes a backplate 1306. The backplate 1306 may include CMOS peripheral circuitry 1308. A plurality of bumps 1310 electrically connect the thin film circuit layer 1304 with the backplate 1306 (e.g., bumps 1310 connect the thin film circuit layer 1304 with the CMOS peripheral circuitry 1308).

The device layer 1302 includes an array of light sources (e.g., an array of LEDs, such as a mu LED die 1102 array or an array of LEDs 700). The LED array includes a layered epitaxial structure including a first doped semiconductor layer (e.g., a p-doped layer), a second doped semiconductor layer (e.g., an n-doped layer), and a light emitting layer (e.g., an active region). The device layer 1302 of the LED array has a light-emitting side 1312 (e.g., light is emitted in the z-direction) and a side 1314 opposite the light-emitting side 1312.

A thin film circuit layer 1304 is deposited on a side 1314 of the device layer 1302 opposite the light emitting side of the LED array. The thin film circuit layer 1304 may include: a transistor layer (e.g., a Thin Film Transistor (TFT) layer); an interconnect layer; and/or a bonding layer (e.g., a layer including a plurality of under bump metallization pads to allow for interconnect bumps to be attached thereto). The device layer 1302 is a support structure for the thin film circuit layer 1304. The thin film circuit layer 1304 includes circuitry for controlling the operation of the LEDs in the LED array. The device layer 1302 and the thin film circuit layer 1304 may form a vertical stack (e.g., in the z-direction; monolithically integrated).

The backplate 1306 is coupled to the thin film circuit layer 1304 using bumps 1310. Bump 1310 is a plurality of metal bonds. The back plate 1306 includes a driving circuit for supplying current to the thin film circuit layer 1304 through a plurality of metal bonds. For example, the backplate 1306 includes a silicon substrate, and the CMOS peripheral circuitry 1308 (e.g., drive circuitry) includes transistors fabricated on the silicon substrate (e.g., in the silicon substrate or in a layer supported by the silicon substrate). In some embodiments, the backplate 1306 may comprise a transparent substrate.

Bump 1310 forms a plurality of metal bonds. Since the thin film circuit layer 1304 may be used to enable data to be sent from the backplate 1306 through one bump 1310 to operate multiple LEDs, the number of multiple metal bonds may be less than the number of LEDs in the LED array. In fig. 13, bump 1310 may represent a single interconnect or multiple interconnects for carrying a set of signals targeted to a particular LED, pixel, set of LEDs, or set of pixels.

In display device 1300, each LED may form one pixel, or multiple LEDs may form one pixel (e.g., one or more red, green, or blue LEDs may form one pixel). The thin film circuit layer 1304 may include a plurality of sets of TFTs, each set corresponding to an LED device of one pixel and forming one pixel TFT. The pixel TFT may control the operation of the corresponding LED or group of LEDs. For example, the pixel TFT may control the magnitude of the current flowing through the corresponding LED to control the intensity of light emitted by the LED. The pixel TFTs may control pixels based on control signals received from CMOS peripheral circuitry 1308 of the backplate 1306, and the CMOS peripheral circuitry 1308 may include an array of high-speed driver circuits. The control signal may be received at the thin film circuit layer 1304 via the bump 1310.

In display device 1300, thin film circuit layer 304 may include signal lines (e.g., traces 1106 in fig. 12) that may be electrically connected to each pixel TFT or group of pixel TFTs. The common signal line may carry a selection signal to indicate which of the pixel TFT/pixel TFT groups is selected. The common signal line may also carry an operating signal to control the magnitude of the current flowing, for example, through the LEDs controlled via the selected pixel TFT/pixel TFT group. The common signal line of the thin film circuit layer 1304 may be electrically connected to the backplate 1306 through the bump 1310. The CMOS peripheral circuit 1308 may generate a selection signal and an operation signal to select, for example, rows of LEDs to sequentially emit light to form a scanning display.

Fig. 14 illustrates an example of a micro LED array 1400. Each point in fig. 14 represents the location of a light source 1402, such as an LED or pixel. The array 1400 is superimposed on the dashed line forming the grid 1404. Fig. 14 illustrates the distribution of LEDs. The array 1400 is partially shown. For example, the light sources 1402 may extend in x and/or y such that there are more than 6k, 10k, 100k, 500k, or 1,000k light sources 1402 in the array 1400.

If there is one signal line for each light source 1402, the bumps 1114 in FIG. 11 may be at least as densely spaced as the light sources 1402 in the array 1400, or the bumps 1114 may be placed outside the area of the array 1400. Forming small, closely spaced bumps (e.g., when the spacing between bumps is less than 10 μm, 5 μm, or 2 μm) and/or using them for bonding can be challenging.

Fig. 15 illustrates an example of bump locations associated with the array 1400 of light sources 1402 in fig. 14. Fig. 15 shows a plurality of bumps 1502 superimposed over a grid 1404. The pitch between the bumps 1502 is much larger than the pitch between the light sources 1402 in fig. 14. Thus, one bump 1502 may be used to transmit control signals (e.g., select signals, operation signals, etc.) to the light sources 1402 in a group. The light sources 1402 may be grouped, each group sharing bumps 1502 for transmitting signals to the light source groups 1402. In some embodiments, there may be 50, 64, 100, 128, 250, or 500 light sources 1402 per group. In other embodiments, each group may have a different number of light sources 1402. The thin film circuit layer 1304 may be used to activate the individual light sources 1042 in response to control signals.

The number of the plurality of bumps 1502 in fig. 15 is less than the number of the plurality of light sources 1402 in the array 1400. For example, the array 1400 may include two million LEDs to support High Definition (HD) projection, and each LED may have a small pitch between LEDs equal to or greater than 0.1 μm, 0.5 μm, or 1 μm, and/or equal to or less than 20 μm. To support individual pixel level interconnects, two million bumps (or bump groups) will be provided on the back plate, with the pitch of each bump being the same as (or less than) the pitch between LEDs (e.g., 0.1 μm to 20 μm). Advanced and expensive manufacturing techniques can be used to densely arrange such a large number of bumps on the back plate with high precision to conform to the pitch of the LEDs. In contrast, using the described techniques, far fewer bumps (e.g., about 4000 bumps for two million LEDs) may be placed on the back plate, wherein each bump may be separated by a distance much greater than the LED pitch (e.g., the bump pitch may be about 12, 14, 15, 25, 35, 45, 55, or 65 μm). Bumps 1502 having larger pitches can relax manufacturing tolerances. Accordingly, display device 1300 may be manufactured using less advanced and/or more cost effective manufacturing techniques.

Fig. 16 illustrates a cross-sectional view of device layer 1602, wherein thin film circuit layer 1604 is disposed on device layer 1602. Thin film circuit layer 1604 includes a portion of transistor layer 1606, interconnect layer 1608, and bonding layer 1610.

The device layer 1602 includes a plurality of LEDs 1614. The LEDs 1614 may be micro LEDs in an array (e.g., array 1400). The LEDs 1614 may be formed on substrates compatible with LED materials and operation (e.g., group III-V or group III nitride materials, including gallium nitride (GaN), gaN on Si (silicon), gaN on sapphire, indium gallium arsenide (InGaAs), aluminum indium gallium phosphide (AlInGaP), and gallium arsenide (GaAs)). The LED 1614 may include an active region 1616, a reflector 1618, and/or light extraction features 1620.

Transistor layer 1606 may include one or more electrical devices. For example, transistor layer 1606 may include a Thin Film Transistor (TFT) 1622, a metal via 1624, an interconnect, a capacitor, a resistor, and the like (e.g., monolithically formed on device layer 1602). The TFT 1622 may include materials including, for example, c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO), amorphous indium gallium zinc oxide (a-IGZO), low Temperature Polysilicon (LTPS), amorphous silicon (a-Si), and the like. Example structures of the TFT may include a top gate or a bottom gate; a top contact or a bottom contact; etc. In some embodiments, transistor 1622 is a trench gate self-aligned (TGSA) thin film transistor.

TFT 1622 may be formed on the back-end of device layer 1602 (e.g., on the back-end of the array of LEDs 1614). This arrangement allows the LED devices to be fabricated on separate wafers, thereby achieving LED device/process optimization. For example, etching and passivation may be performed to isolate the cathode/anode to achieve pixel scaling. In some embodiments, transistor layer 1606 includes transistors and capacitors that are interconnected to form pixel circuitry for controlling the operation of LED 1614.

Interconnect layer 1608 includes a common signal line, sometimes referred to as a control line or data line 1628. The common signal line may be part of a global network. The bonding layer includes a plurality of pads 1630 to bond the bumps. A data line 1628 connects a plurality of pixel circuits (e.g., for a plurality of LEDs 1614) from the transistor layer 1606 to one pad 1630 in the bonding layer 1610.

Fig. 17 illustrates a cross-sectional view of an example of a back plate 1704 bonded to an array of LEDs 1614. The backplate 1704 may include a silicon wafer including transistors and interconnects to implement, for example, CMOS peripheral circuitry 1308. Bump 1502 electrically connects back plane 1704 and thin film circuit layer. Bump 1502 may comprise copper, copper alloy, aluminum, tungsten, or the like. Further, bump 1502 may be in the form of a die-to-die or die-to-wafer interconnect.

Fig. 17 shows one data line 1628 connected to a first transistor 1622-1 of a first pixel circuit to control operation of a first LED 1614-1 and to a second transistor 1622-2 of a second pixel circuit to control operation of a second LED 1614-2. The pixel circuits are interconnected by data lines 1628 (e.g., the pixel circuits share data lines) to reduce the number of global signals and (e.g., to reduce the number of bumps 1502 for transmitting global signals). The data line 1628 is connected to the first pad 1708-1. Bump 1502 bonds first pad 1708-1 to second pad 1708-2, wherein second pad 1708-2 is part of backplate 1704.

Fig. 18 illustrates an example architecture of a display device 1800 in accordance with examples of the disclosed technology. The displacement device 1800 is but one example architecture among various architectures along a range of increased functionality in a thin film circuit layer (e.g., as shown in fig. 27). As shown in fig. 18, the backplate 1704 may include a CMOS wafer including a plurality of address drivers 1802, data line/bit line drivers 1804, and control/timing drivers 1806. The address driver 1802 may generate a selection signal to select one or more pixel TFTs (and corresponding LEDs). The select signal may specify, for example, an address (e.g., row address, column address, etc.) of the target LED. The data line/bit line driver 1804 may generate an operation signal to set the magnitude (or average magnitude) of the current flowing through the LED. The control/timing driver 1806 may generate timing signals to control the timing of the application of the operation signals. The driver may be controlled by a control logic display pipeline (pipeline) 1808. The backplate 1704 may also include a supply voltage regulator 1810 that supplies voltage (and ground) to the LEDs. The selection signal, the operation signal, the timing signal, and the power supply voltage may be transmitted to the thin film circuit layer via the bump 1502. The thin film circuit layer includes a common signal line (e.g., data line 1628) shared by the pixel TFT groups. The target pixel TFT may be selected/enabled by a selection signal and controls a current flowing through a corresponding LED based on an operation signal and a timing signal.

As an example, the backplate 1704 is configured to transmit global signals to the thin film circuit layer through one of the plurality of metal bonds (e.g., the bump 1502), wherein the global signals include one or more of: row select data, column select data, analog bias, supply voltage, pulse clock, or dft (test enable circuit). The drive circuitry of the backplate 1704 may include one or more of the following: an address driver 1802, a data line driver 1804, or a control/timing driver 1806. The thin film circuit layer may include a selector multiplexer for applying a signal to the pixel circuit.

Fig. 19-21 illustrate example modulation circuits of a display device. The modulation circuitry may be formed in the thin film circuit layer 1604 and/or the backplate 1704. Fig. 19 is an example of an analog modulation circuit. The amplitude of the operating signal in the analog circuit corresponds to the amplitude of the current to be applied to the LED 1614. The analog modulation circuit may have minimal footprint, but amplitude modulation may cause the LED 1614 to red shift or blue shift.

Fig. 20 is an example of a circuit for Pulse Code Modulation (PCM) of the intensity of the LED 1614. The circuit in fig. 20 is relatively simple, but the glitch (glitch) may cause some perceptual artifacts (perceptual artifact). Fig. 21 is an example of a circuit for Pulse Width Modulation (PWM) of the intensity of LED 1614. PWM circuits have the largest footprint but less perceived artifacts.

Changing the coded signal may change the duration that the LED is on, thereby changing the brightness that the LED presents to the user. In PCM and PWM, the operating signal comprises a digital signal representing the percentage of time that current flows to the selected LED 1614. The graph below the circuit diagram shows the signal "on" duration based on different combinations of the encoded signals. For example, in the PCM circuit of fig. 20, the "wl" and "bl" signals may be operation signals controlled by the address driver to charge the capacitors d0, d1, and d 2. The counter signals c0, c1, and c2 may be controlled by a control/timing driver to control when the capacitors d0, d1, and d2 discharge through the LED 1614, which may modulate the conduction duration of the current through the LED 1614. The PWM circuit of fig. 21 may also modulate the conduction duration of the current through LED 1614 based on similar principles, but with different timing for counter signals c0, c1, and c 2. In fig. 19 to 21, if a signal network (signal net) is connected to only terminals within a single pixel, it can be regarded as a local signal. A signal network can be considered a global network if it connects a plurality of bit cells (bitcells) together. For example, in graph 120, "bl" (bit line), "wl" (word line), "c0", and "vdd" (power supply) may be considered part of a global network. The global signal is transmitted over a global network. One feature of global signals is that they may have a high capacitive load. Some global signals may also have high steady state current loads. Because of the limited drive strength of the TFT components, it is recommended not to use TFT components to charge or discharge the global network. Instead, it is acceptable for the TFT components to load the global network. Similarly, the TFT component may be acceptable to charge or discharge the local network due to reduced local network capacitance and thus reduced drive requirements.

Fig. 22-24 illustrate examples of addressing schemes. Fig. 22 illustrates an addressing scheme in which each pixel 2202 has a separate address connection. Fig. 23 illustrates an example of addressing a pixel 2302 by using a row address and a column address, which may reduce the number of connections to the pixel compared to addressing according to fig. 22. In fig. 23, each row address and column address may be shared between pixels along the same row and column, respectively.

As shown in fig. 24, to reduce capacitive loading on the pixel TFT input, two transistors 2402 connected in series may be provided to control the input of the pixel TFT. The two transistors 2402 can be controlled by, for example, two row selection signals configured to select or deselect a row of pixels, two column selection signals configured to select or deselect a column of pixels, and the like. Capacitor 2404 is a storage capacitor. BL may be a bit line, which may also be referred to as a data line. The two transistors 2402 can also be controlled by the same signal to reduce the number of common signals. Thus, the pixel circuit may be coupled to a plurality of select signals that are asserted (asserted) in combination to couple the storage capacitor to the data line. A single pixel circuit may be connected to a plurality of row selection signals. The control signals may include a unique address of the LED 1614 and the operation signals may control the operation of selected LEDs in the LED array. The circuit in fig. 24 may be formed in the transistor layer 1606 and is sometimes referred to as a selector.

Fig. 25 illustrates an example layout for addressing a pixel 2302 using multiple row signals. Multiple columns may be folded into one column 2502 to reduce the number of column connections (e.g., to reduce the number of bumps 1502 used). For example, two rows and four columns may be electrically and/or logically connected to have one column and eight rows. The addressing scheme and selection signals may be configured to distinguish pixels 2302 that are within the same column but are addressed to different columns. Each pixel TFT may be configured to perform pixel level (in-pixel) decoding of the selection signal based on the addressing scheme so that the correct pixel may be selected. For the example in FIG. 25, pixels 2302-1, 2302-2, 2302-4, 2302-5, 2302-6, 2302-7, 2302-8 can be addressed individually by a combination of column data line signals 2502 and row data line signals (e.g., A, B, C, X, Y and Z). Addressing is achieved by having two selector signals per pixel. For example, both signal "A" and signal "X" must be active (asserted) to select pixel 2302-1. For example, both signal "B" and signal "X" must be active to select pixel 2302-2. More generally, to address N pixels on a data line, a square root of N selector signals are used. This approach has the advantage of further reducing the number of "bump" interconnects used and thus achieves a coarse, more manufacturable pitch objective. In some embodiments, the center-to-center spacing between pixels 2302 is equal to or less than 5 microns, 3 microns, or 2 microns and equal to or greater than 0.1 microns, 0.5 microns, or 1 micron.

Fig. 26 is a flow chart of an embodiment of a process 2600 of manufacturing a display device. The process 2600 begins at step 2602 with fabricating micro LEDs on a micro LED wafer in step 2602. Micro LED devices may be formed on a wafer, which may include a substrate compatible with micro LED materials and operation. Examples include group III-V or group III nitrides, including GAN, GAN on Si, GAN, inGaAs, alInGaP, gaAs on sapphire, and the like.

In step 2604, TFTs may be monolithically formed on the oxide of the micro LED wafer to form one or more micro LED dies such that the TFTs and micro LEDs are formed on the same wafer. The TFT may include a trench gate self-aligned (TGSA) c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO) TFT. The TFT may further include, for example, amorphous indium gallium zinc oxide (a-IGZO), low Temperature Polysilicon (LTPS), amorphous silicon (a-Si), and the like, and may be manufactured in a low temperature back end compatible process.

In step 2606, interconnect formation and metallization may be performed within the micro LED chip to provide a common signal line shared by, for example, pixel TFTs. The interconnect may be formed using a metal (e.g., copper alloy, aluminum, tungsten, etc.). In step 2608, a micro bump interface may be formed on a surface of the micro LED chip to connect with the interconnect.

In step 2610 (which may occur concurrently with steps 902-908), a silicon back plate may be fabricated. The silicon back plate may include driver circuitry (such as the driver circuitry shown in fig. 18). In step 2612, a micro-bump interface may be formed (e.g., a micro-bump interface may be formed on the back plate; in some embodiments, bumps may be formed on the micro-bump interface in step 2608). In step 2614, a singulation process (singulation process) may be performed on the micro LED die and/or the silicon back plate. The micro LED die and the silicon back plate may be assembled by forming micro bump connections at corresponding micro bump interfaces to form a display device.

FIG. 27 illustrates an example sliding scale for complexity and micro-bump reduction with respect to adding functionality to a thin film circuit layer. More circuitry placed in the thin film circuit layer reduces the number of bumps used, which may reduce alignment tolerances. However, the more circuits that are placed in a thin film circuit layer, the more complicated the thin film circuit layer is to manufacture. In addition, the circuitry in the thin film circuit layer may be slower than the circuitry formed in the back plate. Fig. 27 illustrates three example devices: devices 2702-A, 2702-B, and 2702-C. These three example devices are not intended to be limiting, as other combinations of functions divided between the back plane and thin film circuit layers may also be used.

In device 2702-a, the pixel circuits are in the backplane. In this example, the thin film circuit layer is not used and the pitch of the micro-bumps is very tight (e.g., the pitch of the micro-bumps is equal to or greater than 1 micron and equal to or less than 3 microns, such as 1.1 microns, 1.3 microns, 1.4 microns, 1.6 microns, 1.8 microns, 2.1 microns, or 2.3 microns) for high definition.

In the device 2702-B, a pixel circuit having a selector multiplexer is formed in the thin film circuit layer. The micro-bumps are closely spaced but the thin film circuit layer is easier to manufacture than the devices 2702-C (e.g., the micro-bumps are spaced 8 microns or more and 30 microns or less, such as 10 microns, 12 microns, 14 microns, 16 microns, 18 microns, or 20 microns).

In the device 2702-C, the thin film circuit layer includes circuitry in the device 2702-B plus memory (e.g., DRAM) and modulation circuitry (e.g., in fig. 19-21). The micro-bumps in device 2702-C have a maximum pitch (e.g., a pitch of the micro-bumps is equal to or greater than 30 microns and equal to or less than 75 microns, such as 35 microns, 34 microns, 55 microns, or 64 microns).

Thus, in some embodiments, the thin film circuit layer includes a selector multiplexer; the back plane includes memory circuitry and/or modulator circuitry; and/or the thin film circuit layer includes a memory circuit and a modulator circuit.

Fig. 28 is a flow chart of an embodiment of a process 2800 for manufacturing a micro LED display. Process 2800 begins at step 2802 where a semiconductor structure is obtained at step 2802. The semiconductor structure may be a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer. Fig. 7A provides an example of a semiconductor structure, and device layer 1602 in fig. 16 is another example of a semiconductor structure.

In step 2804, a thin film circuit layer is deposited over the semiconductor structure. For example, a layer for forming a thin film transistor is deposited on a semiconductor structure. In step 2806, circuitry is formed in the thin film circuit layer to control light emission of the light emitting layer. For example, transistors, capacitors, traces, and/or common signal lines are formed in the thin film circuit layer. Bond pads (e.g., lower bond pads) may be formed in the thin film circuit layer.

In step 2808, a backplate (e.g., backplate 1704) is obtained. In some embodiments, the back-plate is obtained by manufacturing the back-plate. The back plate includes a driving circuit for supplying current to the thin film circuit layer through the plurality of metal bonds. The back plate may include a plurality of bonding pads (e.g., upper bonding pads) for bonding. In step 2810, a plurality of micro-bumps are formed on the thin film circuit layer or on the back plane (e.g., on the bond pads). In step 2812, the back plate is bonded to the thin film circuit layer using a plurality of micro bumps (e.g., bump 1502). For example, the back-plate is heated and pressed against the thin-film circuit layer such that the micro-bumps (e.g., solder) melt and form an ohmic connection between the back-plate and the thin-film circuit layer. The micro-bumps become a plurality of metal bonds after bonding (e.g., after cooling).

In step 2814, an array of Light Emitting Diodes (LEDs) is formed from the semiconductor structure. The LED array may be formed before or after bonding. The number of the plurality of metal bonds is less than the number of LEDs in the LED array to achieve a greater spacing (e.g., center-to-center) between the metal bonds.

In some embodiments, the LED array has a light emitting side (e.g., light emitting side 1312) and a side opposite the light emitting side (e.g., side 1314) with a thin film circuit layer deposited on the side opposite the light emitting side; obtaining the backplate includes forming a plurality of CMOS transistors and interconnects in a silicon device layer of a silicon wafer; forming the LED array includes singulating the semiconductor structures; the singulated semiconductor structures occur prior to bonding the back plate to the thin film circuit layer; the thin film circuit layer is formed on the wafer-level semiconductor structure; the back plate includes circuitry formed in the back plate prior to bonding; the micro-bumps are made of ohmic material; the thin film circuit layer may be applied to a variety of different types of substrate materials (e.g., sapphire or glass) other than semiconductor structures; the back plate comprises crystalline silicon; the number of micro-bumps used is equal to or greater than 1000 and/or equal to or less than 10,000; and/or the spacing between the micro bumps is greater than the spacing between the LEDs.

The multiplexer may be used to reduce the number of bumps between the thin film circuit layer and the back plane. One example of a multiplexer that may be used to reduce the number of bumps between a thin film circuit layer and a backplane is a tiled-rolling shutter (tile). Tiled rolling shutters divide an array of light sources into blocks, sometimes referred to as groups. Each block has a plurality of rows and a plurality of columns. The command signal is applied to the rows in turn over a period of time such that current is applied to each row in the block during the period of time, only one row receiving current at a time. Although a tiled rolling shutter is provided as one example of a multiplexer, other multiplexers may be used. Variations of tiled rolling shutters may also be used. The multiplexer may be formed in the thin film circuit layer to reduce the number of connections between the back plane and the thin film circuit layer.

Fig. 29 illustrates one example of an LED array divided into blocks 2902 that are part of a tiled rolling shutter. The activation of the rows of the first block 2902-1 and the second block 2902-2 over time is shown. Although two blocks 2902 are shown, it should be understood that there may be more than two blocks 2902 in an LED array. For example, if there are 100 tens of thousands of LEDs in the array, and the array is divided into blocks 2902, each block having 500 LEDs, then the array will be divided into 2000 blocks.

Each block 2902 includes a plurality of rows r and a plurality of columns c. There are m rows and n columns in each block 2902. In the example shown in fig. 29, m=64 and n=6. It should be appreciated that m and n may have different values than those shown in fig. 29. In some embodiments, m is equal to or greater than two, three, four, or five times n. The first row r-1, the second row r-2, the third row r-3, the 64 th row r-64, the first column c-1, the second column c-2, and the third column c-3 of the first and second blocks 2902-1 and 2902 are labeled in FIG. 29.

One period is divided into a plurality of slots T. The number q of time slots T in the period may be equal to the number m of rows. Each row r is activated once during this period. In the example shown, there are 64 time slots T. First time slot T-1, second time slot T-2, third time slot T-3, through 64 th time slot T-64. The sequential rows are activated in sequential time slot T such that the LEDs in each row may be activated once during the period. For example, during the first time slot T-l, the LEDs in the first row r-1 may be activated; during the second time slot T-2, the LEDs in the second row r-2 may be activated; during the third time slot T-3, the LEDs in the third row r-3 may be activated; the LEDs in row 64 r-64 may be activated until during the 64 th time slot T-64. When a row is activated, each LED in the row may receive current individually for a given duration and/or a given intensity. For example, the graphs in fig. 20 and 21 show how an LED may be modulated to remain on (on) for a given duration (e.g., percentage) of time slot T. The longer the LED is on during time slot T, the brighter the LED appears to the viewer. The time period may be so short that the viewer may not perceive that the LED is turning off and on (e.g., the time period may be equal to or less than 15ms, 1ms, 500 μs, 100 μs, or 10 μs; and/or the time period may be equal to or greater than 1 μs). Each row r of block 2902 may be activated at a different time. In some embodiments, the display system may display a frame rate of 120 frames per second and the display tile may contain 64 rows. In some embodiments, the display may have a 50% duty cycle to account for display and graphics system operating overhead. In some embodiments, the row display time may be about 64 microseconds (0.5 x 1/120 x 1/64). In some embodiments, the pixel intensity may be driven by a variable analog current during a row display time of 64 microseconds. In some embodiments, the pixel intensities may be digitally modulated during a line display time of 64 microseconds. In some embodiments, pixels may be switched in 2 microsecond increments to enable 7 bit gray scales to be created (2us=64 us/2^7). Although this example describes activating rows in sequential order, in some embodiments, rows may not be activated in sequential order. In some embodiments, rows r of different columns c may be activated at different times. For example, LEDs in cells (cells) r-1, c-1 may be activated during time slot T-1; the LEDs in units r-2, c-1 may be activated during time slot T-2, and the LEDs in units r-1, c-2 may be activated during time slot T-2; and the LEDs in units r-3, c-1 may be activated during time slot T-3, the LEDs in units r-2, c-2 may be activated during time slot T-3, and the LEDs in units r-1, c-3 may be activated during time slot T-3; etc.

Fig. 30 illustrates an example of a simplified circuit that may be used to apply current to LEDs in a column of tiles. Fig. 30 shows a bond 3002 that electrically couples a back plate 3004 with a control line 3006 in a thin film circuit layer 3008. The control line 3006 provides current to the LED 3010 through the transistor 3012. Control line 3006 may be similar to data line 1628 in fig. 16. Transistor 3012 can be similar to transistor 1622 in fig. 16. The bond 3002 may be a metal bond formed by the bump 1502 in fig. 17.

Control line 3006 provides current to LEDs 3010 in the columns of blocks. The first LED 3010-1 is in the first row r-1, the second LED 3010-2 is in the second row r-2, the third LED 3010-3 is in the third row r-3, and so on until the mth LED 3010-m is in the mth row r-m. The transistor 3012 is sequentially activated (e.g., scrolled) to allow a signal from the control line 3006 to be transmitted to the LED 3010. Cathode 3014 provides a return path for current flowing through LED 3010. The cathode 3014 may be a common cathode (e.g., connected to multiple LEDs 3010 in a column of the block and/or to LEDs in multiple columns and/or blocks).

In this example, the back plate 3004 may include a memory 3016, modulation circuitry 3018, and a current source 3020. The example in fig. 30 is similar to the device 2702-B in fig. 27 in terms of functional division between the thin film circuit layer and the back plane. If the memory 3016 and modulation circuitry 3018 are in the thin film circuit layer 3008, then this configuration would be similar to the device 2702-C in FIG. 27.

By coupling one control line 3006 with multiple LEDs 3010, the number of bonds 3002 between the back plate 3004 and the LEDs 3010 may be reduced as compared to having one control line 3006 per LED 3010.

If the number of columns n in a tile is equal to 8, there will be 8 bonds 3002 per tile and 8 times m LEDs 3010. There will also be 8 modulation circuits 3018 and 8 memories 3016 per block. In some embodiments, the LED array may be divided into 512, 1000, 2048, 2542, or other number of blocks.

Fig. 31 illustrates an example of block 3100 with bond sites for bond 3002. Block 3100 may be similar to block 2902. Block 3100 has m number of rows and n number of columns. Block 3100 has eight columns (n=8). There is one LED in each cell of the rows and columns. Block 3100 illustrates a subset of the LED array. The LED array occupies a certain footprint and the bonds 3002 are dispersed over that footprint. While the bond 3002 appears to be on the LED array, the bond 3002 is between the LED array and the back plate; fig. 31 shows bonding sites juxtaposed (juxtaposition) with an LED array. The LEDs in block 3100 of FIG. 31 have a pitch of 1.8 μm, but other pitches of LEDs may be used. The combined width of rows 1-64 is 115.2 μm and the combined width of columns is 14.4 μm. Other dimensions may be used.

When bonding two wafers together using solder as a bonding material, the solder is heated. If the two wafers have substrates with different Coefficients of Thermal Expansion (CTE), the two wafers may expand at different rates, resulting in "walk-off" of the contacts (i.e., bond sites or pads, such as pad 1630 in fig. 16), and thus misalignment of the contacts of the bond 3002. Higher bonding temperatures result in higher degrees of walk-off and greater degrees of misalignment. For example, the back plate may be made using a silicon substrate, while the LEDs may be made of a III-V material (such as GaAs). The thin film circuit layer is applied to GaAs (e.g., gaAs of an LED acts as a substrate for the thin film circuit layer). Silicon and GaAs have different CTEs. When silicon and GaAs are heated to melt the solder to form a bond, the bond sites in the backplate are offset compared to the bond sites in the thin film circuit layer. The higher the temperature used in bonding, the greater the shift in bonding sites in the back plane as compared to bonding sites in the thin film circuit layer.

To reduce walk-off, larger bonding sites and/or lower bonding temperatures may be used. In addition, etching through one substrate (e.g., a substrate using dry and/or deep etching to etch a thin film circuit layer; etching through GaAs) to form a chiplet (chiplet) can allow movement of bonding sites in the thin film circuit layer. Wafer-to-wafer bonding or die-to-wafer bonding may be used instead of wafer-to-wafer bonding. For example, LEDs on GaAs wafers can be divided into smaller arrays on chiplets, with each chiplet having n-type and p-type contacts. The use of smaller arrays may also allow reworking (reworking) defective portions of the display.

The closely spaced bonding sites may also lead to difficulties in applying underfill (underseal). Applying an underfill may have a variety of benefits including providing additional rigidity, facilitating heat transfer, and/or reducing stress on the bond. If the bonding sites are too close together, it may be challenging for the underfill material to flow between the bonding sites (e.g., because the underfill is too viscous and/or the particle size is too large). The effectiveness of the underfill may be reduced because no underfill material flows between the bond sites. Specific materials have been found to be sufficient for bond site spacing as low as 40 microns (e.g., U8410-302LF1 and XS8410-302SNSB from Namics). Particular materials have been found to be suitable for bond site spacing as low as 20 microns (e.g., U8410-302F from Namics). Another approach may be to use a pre-applied underfill material, which may be a spin-coatable adhesive material or a laminable film, on the back-sheet and/or thin-film circuit layer prior to bonding the back-sheet to the thin-film circuit layer.

Fig. 31 shows that the bonding sites of the bond 3002 can be larger by implementing a tiled-roll multiplexer (tile-roller multiplexor) than if each LED were to bond one control line (e.g., control line 3006 in fig. 30). Block 3100 in fig. 31 shows a block with 64 rows and 8 columns. There are eight bonding elements 3002, one bonding element 3002 for each column, and a corresponding control line. There is a first bond 3002-1 connected to the control lines of the first column c-1; a second bonding element 3002-2 connected to the control lines of the second column c-2; a third bond 3002-3 connected to the control lines of the third column c-3; a fourth bonding element 3002-4 connected to the control lines of the fourth column c-4; a fifth bonding element 3002-5 connected to the control lines of the fifth column c-5; a sixth bonding element 3002-6 connected to the control lines of the sixth column c-6; a seventh bonding element 3002-7 connected to the control lines of the seventh column c-7; and an eighth bonding element 3002-8 connected to the control line of the eighth column c-8. The spacing between the bonding elements 3002 is greater than if there were one bonding element 3002 per LED. The bond 3002 may also be larger than if there was one bond 3002 per LED. Thus, the bumps may be spread at a larger spacing than the pitch of the LEDs in the array.

In some embodiments, the small pitch (distance between the bonds 3002) may be equal to or less than 60 μm, 50 μm, 40 μm, 30 μm, 20 μm, 15 μm, or 10 μm and/or equal to or greater than 1 μm. The smaller the pitch, the lower the temperature required for bonding to reduce walk-off due to CTE mismatch of the substrates. In some embodiments, the bonding temperature is no higher than 300 degrees celsius to reduce walk-off. Sometimes, the bonding temperature may be equal to or less than 300 degrees celsius, 250 degrees celsius, 200 degrees celsius, 150 degrees celsius, 100 degrees celsius, 80 degrees celsius, or 75 degrees celsius, depending on the spacing of the bonds 3002. For example, nanoporous gold compression bonding (compression bonding) can be for a bonding temperature of 75 degrees celsius, which can result in low to no stress caused by CTE mismatch of the materials.

As the bonding temperature decreases, the choice of materials for the bump can become challenging. If solder is used as the bonding material, the bump material has a melting point equal to or less than the bonding temperature, so that the bump melts and forms a bond. The bump material also has a melting point that is higher than the operating temperature of the device (e.g., such that the solder does not re-liquefy during device operation). Accordingly, the solder bump (e.g., bump 1502 in fig. 17) is configured to have a melting point equal to or less than the bonding temperature. In some embodiments, the nanoporous gold or nanoporous copper is used at a bonding temperature equal to or less than 250 degrees celsius, 200 degrees celsius, 150 degrees celsius, 100 degrees celsius, or 75 degrees celsius. The nanoporous gold has a bonding temperature of about 150 degrees or less. The bonding temperature may depend in part on the bonding pressure and/or bonding time used. In some embodiments, copper is used instead of gold because copper is less expensive than gold; the use of copper reduces the risk of silver migration that may occur when gold is used; and/or copper is less likely to contaminate the silicon, which makes copper preferable to gold in back-end processing. The nanoporous copper is expected to have a bonding temperature similar to that of nanoporous gold (e.g., 150 degrees or less). Some other melting points (melting points in degrees celsius) of materials used as solder bumps include: indium (180 °); copper (200 °); indium silver (200 °); copper tin (250 °); gold tin (280 °); gold (290 °). The bumps (before they become the bond 3002) may be spherical, cylindrical, tapered, or other shapes; made of eutectic materials or simple metals (e.g., au or Cu); solid or nanoporous; and/or thermally activated using global heating (e.g., using a bonding tool or oven) and/or thermally activated using local heating (e.g., using a laser to generate a bonding temperature).

Fig. 32 is an example chart comparing block size (in fig. 32, block size is reported as the number of rows in the block, since the number of columns far exceeds the number of rows) to bump pitch. As the block size increases, bump pitch increases because fewer bumps are used to transmit control signals from the back-plate to the LEDs. For example, if the tile size is 1, the bump pitch will be the size of the LED pitch (e.g., 1.8 μm in fig. 31). If the block size is 16, the bump pitch may be 7.2 μm. If the block size is 64, the bump pitch may be 14.4 μm, and so on. The LED array may include a count of LEDs, the plurality of metal bonds corresponds to the count of metal bonds, and the count of metal bonds is at least one, two, or three orders of magnitude less than the count of LEDs in the array. There is a tradeoff between the complexity of the thin film circuit layer and the pitch of the bond. For example, the pitch of the bonds of device 2702-C in FIG. 27 may be greater than the pitch of the bonds of device 2702-B in FIG. 27, however, forming thin film circuit layers in device 2702-C may be more complex and/or create slower circuitry than device 2702-B because the materials used in the thin film circuit layers may not be as efficient as the materials used in the backplate.

Fig. 33 is a flow chart of an embodiment of a process 3300 for manufacturing an LED display. Process 3300 begins at step 3302, where a plurality of LEDs are formed in step 3302. In some embodiments, the number of the plurality of LEDs may be equal to or greater than 4, 8, 16, 32, 64, and 128, and/or equal to or less than 64 or 128 (e.g., the plurality of LEDs may be equal to the number m of rows r in block 2902 of fig. 29). In some embodiments, the number of the plurality of LEDs may be equal to or greater than 307,200, 921,600, or 2,073,600. The plurality of LEDs may be formed of a crystalline semiconductor structure (e.g., a III-V epitaxial layer such as GaAs or InP). LEDs 3010-1 to 3010-m are examples of multiple LEDs.

In step 3304, a thin film circuit layer including a plurality of transistors electrically coupled to a plurality of LEDs is formed. For example, a thin film circuit layer 3008 having the transistor 3012 in fig. 30 is formed. The transistor is electrically coupled to the plurality of LEDs. The plurality of transistors are configured to control operation of the plurality of LEDs. For example, the transistor 3012 controls when current is applied to the LED 3010. In some embodiments, the thin film circuit layer is not lattice matched to the crystalline semiconductor structures of the plurality of LEDs. For example, the thin film circuit layer may include a semiconductor material having an amorphous or polycrystalline structure instead of a single crystal structure.

In step 3306, control lines are formed to electrically connect the plurality of transistors to a first pad (e.g., pad 1630 in fig. 16). For example, the control line 3006 in fig. 30 is configured to control 8, 16, 32, 64, 128, or 256 pixels; the number of pixels need not be a power of 2 and thus other numbers (e.g. 33 or 100 pixels) are possible. The control lines may be formed in and/or part of the thin film circuit layer. In some embodiments, the control lines may be made of copper, copper alloys, aluminum, and/or tungsten; in other embodiments, other materials may be used. In some embodiments, the control lines are common signal lines (e.g., control lines 3006 or data lines). A common signal line may be used to transmit the global signal. One common signal line may be connected to all or part of the pixels in one row. For example, one common signal line may be coupled to transistors controlling the operation of all pixels in a row, where there are 440, 1600, 1920, or 2560 pixels in the row; or the common signal line may be coupled with transistors that control the operation of half of the pixels in a row (e.g., 720, 800, 960, or 1280 pixels).

In step 3308, a back plate (e.g., back plate 3004) is obtained. The backplane may include drive circuitry (e.g., memory 3016 and/or modulation circuitry 3018 in fig. 30, and/or address drivers 1802, data/bit line drivers 1804, control/timing drivers 1806, control logic 1808, and/or supply voltage regulators 1810 in fig. 18). The backplate includes second pads (e.g., bump 1502 is shown in fig. 17 as contacting the first and second pads). As used herein, a back plane may refer to circuitry formed on logic die separate from the ul led epitaxial wafer.

In step 3310, the first pad is bonded to the second pad (e.g., forming bond 3002 in fig. 30). Bonding may include heating the solder (e.g., bump 1502 in fig. 17) to melt the solder. Heating the solder may include heating the solder to no more than 300 degrees celsius, 250 degrees celsius, 200 degrees celsius, 175 degrees celsius, or 150 degrees celsius. In some embodiments, the solder is heated to no less than 50 degrees celsius, 75 degrees celsius, or 100 degrees celsius.

The bond electrically couples the first pad to the second pad such that a controller (e.g., address driver 1802, data/bit line driver 1804, control/timing driver 1806, control logic 1808, and/or supply voltage regulator 1810 in fig. 18) in the backplane is electrically coupled to the control lines. In some embodiments, the method further includes forming a common cathode (e.g., cathode 3014 in fig. 30) to connect to the plurality of LEDs.

Various processes may be used to form an epitaxial structure having a thin film circuit layer and a backplate. The epitaxial structure is used to form an LED array. The back plate may be vertically integrated or horizontally integrated with the epitaxial structure and thin film circuit layers. Fig. 34-54 and 55-64 provide examples of vertical integration. Fig. 67 and 68 provide examples of horizontal integration. If a silicon substrate is used for the back plate, vertical integration may be used for non-transparent displays, as the silicon substrate may be opaque and behind the LED array. Thus, the user will not see other content than the LED array. Horizontal integration may be used for transparent displays. In horizontal integration, the back plate is located on one side of the LED array. Epitaxial structures and thin film circuit layers transparent to the user may be bonded to the transparent substrate. Transparent traces (e.g., using indium tin oxide) may be used to connect the back plane to the thin film circuit layer. Thus, horizontal integration may be used for transparent displays to allow a user to see other content in addition to the LED array.

The epitaxial layers may be singulated in various ways to isolate portions of the epitaxial structure to form individual LEDs. For example, etching may be used to form the mesas. Fig. 34-54 provide examples of etched mesas. Ion implantation may also be used to form planar LEDs. Fig. 55-65 provide examples of planar LEDs. Other isolation processes may also be used.

Referring next to fig. 34-53, simplified cross-sections of processing steps of an embodiment of etching an epitaxial structure to singulate the epitaxial structure for forming LEDs in the epitaxial structure are shown. Fig. 34 is a simplified cross-section of an embodiment of an epitaxial structure 3400. The epitaxial structure 3400 includes a first doped semiconductor layer 3402 and a second doped semiconductor layer 3404. The first and second doped semiconductor layers 3402 and 3404 are on the substrate 3406. In some embodiments, the substrate 3406 is part of an epitaxial structure 3400. The first doped semiconductor layer 3402 and the second doped semiconductor layer 3404 may be grown (e.g., epitaxially grown) on a substrate (e.g., lattice matched to the substrate 3406). In some embodiments, the substrate is a group III-V binary compound (e.g., gaAs, gaP) and the first and second doped semiconductor layers 3402, 3404 are binary, ternary, or quaternary compounds (e.g., inGaAs, inGaAsP).

The epitaxial structure 3400 may further include a light emitting layer 3408 between the first and second doped semiconductor layers 3402 and 3404. The light emitting layer 3408 may be an interface of the first and second doped semiconductor layers 3402 and 3404, or the light emitting layer 3408 may include a material (e.g., a material layer forming a Multiple Quantum Well (MQW)) separate from the first and second doped semiconductor layers 3402 and 3404.

In the embodiment shown in fig. 34, the first doped semiconductor layer 3402 is n-type doped (e.g., fewer electrons (excess holes) in the lattice), while the second doped semiconductor layer 3404 is p-type doped (e.g., excess electrons in the lattice). However, in other embodiments, the first doped semiconductor layer 3402 may be p-type doped, and/or the second doped semiconductor layer 3404 may be n-type doped.

Fig. 35 is a simplified cross-section of an embodiment of an epitaxial structure 3400 in which a contact layer 3502 and a temporary bonding layer 3504 are deposited on the epitaxial structure 3400. Contact layer 3502 is a p-type contact. The contact layer 3502 may be a conductive material, such as a metal. The contact layer 3502 may be deposited by photolithographic techniques. Contact layer 3502 may be used to form a p-type contact for each LED in an array of LEDs. In some embodiments, contact layer 3502 may be used to form common cathode 3014 in FIG. 30. A contact layer 3502 is deposited on top of the second doped semiconductor layer (p-doped layer). In some embodiments, contact layer 3502 may be electrically coupled to a ground plane in the thin film circuit layer through one or more vertical vias. In some embodiments, epitaxial structure 3400 and/or contact layer 3502 may be part of device layer 1602 in fig. 16.

Temporary bonding layer 3504 may be an adhesive (e.g., applied by spin coating) for securing the temporary carrier to epitaxial structure 3400. Temporary bonding layer 3504 is applied on top of contact layer 3502.

Fig. 36 is a simplified cross-section of an embodiment of an epitaxial structure 3400 with a temporary carrier 3602 fixed to the epitaxial structure 3400. Temporary carrier 3602 is secured to epitaxial structure 3400 by temporary bonding layer 3504. Temporary carrier 3602 is attached to the p-side of epitaxial structure 3400 (e.g., p-type doped second doped semiconductor layer 3404 is closer to temporary carrier 3602 than n-type doped first doped semiconductor layer 3402).

Fig. 37 is a simplified cross-section of an embodiment of an epitaxial structure 3400, with a substrate (e.g., substrate 3406 in fig. 36) removed from the epitaxial structure 3400. After removing the substrate, the epitaxial structure is planarized (e.g., by Chemical Mechanical Planarization (CMP)). The n-type doped first doped semiconductor layer 3402 is exposed and planarized.

The structure in fig. 37 is sometimes referred to as an intermediate structure 3700. Intermediate structure 3700 can be used in a variety of etching configurations. For example, the intermediate structure may be used in the following process: a process of etching the epitaxial structure 3400 (e.g., described in fig. 38-42) prior to applying the thin film circuit layer to the epitaxial structure 3400; a process of etching the epitaxial structure 3400 after bonding the epitaxial structure 3400 to the backplate (e.g., described in fig. 43-47); and a process of etching the epitaxial structure 3400 between depositing layers of thin film circuit layers to the epitaxial structure 3400 (e.g., described in fig. 48-53).

Fig. 38-42 depict simplified cross-sections of a process of etching the epitaxial structure 3400 prior to applying a thin film circuit layer to the epitaxial structure 3400. Fig. 38 is a simplified cross-section of an embodiment of an epitaxial structure 3400, wherein the epitaxial structure 3400 is etched to singulate the epitaxial structure. In fig. 38, trench 3802 is formed by etching epitaxial structure 3400. The groove 3802 is defined by a wall 3804. The trench 3802 may be formed by etching the first doped semiconductor layer 3402, the light emitting layer 3408, the second doped semiconductor layer 3404, the contact layer 3502, and/or the temporary bonding layer 3504. In some embodiments, contact layer 3502 or temporary bonding layer 3504 may be used as an etch stop layer (etch stop).

The epitaxial structure 3400 is etched from one side (e.g., n-side) of the first doped semiconductor layer 3402 to form a plurality of mesas 3808. Temporary carrier 3602 may serve as a "handle" to which a plurality of mesas 3808 (epitaxial structure 3400) are attached.

The trenches 3802 in the x/y plane (e.g., as viewed in the z-direction) may form a grid that produces an array of mesas 3808. The grid may be formed in various shapes such that the mesas 3808 of the plurality of mesas 3808 may have a rectangular, circular, square, triangular shape in the x/y plane, or other shape.

Fig. 39 is a simplified cross-section of an embodiment of a thin film circuit layer 1604 deposited on an epitaxial structure 3400. Thin film circuit layer 1604 includes transistor layer 1606 and interconnect layer 1608. A transistor layer 1606 is formed on an exposed surface of the first doped semiconductor layer 3402 (e.g., n-type). Transistor layer 1606 may include a thin film transistor semiconductor material (e.g., transistor layer 1606 may include Indium Gallium Zinc Oxide (IGZO)). Transistor layer 1606 may be referred to as a first thin film layer of thin film circuit layer 1604.

An interconnect layer 1608 is formed on top of the transistor layer 1606. The interconnect layer 1608 may be referred to as a second thin film layer of the thin film circuit layer 1604. A pad 1630 may also be formed for bonding to the metal bump.

In fig. 40, the backplate 1704 is bonded to the thin film circuit layer 1604 using the bumps 1502. The backplate 1704 may include a driver circuit. The epitaxial structure 3400, thin film circuit layer 1604, and backplate 1704 are vertically aligned (e.g., stacked). Fig. 40 shows temporary carrier 3602 extending (in the z-direction) over epitaxial structure 3400.

Fig. 41 is a simplified cross-section of an embodiment in which a temporary carrier (e.g., temporary carrier 3602 in fig. 40) is removed after bonding the backplate 1704 to the thin film circuit layer 1604. In some embodiments, the temporary carrier and/or temporary bonding layer is removed by a solvent (e.g., a solvent that dissolves the temporary bonding layer). Removing the temporary carrier exposes second doped semiconductor layer 3404 and/or contact layer 3502.

Fig. 42 is a simplified cross-section of an embodiment of adding an optical element 4202 to an epitaxial structure 3400. The optical element 4202 may be used to more efficiently extract light from the epitaxial structure 3400. For example, the optical element 4202 may be a diffraction grating. Although the optical element 4202 is shown in fig. 42 as resembling a diffraction grating, the optical element 4202 may be other optical features, such as a lens.

Fig. 43-47 depict simplified cross-sections of embodiments of a process of etching an epitaxial structure after bonding the epitaxial structure to a backplate. Fig. 43 is a simplified cross-section of an embodiment of thin film circuit layer 1604 deposited on intermediate structure 3700. Fig. 43 is similar to fig. 39, except that trench 3802 of fig. 38 has not been formed prior to depositing thin film circuit layer 1604 on intermediate structure 3700 of fig. 43.

Fig. 44 is a simplified cross-section of an embodiment of bonding thin film circuit layer 1604 to backplate 1704. Bump 1502 is used to bond thin film circuit layer 1604 to back plate 1704 and/or to provide an electrical connection from back plate 1704 to thin film circuit layer 1604. Temporary carrier 3602 may be used as a handle when bonding. Thin film circuit layer 1604 is between intermediate structure 3700 and backplate 1704.

Fig. 45 is a simplified cross-section of an embodiment of removing a temporary carrier (e.g., temporary carrier 3602 in fig. 44) after bonding thin-film circuit layer 1604 to backplate 1704. In fig. 46, a simplified cross-section of an embodiment of a trench 3802 etched in an epitaxial structure 3400 is shown. After removing the temporary carrier and/or after bonding the backplate 1704 to the thin film circuit layer 1604, trenches 3802 are etched in the epitaxial structure 3400. Fig. 47 is a simplified cross-section of an embodiment in which an optical element 4202 is added to an epitaxial structure 3400 (e.g., similar to fig. 42).

Referring next to fig. 48-53, a cross-section of an embodiment of a process for etching an epitaxial structure between deposition of layers of a thin film circuit layer to the epitaxial structure is shown. Fig. 48 is a simplified cross section of an embodiment of a transistor layer 1606 deposited over an intermediate structure 3700. Transistor layer 1606 may be referred to as a first thin film layer of a thin film circuit layer. Transistor layer 1606 is deposited over first doped semiconductor layer 3402 (e.g., n-doped).

Fig. 49 is a simplified cross-section of an embodiment etched through transistor layer 1606 and epitaxial structure 3400. Trench 4902 is formed in both transistor layer 1606 and the epitaxial structure. Transistor layer 1606 and wall 4904 in epitaxial structure 3400 define sides of trench 4902. Trench 4902 is similar to trench 3802 except that trench 4902 extends through transistor layer 1606 and epitaxial structure 3400. The trench isolates the epitaxial structure 3400 to form a plurality of LEDs.

The isolation process of etching through transistor layer 1606 to etch epitaxial structure 3400 may have some limitations. For example, the isolation process in fig. 48-53 assumes that transistor layer 1606 is isolated for individual LEDs, which may not be a valid assumption in some embodiments. For example, transistor layer 1606 may be used to implement circuitry shared by multiple LEDs (e.g., circuitry to perform functions such as multiplexing, modulation, memory, etc.).

Fig. 50 is a simplified cross section of an embodiment of interconnect layer 1608 deposited over transistor layer 1606 after transistor layer 1606 is etched to isolate epitaxial structure 3400. The interconnect layer 1608 may be referred to as a second thin film layer of the thin film circuit layer 1604.

In fig. 51, a back plate 1704 is bonded to a thin film circuit layer 1604 using bumps 1502. The backplate 1704 may include a driver circuit. The epitaxial structure 3400, thin film circuit layer 1604, and backplate 1704 are vertically aligned (e.g., stacked). Fig. 51 shows temporary carrier 3602 extending (in the z-direction) over epitaxial structure 3400.

Fig. 52 is a simplified cross-section of an embodiment of removing a temporary carrier (e.g., temporary carrier 3602 in fig. 51) after bonding the backplate 1704 to the thin film circuit layer 1604. In some embodiments, the temporary carrier and/or temporary bonding layer is removed by a solvent (e.g., a solvent that dissolves the temporary bonding layer). Removing the temporary carrier exposes second doped semiconductor layer 3404 and/or contact layer 3502.

Fig. 53 is a simplified cross-section of an embodiment of adding an optical element 4202 to an epitaxial structure 3400. The optical element 4202 may be used to more efficiently extract light from the epitaxial structure 3400. For example, the optical element 4202 may be a diffraction grating. Although the optical element 4202 is shown in fig. 53 as resembling a diffraction grating, the optical element 4202 may be other optical features, such as a lens.

Figure 54 is a flow chart of an embodiment of a process 5400 for etching to isolate portions of an epitaxial structure. Process 5400 begins at step 5402, where an epitaxial structure (e.g., epitaxial structure 3400 in fig. 34) is obtained at step 5402. The epitaxial structure may be a layered structure including a first doped semiconductor layer (e.g., first doped semiconductor layer 3402 in fig. 32), a second doped semiconductor layer (e.g., second doped semiconductor layer 3404 in fig. 32), and/or a light emitting layer (e.g., light emitting layer 3408 in fig. 32) between the first doped semiconductor layer and the second doped semiconductor layer. In some embodiments, the epitaxial structure is obtained by growing a first doped semiconductor layer, a light emitting layer, and a second doped semiconductor layer on a substrate (e.g., substrate 3406 in fig. 34).

In step 5404, the epitaxial structure is etched to singulate the epitaxial structure to form a plurality of LEDs. For example, epitaxial structure 3400 in fig. 38, 46, and 52 is etched to form mesa 3808 (as shown in fig. 38). Although only two mesas are shown in fig. 38, it should be understood that there are many mesas (e.g., one mesa for each light source 1402 in the array 1400 of fig. 14).

In step 5406, a first thin film layer is deposited over the epitaxial structure (e.g., transistor layer 1606 is formed over epitaxial structure 3400 in fig. 39). In step 5408, a second thin film layer is deposited over the epitaxial structure (e.g., interconnect layer 1608 is formed over transistor layer 1606 in fig. 39). In step 5410, a second thin film layer is bonded to the backplate (e.g., backplate 1704 is bonded to thin film circuit layer 1604 by bumps 1502 in fig. 40). In step 5412, a light extraction element (e.g., optical element 4202 in fig. 442) is formed.

In some embodiments, the second doped semiconductor layer may be p-type doped, and the method further comprises bonding a temporary carrier to the second doped semiconductor layer and removing the substrate from the epitaxial structure, wherein the substrate is closer to the first doped semiconductor layer than the second doped semiconductor layer prior to removing the substrate (e.g., removing the substrate as depicted in fig. 37). Etching the epitaxial structure may occur prior to depositing the thin film circuit layer to the epitaxial structure (e.g., fig. 38). Etching the epitaxial structure may occur after bonding the thin film circuit layer to the backplate (e.g., fig. 41). Etching the epitaxial structure may occur after depositing the first thin film layer and before applying the second thin film layer (e.g., fig. 49).

Instead of etching to isolate the epitaxial structure to form the LED array, other forms of isolation may be used. For example, ion implantation may be used to isolate the epitaxial structure to form a plurality of LEDs. Referring next to fig. 55-64, cross-sections of embodiments of a process for isolating epitaxial structures by ion implantation are shown. Fig. 55 is a simplified cross-section of an embodiment of an epitaxial structure 3400 similar to epitaxial structure 3400 in fig. 34. The epitaxial structure 3400 includes a first doped semiconductor layer 3402 and a second doped semiconductor layer 3404. The first and second doped semiconductor layers 3402 and 3404 are on the substrate 3406. In some embodiments, the substrate 3406 is part of an epitaxial structure 3400. The epitaxial structure 3400 may further include a light emitting layer 3408 between the first and second doped semiconductor layers 3402 and 3404. In the illustrated embodiment, the first doped semiconductor layer 3402 is n-type doped and the second doped semiconductor layer 3404 is p-type doped. In other embodiments, the first doped semiconductor layer 3402 may be p-type doped and/or the second doped semiconductor layer 3404 may be n-type doped.

Fig. 56 is a simplified cross-section of an embodiment of p-side isolation of an external structure by ion implantation. Ions are implanted into the second doped semiconductor layer 3404, altering a portion of the second doped semiconductor layer 3404 to form a blocking region 5602. The blocking region 5602 isolates adjacent portions of the second doped semiconductor layer 3404 to form a plurality of LEDs. In some embodiments, other isolation processes (e.g., chemical or GaN modification) are used instead of or in combination with ion implantation. The blocking region 5602 may have a two-dimensional shape (e.g., in the x/y plane) similar to the trench 3802 in fig. 38.

Fig. 57 is a simplified cross-section of an embodiment of an epitaxial structure 3400 in which a contact layer 3502 and a temporary bonding layer 3504 are deposited on the epitaxial structure 3400. Contact layer 3502 and temporary bonding layer 3504 are applied to epitaxial structure 3400 in a manner similar to that described in fig. 35.

Fig. 58 is a simplified cross section of an embodiment of an epitaxial structure 3400 in which a temporary carrier 3602 is bonded to the epitaxial structure 3400. Temporary carrier 3602 is secured to epitaxial structure 3400 by temporary bonding layer 3504. Temporary carrier 3602 is attached to the p-side of epitaxial structure 3400 (e.g., p-type doped second doped semiconductor layer 3404 is closer to temporary carrier 3602 than n-type doped first doped semiconductor layer 3402).

Fig. 59 is a simplified cross-section of an embodiment of an epitaxial structure 3400 with a substrate (e.g., substrate 3406 in fig. 58) removed from the epitaxial structure 3400. After removing the substrate, the epitaxial structure 3400 is planarized (e.g., by Chemical Mechanical Planarization (CMP)). The n-type doped first doped semiconductor layer 3402 is exposed and planarized.

Fig. 60 is a simplified cross-section of an embodiment of n-side isolation of the external structure 3400 by ion implantation. Ions are implanted into the first doped semiconductor layer 3402, altering a portion of the first doped semiconductor layer 3402 to form a blocking region 6002. The blocking region 6002 isolates adjacent portions of the first doped semiconductor layer 3402 to form a plurality of LEDs. In some embodiments, other isolation processes (e.g., chemical or GaN modification) are used instead of or in combination with ion implantation. The blocking region 6002 may have a two-dimensional shape (e.g., in the x/y plane) similar to the blocking region 5602 in the second doped semiconductor layer 3404.

Fig. 61 is a simplified cross-section of an embodiment of thin film circuit layer 1604 deposited on epitaxial structure 3400 similar to fig. 39. Thin film circuit layer 1604 includes transistor layer 1606 and interconnect layer 1608. A transistor layer 1606 is formed on an exposed surface of the (e.g., n-type) first doped semiconductor layer 3402. Transistor layer 1606 may include a thin film transistor semiconductor material.

Fig. 62 is a simplified cross-section of an embodiment of thin film circuit layer 1604 bonded to backplate 1704 of fig. 40. The epitaxial structure 3400, thin film circuit layer 1604, and backplate 1704 are vertically aligned (e.g., stacked). Fig. 62 shows temporary carrier 3602 extending (in the z-direction) over epitaxial structure 3400.

Fig. 63 is a simplified cross-section of an embodiment similar to fig. 41 in which temporary carrier (e.g., temporary carrier 3602 in fig. 62) is removed after bonding back plate 1704 to thin film circuit layer 1604. In some embodiments, the temporary carrier and/or temporary bonding layer is removed by a solvent (e.g., a solvent that dissolves the temporary bonding layer). Removing the temporary carrier exposes second doped semiconductor layer 3404 and/or contact layer 3502.

Fig. 64 is a simplified cross-section of an embodiment similar to fig. 42 in which an optical element 4202 is added to an epitaxial structure 3400. The optical element 4202 may be used to more efficiently extract light from the epitaxial structure 3400. For example, the optical element 4202 may be a diffraction grating. Although the optical element 4202 is shown in fig. 64 as resembling a diffraction grating, the optical element 4202 may be other optical features, such as a lens.

Although fig. 58-64 depict isolating (e.g., by ion implantation) the first doped semiconductor layer 3402 and the second doped semiconductor layer 3404, in some embodiments only one doped semiconductor layer is isolated. For example, only the first doped semiconductor layer 3402 is isolated by ion implantation, or only the second doped semiconductor layer 3404 is isolated, not both.

Fig. 65 is a flow chart of an embodiment of a process 6500 for isolating portions of an epitaxial structure using ion implantation to form an LED array. Process 6500 begins at step 6502, where an epitaxial structure (e.g., epitaxial structure 1400 in fig. 55) is obtained in step 6502. The epitaxial structure may be a layered structure having a first doped semiconductor layer, a second doped semiconductor layer, and/or a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer. The temporary carrier may be bonded to the epitaxial structure with the second doped semiconductor structure between the first doped semiconductor structure and the temporary carrier and the first doped semiconductor structure between the second doped semiconductor structure and the substrate of the epitaxial structure (e.g., fig. 58). The substrate may be removed (e.g., fig. 59).

In step 6504, ions are implanted into the first doped semiconductor layer to isolate portions of the first doped semiconductor layer to form a plurality of LEDs (e.g., fig. 60). In step 6506, a thin film circuit layer is applied to the epitaxial structure (e.g., fig. 61). In step 8508, the thin film circuit layer is bonded to the back plate (e.g., fig. 62). The temporary carrier may be removed (e.g., fig. 63). In step 6510, light extraction elements (e.g., fig. 64) are formed.

In some embodiments, the process 6500 may further include implanting ions in the second doped semiconductor layer prior to bonding the temporary carrier to the epitaxial structure (e.g., fig. 56). In some embodiments, the first doped semiconductor layer is not implanted with ions.

Fig. 66 is a flow chart of an embodiment of a process 6600 for isolating portions of an epitaxial structure. Process 6600 begins at step 6602, where an epitaxial structure (e.g., epitaxial structure 34 in fig. 35 or 55) is obtained in step 6602. The epitaxial structure is a layered structure comprising: a first doped semiconductor layer (e.g., first doped semiconductor layer 3402 in fig. 35 or 55); a second doped semiconductor layer (e.g., second doped semiconductor layer 3404 in fig. 35 or 55); and/or a light emitting layer (e.g., light emitting layer 3408 in fig. 35 or 55) between the first doped semiconductor layer and the second doped semiconductor layer.

In step 6604, portions of the epitaxial structure are isolated. For example, isolating the epitaxial structure may include isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer to form a plurality of LEDs. Examples of portions of the isolated epitaxial structure are depicted in fig. 38, 46, 49, 56, and 60. The isolation of portions of the epitaxial structure may be accomplished by various processes including etching and ion implantation.

In step 6606, a thin film circuit layer (e.g., thin film circuit layer 1604) is deposited on the epitaxial structure. The thin film circuit layer may include a first thin film layer (e.g., transistor layer 1606), wherein the first thin film layer includes a plurality of transistors, and/or a second thin film layer (e.g., interconnect layer 1608), wherein the second thin film layer includes interconnects for the plurality of transistors.

In step 6608, the thin film circuit layer is bonded to the back plate (e.g., back plate 1704 is bonded to thin film circuit layer 1604 in fig. 40, 44, 51, or 62). In some embodiments, light extraction elements may be formed to the epitaxial structure to couple light out of the light emitting layer. For example, the optical element 4202 in fig. 42, 47, 53, or 64 may be formed.

A temporary carrier (e.g., temporary carrier 3602 in fig. 36 or 58) may be bonded to the epitaxial structure prior to bonding the thin film circuit layer to the epitaxial structure, and/or the temporary carrier may be removed after bonding the thin film circuit layer to the backplate.

In the embodiment of fig. 34 and 55, the first doped semiconductor layer 3402 is n-type doped, while the second doped semiconductor layer 3404 is p-type doped. The p-doped layer may be used as a common layer (e.g., cathode 3014 in fig. 30). In some embodiments, the first doped semiconductor layer 3402 may be p-type doped, and the second doped semiconductor layer 3404 may be n-type doped. If so, temporary carrier 3602 in FIG. 36 or 58 will not be used. However, if the n-doped side is a common side instead of using the p-doped side as the common side, more transistors may be used. The thin film circuit layers are on a non-common side, but in some embodiments the thin film circuit layers may be on a common side where vias are used.

Fig. 67 is a simplified cross-section of an embodiment of an etched epitaxial structure 3400 bonded to a transparent substrate 6702. The transparent display allows the user to see through the display and may be used for AR applications. In fig. 67, two mesas for forming LEDs 6704 are shown for illustration purposes, but a large number of LEDs 6704 are contemplated for an actual display. Trenches 3802 are etched through the epitaxial structure 3400 to separate the LEDs 6704. Although fig. 67 presents a cross-sectional view, the same or similar singulation process may be performed on multiple sides, thereby defining the perimeter of each LED 6704. For example, the LEDs 6704 (e.g., in the x/y plane) may have a square or other shape (as viewed in the negative z-direction) from a top-down view.

Thin film circuit layer 1604 is deposited on epitaxial structure 3400. The thin film circuit layer 1604 is bonded to the transparent substrate 6702. The transparent substrate 6702 may be made of glass or other transparent material. The thin film circuit layer 1604 is electrically coupled to traces 6708 that electrically connect the thin film circuit layer with pads 6710 on the transparent substrate 6702. Although only one trace 6708 and one pad 6710 are shown in fig. 67, it should be understood that there may be many traces 6708 electrically coupling thin film circuit layer 1604 with many pads 6710. Trace 6708 may be made of a transparent conductive material such as Indium Tin Oxide (ITO). The pads 6710 are electrically coupled to the backplate by one or more bumps 1502.

In fig. 67, the epitaxial structure 3400 is disposed horizontally rather than vertically with the backplate 1704. The epitaxial structure 3400 is placed beside the backplate 1704 on the transparent substrate 6702. The horizontal arrangement allows the backplate 1704 with the silicon substrate to be located at the periphery of the display, thereby maintaining the overall transparency of the display.

Although the epitaxial structure 3400 has portions isolated by the trenches 3802, other isolation processes (e.g., ion implantation as discussed in fig. 56 or 60) may be used to singulate the LEDs 6704. In some embodiments, an apparatus includes a transparent substrate 6702, a plurality of LEDs 6704; a thin film circuit layer 1604 comprising a plurality of transistors electrically coupled to a plurality of LEDs, wherein: the plurality of transistors are configured to control operations of the plurality of LEDs, and the thin film circuit layer 1604 is bonded to the transparent substrate 6702; and/or a back plate 1704 bonded to the transparent substrate 6702, wherein: the backplate 1704 is electrically coupled to the thin film circuit layer 1604 (e.g., by bumps 1502, pads 6710, and traces 6708), and/or the backplate 1704 is on the same side of the transparent substrate 6702 as the thin film circuit layer 1604. In some embodiments, the apparatus further comprises a frame of the augmented reality system (e.g., frame 305 in fig. 3) that holds a plurality of LEDs, wherein the plurality of LEDs are part of a display for the augmented reality system (e.g., part of image source 412 in fig. 4).

Fig. 68 is a simplified illustration of traces 6708 from LEDs 6704 in an array on a transparent substrate 6702 to a backplate 1704. One trace 6708 may electrically couple a set 6802 of LEDs 6704 to the backplate 1704. Similar to the multiple LEDs 3010 sharing control lines 3006 in fig. 30, a group 6802 of LEDs 6704 in fig. 68 may share traces 3708. In some embodiments, a group 6802 of LEDs 6704 is considered a plurality of LEDs. The trace 6708 may be between groups 6802 of LEDs 6704.

In some embodiments, a wafer of multiple LEDs 6704 may be bonded to the transparent substrate 6702 to build an array of LEDs 6704. There may be one or more backplanes 1704 bonded to transparent substrate 6702. The back plate 1704 may be disposed on one, two, three or more sides of the array of LEDs 6704. The back plate 1704 is bonded to one side of the transparent substrate 6702 so as not to be in the optical path of the user.

Note that the figures are not necessarily drawn to scale and the relative thicknesses of the layers may be different than those shown in the figures. For example, although some of the figures depict the thin film circuit layer as thicker than the epitaxial structure, the epitaxial structure may be much thicker than the thin film circuit layer.

Fig. 69 is a flow chart of an embodiment of a process 6900 for bonding an LED array to a transparent substrate. Process 6900 begins at step 6902, where an epitaxial structure (e.g., epitaxial structure 34 in fig. 35 or 55) is obtained at step 6902. The epitaxial structure is a layered structure comprising: a first doped semiconductor layer (e.g., first doped semiconductor layer 3402 in fig. 35 or 55); a second doped semiconductor layer (e.g., second doped semiconductor layer 3404 in fig. 35 or 55); and/or a light emitting layer (e.g., light emitting layer 3408 in fig. 35 or 55) between the first doped semiconductor layer and the second doped semiconductor layer.

In step 6904, a thin film circuit layer (e.g., thin film circuit layer 1604) is applied to the epitaxial structure. In step 6906, portions of the epitaxial structure are isolated. For example, isolating the epitaxial structure may include isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer to form a plurality of LEDs. Examples of portions of the isolated epitaxial structure are depicted in fig. 38, 46, 49, 56, and 60. The isolation of portions of the epitaxial structure may be accomplished by various processes including etching and ion implantation. The isolating thin film circuit layer may be performed before, after, or between the layers of the thin film circuit layer are applied.

In step 6908, after the thin film circuit layer is applied to the epitaxial structure, the thin film circuit layer is bonded to the transparent substrate (e.g., thin film circuit layer 1604 is bonded to transparent substrate 6702 in fig. 67). The transparent substrate is transparent (e.g., 75%, 85%, 90%, 95%, 99% or higher transmittance for light having wavelengths between 450nm and 700 nm; light having wavelengths such as red, green, and/or blue has a transmittance of greater than 75%, 85%, 90%, 95%, or 99% through the transparent substrate).

In step 6910, a back plate (e.g., back plate 1704 in fig. 67) is bonded to the transparent substrate, wherein the back plate is electrically coupled to the thin film circuit layer and/or the thin film circuit layer is on the same side of the transparent substrate as the back plate.

Fig. 70 is a simplified block diagram of an example electronic system 7000 for implementing an example near-eye display (e.g., an HMD device) of some of the examples disclosed herein. The electronic system 7000 may be used as an electronic system for the HMD device or other near-eye display described above. In this example, the electronic system 7000 can include one or more processors 7010 and memory 7020. The processor 7010 may be configured to execute instructions for performing operations at a plurality of components and may be, for example, a general purpose processor or microprocessor suitable for implementation within a portable electronic device. The processor 7010 may be communicatively coupled with various components within the electronic system 7000. To achieve this communicative coupling, the processor 7010 may communicate with other illustrated components via a bus 7040. Bus 7040 may be any subsystem suitable for communicating data within electronic system 7000. Bus 7040 may include multiple computer buses and additional circuitry for transferring data.

The memory 7020 may be coupled to the processor 7010. In some embodiments, the memory 7020 may provide both short-term and long-term storage and may be divided into several units. The memory 7020 may be volatile (such as Static Random Access Memory (SRAM) and/or Dynamic Random Access Memory (DRAM)) and/or nonvolatile (such as Read Only Memory (ROM), flash memory, etc.). In addition, the memory 7020 may include a removable storage device, such as a Secure Digital (SD) card. Memory 7020 may provide storage of computer readable instructions, data structures, program modules, and other data for electronic system 7000. In some embodiments, the memory 7020 may be distributed among different hardware modules. The instructions and/or code sets may be stored on the memory 7020. The instructions may take the form of executable code executable by the electronic system 7000 and/or may take the form of source code and/or installable code (e.g., using any of a variety of commonly available compilers, installers, compression/decompression utilities, etc.) which, when compiled and/or installed on the electronic system 7000, may take the form of executable code.

In some embodiments, the memory 7020 may store a plurality of application modules 7022 to 7024, and the application modules 7022 to 7024 may include any number of applications. Examples of applications may include: a gaming application, a conferencing application, a video playback application, or other suitable application. Applications may include depth sensing functions or eye tracking functions. The application modules 7022-7024 may include specific instructions to be executed by the processor 7010. In some embodiments, particular applications or portions of the application modules 7022-7024 may be executed by other hardware modules 7080. In particular embodiments, memory 7020 may additionally comprise secure memory that may include additional security controls to prevent copying or other unauthorized access to secure information.

In some embodiments, the memory 7020 may include an operating system 7025 loaded therein. The operating system 7025 may be operative to initiate execution of instructions provided by the application modules 7022-7024 and/or manage other hardware modules 7080 and interfaces with the wireless communication subsystem 7030, which wireless communication subsystem 7030 may include one or more wireless transceivers. The operating system 7025 may be adapted to perform other operations on the components of the electronic system 7000, including thread management (threading management), resource management, data storage control, and other like functions.

The wireless communication subsystem 7030 may include, for example, infrared communication devices, wireless communication devices, and/or chipsets (such asDevices, IEEE 802.11 devices, wi-Fi devices, wiMax devices, cellular communication facilities, etc.), and/or the like. The electronic system 7000 may include one or more antennas 7034 for wireless communication as part of the wireless communication subsystem 7030 or as a separate component coupled to any portion of the system. Depending on the desired functionality, the wireless communication subsystem 7030 may include a separate transceiver to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and/or network types, such as a Wireless Wide Area Network (WWAN), a Wireless Local Area Network (WLAN), or a Wireless Personal Area Network (WPAN). The WWAN may be, for example, a WiMax (IEEE 802.16) network. The WLAN may be, for example, an IEEE 802.11x network. The WPAN may be, for example, a bluetooth network, IEEE 802.15x, or some other type of network. The techniques described herein may also be used for any of WWAN, WLAN, and/or WPANAnd (5) combining. The wireless communication subsystem 7030 may allow for the exchange of data with networks, other computer systems, and/or any other devices described herein. The wireless communication subsystem 7030 may include means for transmitting or receiving data, such as an identifier of an HMD device, location data, geographic map, heat map, photograph, or video, using the antenna 7034 and wireless link 7032. The wireless communication subsystem 7030, the processor 7010, and the memory 7020 may together comprise at least a portion of one or more devices for performing some of the functions disclosed herein.

Embodiments of the electronic system 7000 may also include one or more sensors 7090. The sensor 7090 may include, for example, an image sensor, an accelerometer, a pressure sensor, a temperature sensor, a proximity sensor (proximity sensor), a magnetometer, a gyroscope, an inertial sensor (e.g., a module that combines an accelerometer and a gyroscope), an ambient light sensor, or any other similar module operable to provide a sensing output (sensor output) and/or receive a sensing input, such as a depth sensor or a position sensor. For example, in some implementations, the sensors 7090 may include one or more Inertial Measurement Units (IMUs) and/or one or more position sensors. Based on measurement signals received from the one or more position sensors, the IMU may generate calibration data indicative of an estimated position of the HMD device relative to an initial position of the HMD device. The position sensor may generate one or more measurement signals in response to motion of the HMD device. Examples of the position sensor may include, but are not limited to: one or more accelerometers, one or more gyroscopes, one or more magnetometers, another suitable type of sensor that detects motion, one type of sensor for error correction of the IMU, or any combination thereof. The position sensor may be located external to the IMU, internal to the IMU, or any combination thereof. At least some of the sensors may sense using a structured light pattern.

The electronic system 7000 may include a display module 7060. The display module 7060 may be a near-eye display and may graphically present information from the electronic system 7000 to a user, such as images, video, and various instructions. Such information may originate from one or more application modules 7022-7024, a virtual reality engine 7026, one or more other hardware modules 7080, combinations thereof, or any other suitable means for parsing graphical content for a user (e.g., via an operating system 7025). The display module 7060 may use LCD technology, LED technology (including, for example, OLED, ILED, μ -LED, AMOLED, TOLED, etc.), light emitting polymer display (LPD) technology, or some other display technology.

The electronic system 7000 may include a user input/output module 7070. The user input/output module 7070 may allow a user to send an action request to the electronic system 7000. An action request may be a request to perform a particular action. For example, an action request may be to launch or end an application or to perform a particular action within an application. The user input/output module 7070 may include one or more input devices. Example input devices may include a touch screen, touch pad, microphone, buttons, dials, switches, keyboard, mouse, game controller, or any other suitable device for receiving an action request and communicating the received action request to electronic system 7000. In some embodiments, the user input/output module 7070 may provide haptic feedback to the user in accordance with instructions received from the electronic system 7000. For example, haptic feedback may be provided when an action request is received or has been performed.

The electronic system 7000 may include a camera 7050, and the camera 7050 may be used to take a picture or video of the user, for example, to track the eye position of the user. The camera 7050 may also be used to take photographs or videos of an environment, for example, for VR, AR, or MR applications. The camera 7050 may include, for example, a Complementary Metal Oxide Semiconductor (CMOS) image sensor having millions or tens of millions of pixels. In some implementations, the camera 7050 may include two or more cameras that may be used to capture 3D images.

In some embodiments, the electronic system 7000 may include a plurality of other hardware modules 7080. Each other hardware module 7080 may be a physical module within the electronic system 7000. While each of the other hardware modules 7080 may be permanently configured as a structure, some of the other hardware modules 7080 may be temporarily configured to perform particular functions or be temporarily activated. Examples of other hardware modules 7080 may include, for example, audio output and/or input modules (e.g., microphones or speakers), near Field Communication (NFC) modules, rechargeable batteries, battery management systems, wired/wireless battery charging systems, and so forth. In some embodiments, one or more functions of other hardware modules 7080 may be implemented in software.

In some embodiments, the memory 7020 of the electronic system 7000 can also store a virtual reality engine 7026. The virtual reality engine 7026 may execute applications within the electronic system 7000 and receive position information, acceleration information, velocity information, predicted future positions of the HMD device, or any combination thereof, from various sensors. In some embodiments, the information received by the virtual reality engine 7026 may be used to generate signals (e.g., display instructions) to the display module 7060. For example, if the received information indicates that the user has seen to the left, the virtual reality engine 7026 may generate content for the HMD device that reflects the user's movements in the virtual environment. Further, the virtual reality engine 7026 can perform actions within the application and provide feedback to the user in response to action requests received from the user input/output module 7070. The feedback provided may be visual feedback, auditory feedback, or tactile feedback. In some implementations, the processor 7010 can include one or more GPUs that can execute a virtual reality engine 7026.

In various embodiments, the hardware and modules described above may be implemented on a single device or on multiple devices that may communicate with each other using wired or wireless connections. For example, in some implementations, some components or modules, such as the GPU, the virtual reality engine 7026, and applications (e.g., tracking applications), may be implemented on a console that is separate from the head mounted display device. In some implementations, one console may be connected to or support more than one HMD.

In alternative configurations, different and/or additional components may be included in electronic system 7000. Similarly, the functionality of one or more components may be distributed among multiple components in a manner different from that described above. For example, in some embodiments, electronic system 7000 may be modified to include other system environments, such as an AR system environment and/or an MR environment.

The methods, systems, and devices discussed above are examples. Various embodiments may omit, replace, or add various procedures or components as appropriate. For example, in alternative configurations, the described methods may be performed in a different order than described, and/or stages may be added, omitted, and/or combined. Furthermore, features described with respect to certain embodiments may be combined in various other embodiments. The different aspects and elements of the embodiments may be combined in a similar manner. Furthermore, technology is evolving and, as such, many elements are examples and do not limit the scope of the disclosure to those specific examples.

Specific details are given in the description to provide a thorough understanding of the embodiments. However, embodiments may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. This description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the foregoing description of the embodiments will provide those skilled in the art with an enabling description (enabling description) for implementing the various embodiments. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure.

Further, some embodiments are described as a process, which is depicted as a flowchart or a block diagram. Although each may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. Furthermore, the order of operations may be rearranged. The process may have additional steps not included in the figures. Furthermore, embodiments of the methods may be implemented in hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the associated tasks may be stored in a computer readable medium such as a storage medium. The processor may perform the associated tasks.

It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific requirements. For example, custom or dedicated hardware may also be used, and/or specific elements may be implemented in hardware, software (including portable software, such as applets (applets), etc.), or both. In addition, connections to other computing devices, such as network input/output devices, may be employed.

Referring to the drawings, components that may include memory may include non-transitory machine-readable media. The terms "machine-readable medium" and "computer-readable medium" may refer to any storage medium that participates in providing data that causes a machine to operation in a specific fashion. In the embodiments provided above, various machine-readable media may be involved in providing instructions/code to a processing unit and/or other devices for execution. Additionally or alternatively, a machine-readable medium may be used to store and/or carry such instructions/code. In many implementations, the computer-readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including but not limited to, non-volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media (e.g., a Compact Disk (CD) or Digital Versatile Disk (DVD)), punch cards, paper tape, any other physical medium with patterns of holes, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine executable instructions that may represent a procedure, a function, a subroutine, a program, a routine, an application (App), a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements.

Those of skill in the art would understand that information and signals used to transfer the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips (chips) may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The terms "and" or "as used herein may include a variety of meanings that are also contemplated to depend at least in part on the context in which the terms are used. Typically, or if used in association with a list, such as A, B or C, is intended to mean A, B and C (used herein in the inclusive sense) and A, B or C (used herein in the exclusive sense). Furthermore, the terms "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. It should be noted, however, that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, at least one of the terms "..if used in association with a list, e.g., A, B or C, can be construed to represent any combination of A, B and/or C, e.g., A, AB, AC, BC, AA, ABC, AAB, AABBCCC, etc.

Furthermore, while certain embodiments have been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are possible. Some embodiments may be implemented in hardware only, or in software only, or using a combination thereof. In one example, software may be implemented with a computer program product containing computer program code or instructions executable by one or more processors for performing any or all of the steps, operations, or processes described in this disclosure, wherein the computer program may be stored on a non-transitory computer readable medium. The various processes described herein may be implemented on the same processor or on different processors in any combination.

Where a device, system, component, or module is described as being configured to perform a certain operation or function, such configuration may be accomplished, for example, by designing an electronic circuit that performs the operation, by programming a programmable electronic circuit (e.g., a microprocessor) to perform the operation (e.g., by executing computer instructions or code), or a processor or core programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. The processes may communicate using various techniques, including but not limited to conventional techniques for inter-process communication, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, deletions, and other modifications and changes may be made thereto without departing from the broader spirit and scope as set forth in the claims. Thus, while specific embodiments have been described, these embodiments are not intended to be limiting. Various modifications and equivalents are intended to be within the scope of the claims appended hereto.

Claims (20)

1. A display device, comprising:

a Light Emitting Diode (LED) array comprising a layered epitaxial structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;

a thin film circuit layer deposited on the LED array instead of bonded using bond pads, wherein the LED array is a support structure for the thin film circuit layer and the thin film circuit layer includes circuitry for controlling operation of LEDs in the LED array; and

a back plane coupling the back plane with the thin film circuit layer using a plurality of metal bonds between the back plane and the thin film circuit layer, the back plane including a drive circuit for supplying current to the thin film circuit layer through the plurality of metal bonds, wherein a number of metal bonds in the plurality of metal bonds is less than a number of LEDs in the LED array.

2. The apparatus of claim 1, wherein:

the LED array having a light emitting side and a side opposite the light emitting side, and the thin film circuit layer being deposited on the side of the LED array opposite the light emitting side; and

the thin film circuit layer includes transistors and capacitors that are interconnected to form a pixel circuit for controlling the operation of the LEDs in the LED array.

3. The apparatus of claim 2, wherein the pixel circuit implements analog, pulse code modulation, or pulse width modulation to control intensities of LEDs in the LED array.

4. The apparatus of claim 2, wherein the storage capacitor of the pixel circuit is configured to be coupled to the data line by one or more select signals.

5. The apparatus of claim 2, wherein pixel circuits are interconnected to reduce the number of metal bonds between the back plane and the thin film circuit layer.

6. The apparatus of claim 1, wherein a single pixel circuit is connected to a plurality of row select signals.

7. The apparatus of claim 1, wherein the backplane is configured to transmit a global signal to the thin film circuit layer through one of the plurality of metal bonds, wherein the global signal comprises one or more of: row data lines, column data lines, analog bias, supply voltage, pulse clock, or test enable features.

8. The apparatus of claim 1, wherein no transistor in the thin film circuit layer is used to charge/discharge a global network.

9. The apparatus of claim 1, wherein the thin film circuit layer comprises a selector multiplexer.

10. The apparatus of claim 9, wherein:

the selector multiplexer includes a common signal line in the thin film circuit layer electrically coupled with a plurality of transistors in the thin film circuit layer; and

the plurality of transistors are configured to be alternately activated such that a current from the common signal line periodically passes through each of the plurality of transistors.

11. The apparatus of claim 1, wherein the thin film circuit layer comprises a memory circuit and a modulator circuit.

12. The apparatus of claim 1, wherein:

assigning a unique address to each LED in the LED array; and

the control signals include the unique address and the operation signals to control the operation of the selected LEDs in the LED array.

13. The apparatus of claim 12, wherein:

the operating signal is configured to control the magnitude of the current flowing through the selected LED; and

The operating signal comprises a digital signal representing a percentage of time during a period of time that current flows to the selected LED.

14. The device of claim 1, wherein the spacing between the centers of the LEDs is no more than three microns apart.

15. A method of making a display device, comprising:

obtaining a semiconductor structure, wherein the semiconductor structure is a layered epitaxial structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;

depositing, rather than using, a bond pad to bond a thin film circuit layer on the semiconductor structure;

forming a circuit for controlling light emission of the light emitting layer in the thin film circuit layer;

obtaining a back plate including a driving circuit for supplying current to the thin film circuit layer through a plurality of metal bonds between the back plate and the thin film circuit layer;

forming a plurality of interconnects on the thin film circuit layer or on the back plane;

bonding the back plate to the thin film circuit layer using the plurality of interconnects, wherein the plurality of interconnects become the plurality of metal bonds after bonding; and

A Light Emitting Diode (LED) array is formed from the semiconductor structure, wherein a number of metal bonds in the plurality of metal bonds is less than a number of LEDs in the LED array, the LED array having a light emitting side and a side opposite the light emitting side, and wherein the thin film circuit layer is deposited on the side opposite the light emitting side.

16. The method of claim 15, wherein obtaining the backplate comprises forming a plurality of CMOS transistors and interconnects in a silicon device layer of a silicon wafer.

17. The method of claim 15, wherein forming the LED array comprises singulating the semiconductor structure, and wherein singulating the semiconductor structure occurs prior to bonding the back plate to the thin film circuit layer.

18. The method of claim 15, wherein the thin film circuit layer is formed on the semiconductor structure at the wafer level.

19. The method of claim 15, wherein the backplate comprises circuitry formed in the backplate prior to bonding.

20. A system for a near-eye display, the system comprising:

a frame;

a waveguide display coupled with the frame; and

A projector comprising a light source configured to direct light to the waveguide display, wherein the light source comprises:

a Light Emitting Diode (LED) array comprising a layered epitaxial structure comprising a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;

a thin film circuit layer deposited on the LED array instead of bonded using bond pads, wherein the LED array is a support structure for the thin film circuit layer and the thin film circuit layer includes circuitry for controlling operation of LEDs in the LED array; and

a back plane coupling the back plane with the thin film circuit layer using a plurality of metal bonds between the back plane and the thin film circuit layer, the back plane including a drive circuit for supplying current to the thin film circuit layer through the plurality of metal bonds, wherein a number of metal bonds in the plurality of metal bonds is less than a number of LEDs in the LED array.