CN113365009A - Output circuit of pixel array and image sensor - Google Patents
Output circuit of pixel array and image sensor Download PDFInfo
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- CN113365009A CN113365009A CN202110663085.1A CN202110663085A CN113365009A CN 113365009 A CN113365009 A CN 113365009A CN 202110663085 A CN202110663085 A CN 202110663085A CN 113365009 A CN113365009 A CN 113365009A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
Abstract
An output circuit of a pixel array is provided, wherein a row of pixel units is correspondingly coupled with an analog-to-digital conversion unit, and one analog-to-digital conversion unit is correspondingly coupled with K rows of pixel units; a quantized signal input and a reference signal input are connected to the control unit, the first and second ramp signal inputs being adapted to input a pair of differential ramp signals; the analog-to-digital conversion unit carries out quantization processing on the basis of signals received by the quantized signal input end, the reference signal input end, the first ramp signal input end and the second ramp signal input end so as to output a quantization result; the control unit is suitable for selecting two rows from a plurality of rows of pixel units coupled to the same analog-to-digital conversion unit, outputting the reset voltage or signal voltage provided by one pixel unit on one row to a quantization signal input end of the analog-to-digital conversion unit, and outputting the reset voltage provided by the other pixel unit on the other row to a reference signal input end of the analog-to-digital conversion unit.
Description
Technical Field
The invention relates to the field of sensors, in particular to an output circuit of a pixel array and an image sensor.
Background
Charge Coupled Device (CCD) image sensors have long dominated the image sensor market, but their driving circuits and signal processing circuits are difficult to integrate with the pixel array, and require higher operating voltages and higher costs.
CMOS Image Sensors (CIS) have advantages that are not comparable to CCD image sensors, such as integration with pixel arrays and processing circuit chips, low operating voltage, and the like. In the CIS, an Analog-to-Digital Converter (ADC) is an important component of a readout circuit, and plays a role of a bridge connecting an Analog signal and a Digital signal, so that the accuracy and speed of the ADC largely determine the performance of the CIS.
Chinese patent application publication No. CN 101867687a discloses an analog-to-digital converter, a solid-state image sensing device, and a camera system, the analog-to-digital converter including a first comparator that compares an input signal with a first reference signal that is a ramp wave having a predetermined polarity, and inverts an output signal thereof when the input signal coincides with the first reference signal; a second comparator that compares the input signal with a second reference signal that is a ramp wave having a different polarity from the first reference signal, and inverts an output signal thereof when the input signal coincides with the second reference signal; and a counter for counting to measure a comparison time taken by the first comparator and the second comparator, wherein the counter stops a counting operation when any one of an output signal of the first comparator and an output signal of the second comparator is first inverted. The technical scheme of this patent application can reduce power consumption.
However, as can be seen from the technical solutions of the above-mentioned published patent applications, each column of pixel units is connected with a digital-to-analog converter, the digital-to-analog converter uses a column ADC, and the column ADC may cause row noise, and the image may appear as a horizontal streak. Dark column reference pixels are usually required to eliminate the striations by either superimposing power noise on the ramp signal or inversely on the pixel signal. But the chip area of such an image sensor is large.
Disclosure of Invention
The problem to be solved by the invention is the chip area of the existing image sensor.
In order to solve the above problem, the present invention provides an output circuit of a pixel array, where the pixel array includes M rows of pixel units, M is greater than or equal to 2, and the output circuit includes: the device comprises a control unit and N analog-to-digital conversion units, wherein N is more than or equal to 1; one row of pixel units are correspondingly coupled with one analog-to-digital conversion unit, one analog-to-digital conversion unit is correspondingly coupled with K rows of pixel units, and K is more than or equal to 2; the analog-to-digital conversion unit includes: a quantized signal input, a reference signal input, a first ramp signal input, and a second ramp signal input; the quantized signal input terminal and the reference signal input terminal are connected to the control unit, and the first ramp signal input terminal and the second ramp signal input terminal are suitable for inputting a pair of differential ramp signals; the analog-to-digital conversion unit carries out quantization processing on the basis of signals received by the quantized signal input end, the reference signal input end, the first ramp signal input end and the second ramp signal input end so as to output a quantization result; the control unit is suitable for selecting two rows from a plurality of rows of pixel units coupled to the same analog-to-digital conversion unit, outputting the reset voltage or signal voltage provided by one pixel unit on one row to a quantization signal input end of the analog-to-digital conversion unit, and outputting the reset voltage provided by the other pixel unit on the other row to a reference signal input end of the analog-to-digital conversion unit.
The invention also provides an image sensor which comprises a pixel array and the output circuit.
Compared with the prior art, the technical scheme of the invention has the following advantages:
by using the output circuit provided by the invention, each analog-to-digital conversion unit corresponds to a plurality of rows of pixel units, the control unit selects two rows from the plurality of rows of pixel units coupled to the same analog-to-digital conversion unit, one row of pixel units is output as a reference signal, and the other row of pixel units is output as a quantization signal, so that the horizontal stripe noise introduced by a pixel power supply can be greatly reduced, a dark row of reference pixels is not required to be additionally arranged to provide the reference signal, and the chip area is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of an image sensor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an image sensor according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating waveforms of signals on respective signal lines during quantization according to the present invention;
FIG. 4 is a schematic diagram of an analog-to-digital conversion unit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a ramp signal generating unit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a ramp signal waveform according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The present embodiment provides an output circuit of a pixel array. The pixel array comprises M rows of pixel units, and M is more than or equal to 2. The output circuit includes: n analog-to-digital conversion units and a control unit, wherein N is more than or equal to 1.
One row of pixel units is correspondingly coupled with one analog-to-digital conversion unit, one analog-to-digital conversion unit is correspondingly coupled with K rows of pixel units, K is larger than or equal to 2, and optionally, K is equal to M/N.
The analog-to-digital conversion unit includes: a quantized signal input, a reference signal input, a first ramp signal input, and a second ramp signal input.
The quantized signal input and the reference signal input are connected to the control unit, and the first ramp signal input and the second ramp signal input are adapted to input a pair of differential ramp signals. The analog-to-digital conversion unit carries out quantization processing on the basis of signals received by the quantization signal input end, the reference signal input end, the first ramp signal input end and the second ramp signal input end to generate quantized signals.
The control unit is suitable for selecting two rows from a plurality of rows of pixel units coupled to the same analog-to-digital conversion unit, outputting the reset voltage or signal voltage provided by one pixel unit on one row to a quantization signal input end of the analog-to-digital conversion unit, and outputting the reset voltage provided by the other pixel unit on the other row to a reference signal input end of the analog-to-digital conversion unit.
In the embodiment, one analog-to-digital conversion unit is correspondingly coupled to a plurality of columns of pixel units, so that the plurality of columns of pixel units share one analog-to-digital conversion unit, which can reduce the number of analog-to-digital conversion units, thereby reducing the chip area.
In general, the transfer functions of pixel power supply noise to interference of quantized signals and reference signals are basically the same, and the differential mode power supply rejection ratio of differential ramp signals is also strong. Therefore, by using the output circuit of the embodiment, the control unit selects two rows from a plurality of rows of pixel units coupled to the same analog-to-digital conversion unit, one row outputs as a reference signal, and the other row outputs as a quantization signal, thereby greatly reducing the horizontal stripe noise introduced by the pixel power supply.
As shown in fig. 1, taking an example that the pixel array includes 2 rows and 2 columns of pixel units, the image sensor includes: a pixel array and an output circuit thereof. The pixel array includes 2 rows and 2 columns of pixel cells. The analog-to-digital conversion unit 4 is correspondingly coupled to two columns of pixel units, namely, the 1 st column of pixel unit and the 2 nd column of pixel unit of the pixel array. The 1 st column of pixel units of the pixel array comprises: pixel cell 11 and pixel cell 21. The 2 nd column pixel array of the pixel array includes a pixel unit 12 and a pixel unit 22.
The pixel units in the same pixel array have the same structure. For convenience of explanation, only the transistor of the pixel unit 11 is identified and described, and it is understood that other pixel units have the same structure.
In any pixel unit, the photosensitive unit D is connected with an input end of a transmission tube Tx, and an output end of the transmission tube Tx is connected with an input end of a reset tube Tst, a control end of a power tube Ts and a storage capacitor C; the output end of the reset tube Tst is connected with the input end of a power tube Ts, and the input end of the power tube Ts is suitable for inputting pixel power voltage Vddpix; the output end of the power tube Ts is connected with the input end of the row strobe tube Tsel.
The output ends of the row gate tubes in the same row of pixel units are connected with the same bit line, and the output ends of the row gate tubes in the pixel units in different rows are connected with different bit lines. For example, in the 1 st column of pixel units, the output terminals of all the row gate transistors Tsel are connected to the 1 st bit line BL <0> for outputting the corresponding reset voltage or signal voltage. In the 2 nd column of pixel units, the output terminals of all the row strobes Tsel are connected to the 2 nd bit line BL <1> for outputting the corresponding reset voltage or signal voltage.
The control ends of the row strobe tubes in the same row of pixel units are connected with the same row strobe signal line, and the control ends of the row strobe tubes in the pixel units in different rows are connected with different row strobe signal lines. For example, in the row 1 pixel cell, the control terminals of all the row strobe lines Tsel are connected to the row strobe signal line 1 Rsel <0> for receiving the corresponding row strobe signal. In the row 2 pixel unit, the control terminals of all the row strobe lines Tsel are connected to the row strobe signal line Rsel <1> for receiving the corresponding row strobe signal.
The control ends of the reset tubes in the pixel units in the same row are connected with the same reset signal line, and the control ends of the reset tubes in the pixel units in different rows are connected with different reset signal lines. For example, in the pixel unit in the row 1, the control terminals of the reset transistors Tst are all connected to the 1 st reset signal line Rst <0> for receiving the corresponding reset signals. In the 2 nd row pixel unit, the control terminals of the reset tubes Tst are all connected to the 2 nd reset signal line Rst <1> for correspondingly receiving the reset signals.
In the pixel unit coupled to the same analog-to-digital conversion unit, each transmission tube control end is connected with one transmission control signal line, and different transmission tube control ends are connected with different transmission control signal lines. For example, in the 1 st row and 1 st column pixel unit, the transmission tube Tx control terminal is connected to the 1 st transmission control signal line Tx0<0> for receiving the corresponding transmission control signal. In the row 1 and column 2 pixel units, the transmission transistor Tx control terminal is connected to the 2 nd transmission control signal line Tx1<0> for receiving the corresponding transmission control signal. In the row 2 and column 1 pixel unit, the transmission tube Tx control terminal is connected to the 3 rd transmission control signal line Tx0<1> for receiving the corresponding transmission control signal. In the 2 nd row and 2 nd column pixel unit, the transmission tube Tx control terminal is connected to the 4 th transmission control signal line Tx1<1> for receiving the corresponding transmission control signal.
However, in the pixel units coupled to different analog-to-digital conversion units, different transmission control terminals of the transmission transistor can be connected to the same transmission control signal line. As shown in fig. 2, the image sensor includes: the pixel units in 6 rows and 6 columns and the 3 analog-to-digital conversion units are correspondingly coupled with the storage units in 2 columns. The pass control terminals of the first row and the first column of pixel units and the pass control terminals of the first row and the third column of pixel units are connected to the 1 st pass control signal line Tx0<0 >.
Fig. 3 is a schematic diagram of signal waveforms on respective signal lines in a quantization process. In order to distinguish the signal coincidence, fig. 3 distinguishes the signal waveforms as follows:
dot-dash line- (0 >/Rmpn <0> - (Rmpn) - (: the signal waveforms on the quantized signal input end BLp <0>, the reference signal input end BLn <0> and the second slope signal input end Rmpn are overlapped;
the long dashed line- -BLp <0> and the long dashed line BLp <0> (BL <0>) represent: the quantized signal input end BLp <0> inputs the signal on the 1 st bit line BL <0 >;
short dashed line … … … BLn <0>/Rmpn indicates: the signal waveforms at the reference signal input terminal BLn <0> and the second ramp signal input terminal Rmpn coincide.
The quantization process of the image sensor is explained with reference to fig. 3 and fig. 1.
In this embodiment, a progressive quantization process is adopted, and when quantizing pixel units in a first row:
the 1 st row strobe signal line Rsel <0> is high and the first row of pixel cells is selected.
The 1 st reset signal line Rst <0> outputs a first high level pulse, so that the pixel unit 11 and the pixel unit 12 are reset, the pixel unit 11 and the pixel unit 12 generate reset voltages, and corresponding reset voltages are output through the 1 st bit line BL <0> and the 2 nd bit line BL <1 >.
The control unit 3 outputs a low level signal through the selection signal line BLsel to select the reset voltage on the 1 st bit line BL <0> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and to select the reset voltage on the 2 nd bit line BL <1> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the reset voltage output by the pixel unit 11 by using the reset voltage on the 1 st bit line BL <0> as a quantization signal and the reset voltage on the 2 nd bit line BL <1> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs a quantization result.
After the quantization process is performed on the reset voltage output by the pixel unit 11, the 1 st transmission control signal line Tx0<0> outputs a high level pulse to turn on the transmission transistor Tx in the pixel unit 11, and the 1 st bit line BL <0> outputs a signal voltage.
The control unit 3 still outputs a low level signal through the selection signal line BLsel to select the signal voltage on the 1 st bit line BL <0> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and select the reset voltage on the 2 nd bit line BL <1> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the signal voltage output by the pixel unit 11 by using the signal voltage on the 1 st bit line BL <0> as a quantization signal and the reset voltage on the 2 nd bit line BL <1> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs the quantization result.
After the signal voltage output by the pixel unit 11 is quantized, the 1 st reset signal line Rst <0> outputs a second high-level pulse, so that the pixel unit 11 and the pixel unit 12 are reset again, the pixel unit 11 and the pixel unit 12 generate reset voltages, and corresponding reset voltages are output through the 1 st bit line BL <0> and the 2 nd bit line BL <1 >.
The control unit 3 outputs a high level signal through the selection signal line BLsel to select the reset voltage on the 2 nd bit line BL <1> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and to select the reset voltage on the 1 st bit line BL <0> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the reset voltage output by the pixel unit 12 by using the reset voltage on the 2 nd bit line BL <1> as a quantization signal and the reset voltage on the 1 st bit line BL <0> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs a quantization result.
After the reset voltage outputted from the pixel unit 12 is quantized, the 2 nd transmission control signal line Tx1<0> outputs a high level pulse to turn on the transmission transistor Tx in the pixel unit 12, and the 2 nd bit line BL <1> outputs a signal voltage.
The control unit 3 still outputs a high level signal through the selection signal line BLsel to select the signal voltage on the 2 nd bit line BL <1> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and select the reset voltage on the 1 st bit line BL <0> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the signal voltage output by the pixel unit 12 by using the signal voltage on the 2 nd bit line BL <1> as a quantization signal and the reset voltage on the 1 st bit line BL <0> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs the quantization result. At this point, the correlated double sampling process of the pixel units in the first row is completed.
Next, the second row of pixel cells is quantized:
the 2 nd row strobe signal line Rsel <1> is high and the second row of pixel cells is selected.
The 2 nd reset signal line Rst <1> outputs a first high level pulse so that the pixel unit 21 and the pixel unit 22 are reset, the pixel unit 21 and the pixel unit 22 generate reset voltages, and the corresponding reset voltages are output through the 1 st bit line BL <0> and the 2 nd bit line BL <1 >.
The control unit 3 outputs a low level signal through the selection signal line BLsel to select the reset voltage on the 1 st bit line BL <0> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and to select the reset voltage on the 2 nd bit line BL <1> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the reset voltage output by the pixel unit 21 by using the reset voltage on the 1 st bit line BL <0> as a quantization signal and the reset voltage on the 2 nd bit line BL <1> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs a quantization result.
After the quantization process is performed on the reset voltage output by the pixel unit 21, the 3 rd transmission control signal line Tx0<1> outputs a high level pulse to turn on the transmission transistor Tx in the pixel unit 21, and the 1 st bit line BL <0> outputs a signal voltage.
The control unit 3 still outputs a low level signal through the selection signal line BLsel to select the signal voltage on the 1 st bit line BL <0> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and select the reset voltage on the 2 nd bit line BL <1> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the signal voltage output by the pixel unit 21 by using the signal voltage on the 1 st bit line BL <0> as a quantization signal and the reset voltage on the 2 nd bit line BL <1> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs the quantization result.
After the signal voltage output by the pixel unit 21 is quantized, the 2 nd reset signal line Rst <1> outputs a second high-level pulse, so that the pixel unit 21 and the pixel unit 22 are reset again, the pixel unit 21 and the pixel unit 22 generate reset voltages, and corresponding reset voltages are output through the 1 st bit line BL <0> and the 2 nd bit line BL <1 >.
The control unit 3 outputs a high level signal through the selection signal line BLsel to select the reset voltage on the 2 nd bit line BL <1> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and to select the reset voltage on the 1 st bit line BL <0> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the reset voltage output by the pixel unit 22 by using the reset voltage on the 2 nd bit line BL <1> as a quantization signal and the reset voltage on the 1 st bit line BL <0> as a reference signal based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, and the output end Cmpout <0> of the analog-to-digital conversion unit 4 outputs a quantization result.
After the quantization process is performed on the reset voltage output by the pixel unit 22, the 4 th transmission control signal line Tx1<1> outputs a high level pulse to turn on the transmission transistor Tx in the pixel unit 22, and the 2 nd bit line BL <1> outputs a signal voltage.
The control unit 3 still outputs a high level signal through the selection signal line BLsel to select the signal voltage on the 2 nd bit line BL <1> to be input to the quantization signal input terminal BLp <0> of the analog-to-digital conversion unit 4, and select the reset voltage on the 1 st bit line BL <0> to be input to the reference signal input terminal BLn <0> of the analog-to-digital conversion unit 4.
The analog-to-digital conversion unit 4 quantizes the signal voltage output by the pixel unit 22 based on a pair of differential ramp signals provided by the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn by using the signal voltage on the 2 nd bit line BL <1> as a quantization signal and the reset voltage on the 1 st bit line BL <0> as a reference signal, and the output terminal Cmpout <0> of the analog-to-digital conversion unit 4 outputs the quantization result. And finishing the correlated double sampling process of the pixel units in the second row.
According to the quantization process, each analog-to-digital conversion unit corresponds to a plurality of columns of pixel units, the pixels in the plurality of columns are quantized in a single time sharing mode, the pixel units in the plurality of columns can be used as reference signals to eliminate cross striations, and an independent pixel signal line does not need to be additionally arranged to serve as the reference signal.
The control unit 3 described in this embodiment may include: a signal generation unit and a plurality of multiplexer mux.
One analog-to-digital conversion unit 4 is connected to two multiplexers mux, respectively. The multiplexer mux has K inputs and one output o, i.e. the number of inputs K of the multiplexer mux connected to the same adc unit 4 is the same as the number of columns K of pixel units coupled to the adc unit 4. In the multiplexer mux and the pixel units corresponding to the same analog-to-digital conversion unit 4, K input terminals of each multiplexer mux are uniformly connected to K columns of pixel units one to one.
One of the two multiplexer mux outputs o is connected to the quantisation signal input of the analogue to digital conversion unit 4 and the other is connected to the reference signal input of the analogue to digital conversion unit 4. The signal generating unit is adapted to generate a control signal, and the multiplexer mux selects one of the voltages received at the K input terminals to output to the output o of the multiplexer based on the control signal on the selection signal line BLsel.
The analog-to-digital conversion unit 4 described in this embodiment may be a column ADC. As shown in fig. 4, the analog-to-digital conversion unit 4 may include: a first transconductance comparator G1, a second transconductance comparator G2, an adder 41, and a transimpedance amplifier R.
The positive input terminal of the first transconductance comparator G1 and the negative input terminal of the second transconductance comparator G2 are connected to the quantized signal input terminal BLp <0> and the reference signal input terminal BLn <0> respectively. Specifically, the positive input terminal of the first transconductance comparator G1 is connected to the quantized signal input terminal BLp <0>, and the negative input terminal of the second transconductance comparator G2 is connected to the reference signal input terminal BLn <0 >.
The negative input terminal of the first transconductance comparator G1 and the positive input terminal of the second transconductance comparator G2 are connected to the first ramp signal input terminal Rmpp and the second ramp signal input terminal Rmpn, respectively. Specifically, the negative input terminal of the first transconductance comparator G1 is connected to the first ramp signal input terminal Rmpp, and the positive input terminal of the second transconductance comparator G2 is connected to the second ramp signal input terminal Rmpn.
The output terminal of the first transconductance comparator G1 and the output terminal of the second transconductance comparator G2 are connected to the input terminal of the adder 41. The output end of the adder 41 is connected to the input end Cmpout <0> of the transimpedance amplifier R. The input end of the trans-impedance amplifier R is connected with the output end Cmpout <0> of the analog-to-digital conversion unit 4.
The first transconductance comparator G1 is adapted to compare the quantized signal input BLp <0> with the input signal at the first ramp signal input Rmpp to generate a positive current signal. The positive current signal includes a comparison of the ideal reset voltage or signal voltage with the first ramp signal, and a positive noise disturbance.
The second transconductance comparator G2 is adapted to compare the input signals of the reference signal input BLn <0> and the second ramp signal input Rmpn, generating a negative current signal. The negative current signal contains negative-going noise interference.
The adder 41 adds the positive current signal and the negative current signal, and inputs the addition result to the transimpedance amplifier R to generate a final output voltage signal. Because the noise interference of the positive current signal and the negative current signal is mutually offset, the final output voltage signal only contains the comparison result of the ideal reset voltage or the signal voltage and the ramp signal, thereby reducing the striation noise introduced by the pixel power supply.
As shown in fig. 5, the present embodiment further provides a ramp signal generating unit to provide a pair of ramp signals according to the present embodiment. The pair of differential ramp signals is different from a common differential signal of one over one and one under, but one is a fixed level signal, and the other is a ramp level signal, and the undesirable factors are consistent in interference generated by the fixed level signal and the ramp level signal.
The ramp signal generating unit includes: a first input terminal Vin _ p, a second input terminal Vin _ n, a first output terminal Vout _ p, and a second output terminal Vout _ n. The first output terminal Vout _ p and the second output terminal Vout _ n are adapted to output the pair of differential ramp signals. Specifically, the first output terminal Vout _ p outputs a ramp level signal, and the second output terminal Vout _ n outputs a fixed level signal. The ramp signal generating unit performs common-film feedback only for a fixed-level signal of the pair of differential ramp signals.
The prior art generates a common differential signal from top to bottom, and usually performs common-film feedback after averaging positive and negative output signals of the differential output. In the embodiment, only the output fixed level signal is subjected to common film feedback to generate a fixed level signal and a ramp level signal, and the fixed level signal and the ramp level signal are interfered the same.
Fig. 6 shows the ramp level signal of the first input terminal Vin _ p and the superimposed noise, the fixed level signal of the second input terminal Vin _ n and the noise, and the difference between the input signals of the first input terminal Vin _ p and the second input terminal Vin _ n, and the difference between the output signals of the first input terminal Vin _ p and the second input terminal Vin _ n.
As can be seen from fig. 6, after the difference between the output signals of the first input terminal Vin _ p and the second input terminal Vin _ n is made, the resulting signal is a de-noised ramp signal.
The input signals of the first input terminal Vin _ p and the second input terminal Vin _ n are not limited, and may be clean single-ended ramp signals or differential ramp input signals. Sources of the superimposed noise include, but are not limited to, limited power supply rejection ratio, signal trace parasitics, and the like.
The ramp signal generating unit is implemented by a specific circuit, the generation of the differential ramp signal and the circuit timing and operation are not limited to those described above, and those skilled in the art can reasonably select the differential ramp signal according to the teaching of the above.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. An output circuit of a pixel array, the pixel array comprising M columns of pixel units, M ≧ 2, the output circuit comprising: the device comprises a control unit and N analog-to-digital conversion units, wherein N is more than or equal to 1;
one row of pixel units are correspondingly coupled with one analog-to-digital conversion unit, one analog-to-digital conversion unit is correspondingly coupled with K rows of pixel units, and K is more than or equal to 2;
the analog-to-digital conversion unit includes: a quantized signal input, a reference signal input, a first ramp signal input, and a second ramp signal input;
the quantized signal input terminal and the reference signal input terminal are connected to the control unit, and the first ramp signal input terminal and the second ramp signal input terminal are suitable for inputting a pair of differential ramp signals;
the analog-to-digital conversion unit carries out quantization processing on the basis of signals received by the quantized signal input end, the reference signal input end, the first ramp signal input end and the second ramp signal input end so as to output a quantization result;
the control unit is suitable for selecting two rows from a plurality of rows of pixel units coupled to the same analog-to-digital conversion unit, outputting the reset voltage or signal voltage provided by one pixel unit on one row to a quantization signal input end of the analog-to-digital conversion unit, and outputting the reset voltage provided by the other pixel unit on the other row to a reference signal input end of the analog-to-digital conversion unit.
2. The output circuit of the pixel array of claim 1, wherein the analog-to-digital conversion unit comprises: the circuit comprises a first transconductance comparator, a second transconductance comparator, an adder and a transimpedance amplifier;
the positive input end of the first transconductance comparator and the negative input end of the second transconductance comparator are respectively connected with the quantized signal input end and the reference signal input end;
the negative input end of the first transconductance comparator and the positive input end of the second transconductance comparator are respectively connected with the first ramp signal input end and the second ramp signal input end;
the output end of the first transconductance comparator and the output end of the second transconductance comparator are connected with the input end of the adder;
and the output end of the adder is connected with the input end of the transimpedance amplifier.
3. The output circuit of the pixel array of claim 1, further comprising: a ramp signal generating unit;
the ramp signal generating unit comprises a first input end, a second input end, a first output end and a second output end, and the first output end and the second output end are suitable for outputting the pair of differential ramp signals;
the ramp signal generation unit is adapted to perform common-film feedback for only one of the pair of differential ramp signals.
4. The output circuit of the pixel array according to claim 3, wherein one of the pair of differential ramp signals is a fixed level signal, and the other is a ramp level signal, and the ramp signal generating unit is adapted to perform common film feedback only for the fixed level signal.
5. The output circuit of the pixel array according to claim 1, wherein one of the pair of differential ramp signals is a fixed level signal and the other is a ramp level signal.
6. The output circuit of the pixel array of claim 5, wherein the analog-to-digital conversion unit comprises: the circuit comprises a first transconductance comparator, a second transconductance comparator, an adder and a transimpedance amplifier;
the positive input end of the first transconductance comparator is connected with the quantized signal input end, and the negative input end of the first transconductance comparator is suitable for inputting the ramp level signal;
the positive input end of the second transconductance comparator is suitable for inputting the fixed level signal, and the negative input end of the second transconductance comparator is connected with the reference signal input end;
the output end of the first transconductance comparator and the output end of the second transconductance comparator are connected with the input end of the adder;
and the output end of the adder is connected with the input end of the transimpedance amplifier.
7. The output circuit of the pixel array of claim 1, wherein the analog-to-digital conversion unit is a column ADC.
8. The output circuit of the pixel array of claim 1, wherein the control unit comprises: a signal generating unit and a plurality of multiplexers;
each multiplexer is provided with K input ends and an output end, and the K input ends are connected with K columns of pixel units in a one-to-one mode;
one analog-to-digital conversion unit is correspondingly connected with two multiplexers, one of the output ends of the two multiplexers is connected with the quantized signal input end of the analog-to-digital conversion unit, and the other one of the output ends of the two multiplexers is connected with the reference signal input end of the analog-to-digital conversion unit;
the signal generating unit is suitable for generating a control signal, and the multiplexer selects one of the voltages received by the K input ends to be output to the output end of the multiplexer based on the control signal.
9. An image sensor comprising an array of pixels and the output circuit of claims 1-8.
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