CN113364599A - Dual-state physical unclonable function circuit - Google Patents
Dual-state physical unclonable function circuit Download PDFInfo
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- CN113364599A CN113364599A CN202110658063.6A CN202110658063A CN113364599A CN 113364599 A CN113364599 A CN 113364599A CN 202110658063 A CN202110658063 A CN 202110658063A CN 113364599 A CN113364599 A CN 113364599A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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Abstract
The invention relates to the technical field of physical unclonable functions, in particular to a two-state physical unclonable function circuit, which comprises: the signal driving circuit converts the received serial excitation signal and serial configuration signal into parallel signals respectively; the system comprises a plurality of two-state physical unclonable function circuit units, a plurality of signal processing units and a plurality of signal processing units, wherein each unit acquires a response according to an excitation signal and a configuration signal; the time sequence control circuit ensures that the circuit works according to the designed time sequence; the parallel/serial converter circuit implements serial output of a multi-bit response. Wherein each two-state physically unclonable function circuit cell comprises: the state configuration circuit switches the working state of the circuit according to the configuration signal; the amplifier chain circuit amplifies the signals with process deviation; the response readout circuit selects a cell according to the excitation signal and outputs a response. The circuit is arranged to generate a key with high reliability.
Description
Technical Field
The invention relates to the technical field of physical unclonable circuits, in particular to a two-state physical unclonable function circuit.
Background
A Silicon-based physical unclonable function (Silicon-PUF) is used as a new hardware security primitive, can determine a 'stimulus-response' mapping relation depending on the process deviation of an integrated circuit, and inherits the randomness, the uncontrollable property and the uniqueness of the process deviation. Compared with the traditional cryptography scheme, the PUF has the characteristics of no storage of a secret key, generation after use, low overhead and the like, and is more suitable for scenes with limited equipment resources, such as the Internet of things, edge computing and the like. Existing PUFs can be classified into strong PUFs and weak PUFs according to the size of excitation-response pairs (CRPs) space. The strong PUFs have a large number of CRPs, and are widely applied to equipment authentication of the Internet of things. Although limited CRPs make weak PUFs unsuitable for authentication protocols that require a large number of exposed CRPs, it also makes them resistant to machine learning modeling attacks and is therefore widely used in key generation, device tagging, key preprocessing, etc. However, several typical PUFs, such as Static Random-Access Memory (SRAM) PUFs, oscillator PUFs, and glitch PUFs, which are susceptible to response inversion caused by environmental factors, need to be enhanced in reliability in practical applications.
Disclosure of Invention
The invention mainly aims to provide a two-state physical unclonable function circuit, aiming at solving the technical problem of generating a key with high reliability. The circuit can be configured to respond to a more stable state by the state configuration stage during the pre-selection phase.
In order to achieve the above object, the present invention provides a two-state physically unclonable function circuit, which includes a signal driving circuit, a plurality of two-state physically unclonable function circuit units, a timing control circuit, and a parallel/serial converter circuit.
Wherein, the first input end of the signal driving circuit is used for receiving an external serial excitation signal, the second input end of the signal driving circuit is used for receiving an external serial configuration signal, the third input end of the signal driving circuit is connected with the first output end of the time sequence control circuit, the first input end and the second input end of the binary physical unclonable function circuit unit are respectively connected with the first output end and the second output end of the signal driving circuit, the third input end of the binary physical unclonable function circuit unit is used for receiving an external pre-charge signal, the output end of the binary physical unclonable function circuit unit is connected with the output ends of other units at the same stage and the first input end of the parallel/serial converter circuit, and the first input end of the time sequence control circuit is used for receiving a clock signal, the second input end of the time sequence control circuit is used for receiving a control signal, and the second input end of the parallel/serial converter circuit is connected with the second output end of the time sequence control circuit; the signal driving circuit is used for converting the received serial excitation signal and the serial configuration signal into a parallel signal excitation signal and a parallel configuration signal respectively, and correspondingly inputting the parallel signal excitation signal and the parallel configuration signal into each two-state physical unclonable function circuit unit; the double-state physical unclonable function circuit unit is used for acquiring response according to the parallel excitation signal and the parallel configuration signal; the time sequence control circuit is used for ensuring that the circuit works according to the designed time sequence; the parallel/serial converter circuit is used for realizing serial output of the multi-bit parallel response signal.
Wherein, the said binary state physics unclonable function circuit unit includes: the circuit comprises a state configuration circuit, an amplifier chain circuit and a response reading circuit; the input end of the state configuration circuit is connected with the first output end of the signal driving circuit, the input end of the amplifier chain circuit is connected with the output end of the state configuration circuit, the first input end of the response reading circuit is used for receiving a pre-charging signal, the second input end of the response reading circuit is connected with the second output end of the signal driving circuit, and the third input end of the response reading circuit is connected with the output end of the amplifier chain circuit; the state configuration circuit is used for controlling a current path according to a configuration signal so as to switch the working state of the two-state physical unclonable function circuit, when the configuration signal meets an inverter type PUF condition, the two-state physical unclonable function circuit unit is in the inverter type PUF state, and when the configuration signal meets a leakage type PUF condition, the two-state physical unclonable function circuit unit is in the leakage type PUF state; the amplifier chain circuit amplifies the output signal of the state configuration circuit to obtain bit response; the response sensing circuit is initialized according to the precharge signal and outputs a response signal according to the excitation signal.
In order to achieve the above object, the state configuration circuit includes: the device comprises a phase inverter I1, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the input end of the phase inverter I1 is connected with the input end of a configuration signal, and the output end of the phase inverter is connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube; the source electrode of the first PMOS tube is connected with a power supply terminal, the drain electrode of the first PMOS tube is simultaneously connected with the source electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the configuration signal input end; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the first NMOS, the drain electrode of the third NMOS and the output end of the state configuration circuit, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube and the output end of the phase inverter 11; the source electrode of the third PMOS tube is connected with the power supply terminal, the drain electrode of the third PMOS tube is connected with the second PMOS drain electrode, the first NMOS drain electrode, the third PMOS drain electrode and the output end of the state configuration circuit, and the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube and the source electrode of the second PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the third PMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube and the CON; the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS and the grid electrode of the third NMOS, the source electrode of the second NMOS tube is connected with the grounding terminal, and the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube and the output end of the phase inverter I1; the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the output end of the state configuration circuit, meanwhile, the grid electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the third NMOS tube is connected with the grounding terminal.
The amplifier chain circuit comprises: the source electrode of the fourth PMOS tube is connected with the power supply terminal, the drain electrode of the fourth PMOS tube is simultaneously connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fourth NMOS tube and the output end of the state configuration circuit; the source electrode of the fourth NMOS tube is connected with the grounding terminal, the drain electrode of the fourth NMOS tube is simultaneously connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth PMOS tube and the output end of the state configuration circuit; the source electrode of the fifth PMOS tube is connected with the power supply terminal, the drain electrode of the fifth PMOS tube is simultaneously connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube; the source electrode of the fifth NMOS tube is connected with the grounding terminal, the drain electrode of the fifth NMOS tube is simultaneously connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube, and the grid electrode of the fifth NMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube; the source electrode of the sixth PMOS tube is connected with the power supply terminal, the drain electrode of the sixth PMOS tube is simultaneously connected with the drain electrode of the sixth NMOS tube and the output end of the amplifier chain circuit, and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube; and the source electrode of the sixth NMOS tube is connected with the grounding terminal, the drain electrode of the sixth NMOS tube is simultaneously connected with the drain electrode of the sixth PMOS tube and the output end of the amplifier chain circuit, and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube.
The response sensing circuit includes: the device comprises a seventh PMOS tube, a seventh NMOS tube and an eighth NMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a power supply terminal, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube and the output end of the response reading circuit, and the grid electrode of the seventh PMOS tube is connected with a pre-charging end; the source electrode of the seventh NMOS tube is connected with the grounding terminal, the drain electrode of the seventh NMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the seventh NMOS tube is connected with the output end of the state configuration circuit; and the source electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the seventh PMOS and the output end of the response reading circuit, and the grid electrode of the eighth NMOS tube is connected with the input end of the excitation signal.
Drawings
Fig. 1 is a schematic diagram of a circuit structure of an m-level x n-bit two-state physically unclonable function according to an embodiment of the present invention;
FIG. 2 is a state configuration circuit according to an embodiment of the present invention;
FIG. 3 is an amplifier chain circuit according to an embodiment of the present invention;
FIG. 4 is a response sensing circuit in an embodiment of the present invention;
FIG. 5 is a block diagram of a binary physical unclonable function circuit bit allocation strategy according to an embodiment of the present invention;
description of reference numerals:
1 a signal driving circuit;
2 a two-state physical unclonable function circuit unit;
3 a time sequence control circuit;
4 a parallel/serial converter circuit;
5 a state configuration circuit;
6 amplifier chain circuit;
7 responsive to the sensing circuit;
a first input terminal of the signal driving circuit A;
a second input end of the B signal driving circuit;
a CLK clock signal input;
a MODE control signal input terminal;
an OUT serial response output terminal;
the EN1 signal drives a circuit enable terminal;
EN2 parallel/serial converter circuit enable terminal;
CON parallel configuration signal input end
WL parallel excitation signal input
PRE precharge terminal
Vy0 state configuration circuit output terminal
Vy3 amplifier chain circuit output terminal
PB response read circuit output
I1 inverter
PM1～PM7 PMOS
NM1～NM8 NMOS
VDD Power supply terminal
GND grounding terminal
m two-state physical unclonable function circuit order
n binary physical unclonable function circuit output bit number
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and not limited to the embodiments set forth herein.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
As shown in fig. 1, the m-level x n-bit two-state physically unclonable function circuit includes: the circuit comprises a signal driving circuit 1, m × n two-state physical unclonable function circuit units 2, a time sequence control circuit 3 and a parallel/serial converter circuit 4.
The first input end A and the second input end B of the signal driving circuit are respectively used for receiving an external serial excitation signal and an external serial configuration signal, the third input end EN1 of the signal driving circuit is connected with the first output end of the time sequence control circuit, and the third input end of the signal driving circuit is used for receiving an enabling signal of the time sequence control circuit.
The first input terminal CON and the second input terminal WL of the two-state physically unclonable function circuit unit are respectively connected to the first output terminal and the second output terminal of the signal driving circuit, the third input terminal PRE of the two-state physically unclonable function circuit unit is used for receiving an external precharge signal, the output terminal PB of the two-state physically unclonable function circuit unit is connected to the output terminals of the m-1 other two-state physically unclonable function circuit units on the same stage and the first input terminal of the parallel/serial converter circuit, and the output terminal of the two-state physically unclonable function circuit unit is used for outputting a 1-bit parallel response signal.
The first input end CLK of the time sequence control circuit is used for receiving a working clock, and the second input end MODE of the time sequence control circuit is used for receiving a control signal.
The first input end of the parallel/serial converter circuit is connected with the output ends of the plurality of the binary physical unclonable function circuit units, the second input end of the parallel/serial converter circuit is connected with the second output end of the time sequence control circuit, the second input end EN2 of the signal driving circuit is used for receiving an enabling signal of the time sequence control circuit, and the output end OUT of the parallel/serial converter circuit is used for outputting an n-bit serial response signal.
As shown in fig. 1 to 4, the two-state physically unclonable function circuit unit includes: a state configuration circuit 5, an amplifier chain circuit 6, and a response sensing circuit 7.
The input end of the state configuration circuit CON is connected with the first output end of the signal driving circuit, and the input end of the state configuration circuit is used for receiving a parallel configuration signal; the input end of the amplifier chain circuit is connected with the output end Vy0 of the state configuration circuit; a first input PRE of said response sensing circuit is adapted to receive a PRE-charge signal, a second input WL of said response sensing circuit is coupled to a second output of said signal driving circuit, a second input of said response sensing circuit is adapted to receive a parallel stimulus signal, and a third input of said response sensing circuit is coupled to an output Vy3 of said amplifier chain circuit.
It should be noted that the two-state physically non-functional circuit has two operating states: an inverter type PUF state when the inverter type PUF condition is satisfied, and a leakage type PUF state when the leakage type PUF condition is satisfied. According to the configuration signal, the two-phase inverter type PUF state and the leakage type PUF state are switched.
As shown in fig. 5, each square represents a unit of the binary physically unclonable function circuit, and the upper number "1" or "0" represents that the unit is configured to be in an inverter type PUF state or a leakage type PUF state, respectively. In the pre-selection stage, the two-state physical unclonable function circuit units are all configured to be in a leakage type PUF state with lower power consumption, and if the 2 nd cell is unstable when the external environment changes, bit configuration strategy processing can be applied, and output stability is judged according to the reconfiguration. If the bit is configured to the inverter type PUF state to become output stable, the bit is configured to the inverter type PUF state output response when actually used, otherwise it is masked or discarded. The bit configuration strategy not only improves the reliability of the PUF, but also can greatly reduce the shielding or discarding bit number of the PUF unit and improve the utilization rate of the dual-state physical unclonable function circuit unit.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (5)
1. A two-state physically unclonable function circuit, comprising: the circuit comprises a signal driving circuit, a plurality of two-state physical unclonable function circuit units, a time sequence control circuit and a parallel/serial converter circuit; wherein, the first input end of the signal driving circuit is used for receiving an external serial excitation signal, the second input end of the signal driving circuit is used for receiving an external serial configuration signal, the third input end of the signal driving circuit is connected with the first output end of the time sequence control circuit, the first input end and the second input end of the binary physical unclonable function circuit unit are respectively connected with the first input end and the second input end of the signal driving circuit, the third input end of the binary physical unclonable function circuit unit is used for receiving an external pre-charge signal, the output end of the binary physical unclonable function circuit unit is connected with the output ends of other units at the same stage and the first input end of the parallel/serial converter circuit, and the first input end of the time sequence control circuit is used for receiving a clock signal, the second input end of the time sequence control circuit is used for receiving a control signal, and the second input end of the parallel/serial converter circuit is connected with the second output end of the time sequence control circuit; the signal driving circuit is used for converting the received serial excitation signal and the serial configuration signal into a parallel signal excitation signal and a parallel configuration signal respectively, and correspondingly inputting the parallel signal excitation signal and the parallel configuration signal into each two-state physical unclonable function circuit unit; the double-state physical unclonable function circuit unit is used for acquiring response according to the parallel excitation signal and the parallel configuration signal; the time sequence control circuit is used for ensuring that the circuit works according to the designed time sequence; the parallel/serial converter circuit is used for realizing serial output of the multi-bit parallel response signal.
2. A two-state physically unclonable function circuit as claimed in claim 1, wherein said two-state physically unclonable function circuit unit comprises: the circuit comprises a state configuration circuit, an amplifier chain circuit and a response reading circuit; the input end of the state configuration circuit is connected with the first output end of the signal driving circuit, the input end of the amplifier chain circuit is connected with the output end of the state configuration circuit, the first input end of the response reading circuit is used for receiving an external precharge signal, the second input end of the response reading circuit is connected with the second output end of the signal driving circuit, and the third input end of the response reading circuit is connected with the output end of the amplifier chain circuit; the state configuration circuit is used for controlling a current path according to a configuration signal so as to switch the working state of the two-state physical unclonable function circuit, when the configuration signal meets an inverter type PUF condition, the two-state physical unclonable function circuit unit is in the inverter type PUF state, when the configuration signal meets a leakage type PUF condition, the two-state physical unclonable function circuit unit is in the leakage type PUF state, and the state configuration circuit outputs a signal with process deviation; the amplifier chain circuit amplifies the output signal of the state configuration circuit; the response sensing circuit is initialized according to the precharge signal and outputs a response according to the excitation signal.
3. A two-state physically unclonable function circuit as claimed in claim 2, wherein said state configuration circuit comprises: the device comprises a phase inverter 11, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the input end of the phase inverter I1 is connected with the input end of a configuration signal, and the output end of the phase inverter is connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube; the source electrode of the first PMOS tube is connected with a power supply terminal, the drain electrode of the first PMOS tube is simultaneously connected with the source electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the configuration signal input end; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the first NMOS, the drain electrode of the third NMOS and the output end of the state configuration circuit, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube and the output end of the phase inverter I1; the source electrode of the third PMOS tube is connected with the power supply terminal, the drain electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the first NMOS, the drain electrode of the third PMOS tube and the output end of the state configuration circuit, and the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube and the source electrode of the second PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the third PMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube and the CON; the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS and the grid electrode of the third NMOS, the source electrode of the second NMOS tube is connected with the grounding terminal, and the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube and the output end of the phase inverter I1; and the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS, the drain electrode of the third PMOS, the drain electrode of the first NMOS and the output end of the state configuration circuit, meanwhile, the grid electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the third NMOS tube is connected with the grounding terminal.
4. A two-state physically unclonable function circuit as claimed in claim 2, wherein said amplifier chain circuit comprises: the source electrode of the fourth PMOS tube is connected with the power supply terminal, the drain electrode of the fourth PMOS tube is simultaneously connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fourth NMOS tube and the output end of the state configuration circuit; the source electrode of the fourth NMOS tube is connected with the grounding terminal, the drain electrode of the fourth NMOS tube is simultaneously connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth PMOS tube and the output end of the state configuration circuit; the source electrode of the fifth PMOS tube is connected with the power supply terminal, the drain electrode of the fifth PMOS tube is simultaneously connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube; the source electrode of the fifth NMOS tube is connected with the grounding terminal, the drain electrode of the fifth NMOS tube is simultaneously connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube, and the grid electrode of the fifth NMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube; the source electrode of the sixth PMOS tube is connected with the power supply terminal, the drain electrode of the sixth PMOS tube is simultaneously connected with the drain electrode of the sixth NMOS tube and the output end of the amplifier chain circuit, and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube; and the source electrode of the sixth NMOS tube is connected with the grounding terminal, the drain electrode of the sixth NMOS tube is simultaneously connected with the drain electrode of the sixth PMOS tube and the output end of the amplifier chain circuit, and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube.
5. A two-state physically unclonable function circuit as claimed in claim 2, wherein said response sensing circuit comprises: the device comprises a seventh PMOS tube, a seventh NMOS tube and an eighth NMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a power supply terminal, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube and the output end of the response reading circuit, and the grid electrode of the seventh PMOS tube is connected with a pre-charging end; the source electrode of the seventh NMOS tube is connected with the grounding terminal, the drain electrode of the seventh NMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the seventh NMOS tube is connected with the output end of the state configuration circuit; and the source electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the seventh PMOS and the output end of the response reading circuit, and the grid electrode of the eighth NMOS tube is connected with the input end of the excitation signal.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190165938A1 (en) * | 2017-11-14 | 2019-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for puf generation using variations in transistor threshold voltage and subthreshold leakage current |
| CN110580419A (en) * | 2018-06-08 | 2019-12-17 | 台湾积体电路制造股份有限公司 | Method and apparatus for accelerating leakage current based physically unclonable function generators under extreme operating conditions |
| US10714199B1 (en) * | 2018-05-09 | 2020-07-14 | Synopsys, Inc. | PUF latch for OTP memory arrays and method of operation |
| CN111490758A (en) * | 2020-04-15 | 2020-08-04 | 芯峰科技(广州)有限公司 | Reliability enhancing structure and enhancing method based on arbiter PUF |
-
2021
- 2021-06-15 CN CN202110658063.6A patent/CN113364599B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190165938A1 (en) * | 2017-11-14 | 2019-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for puf generation using variations in transistor threshold voltage and subthreshold leakage current |
| US10714199B1 (en) * | 2018-05-09 | 2020-07-14 | Synopsys, Inc. | PUF latch for OTP memory arrays and method of operation |
| CN110580419A (en) * | 2018-06-08 | 2019-12-17 | 台湾积体电路制造股份有限公司 | Method and apparatus for accelerating leakage current based physically unclonable function generators under extreme operating conditions |
| CN111490758A (en) * | 2020-04-15 | 2020-08-04 | 芯峰科技(广州)有限公司 | Reliability enhancing structure and enhancing method based on arbiter PUF |
Non-Patent Citations (2)
| Title |
|---|
| JILIANG ZHANG 等: "Physical Unclonable Function-Based Key Sharing via Machine Learning for IoT Security", 《IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS》 * |
| QIANG WU 等: "CT PUF: Configurable Tristate PUF against Machine Learning Attacks", 《2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)》 * |
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