CN113364599A - Dual-state physical unclonable function circuit - Google Patents

Dual-state physical unclonable function circuit Download PDF

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CN113364599A
CN113364599A CN202110658063.6A CN202110658063A CN113364599A CN 113364599 A CN113364599 A CN 113364599A CN 202110658063 A CN202110658063 A CN 202110658063A CN 113364599 A CN113364599 A CN 113364599A
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circuit
drain
gate
nmos
signal
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CN113364599B (en
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张吉良
陈卓俊
李文商
关振宇
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Hunan University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]

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Abstract

本发明涉及物理不可克隆函数技术领域，尤其涉及一种双态物理不可克隆函数电路，所述电路包括：信号驱动电路将接收的串行激励信号和串行配置信号分别转换为并行信号；若干个双态物理不可克隆函数电路单元，每个单元根据激励信号和配置信号获取响应；时序控制电路确保本电路按设计的时序工作；并行/串行转换器电路实现多比特响应的串行输出。其中每个双态物理不可克隆函数电路单元包括：状态配置电路根据配置信号切换本电路的工作状态；放大器链电路对带有工艺偏差的信号进行放大；响应读出电路根据激励信号选择单元并输出响应。通过设置本电路生成了高可靠性的密钥。

Figure 202110658063

The invention relates to the technical field of physical unclonable functions, in particular to a dual-state physical unclonable function circuit, the circuit comprising: a signal driving circuit converts a received serial excitation signal and a serial configuration signal into parallel signals respectively; Two-state physical unclonable function circuit unit, each unit obtains a response according to the excitation signal and the configuration signal; the timing control circuit ensures that the circuit works according to the designed timing; the parallel/serial converter circuit realizes the serial output of multi-bit responses. Each two-state physical unclonable function circuit unit includes: the state configuration circuit switches the working state of the circuit according to the configuration signal; the amplifier chain circuit amplifies the signal with process deviation; the response readout circuit selects the unit according to the excitation signal and outputs it response. A highly reliable key is generated by setting this circuit.

Figure 202110658063

Description

Dual-state physical unclonable function circuit
Technical Field
The invention relates to the technical field of physical unclonable circuits, in particular to a two-state physical unclonable function circuit.
Background
A Silicon-based physical unclonable function (Silicon-PUF) is used as a new hardware security primitive, can determine a 'stimulus-response' mapping relation depending on the process deviation of an integrated circuit, and inherits the randomness, the uncontrollable property and the uniqueness of the process deviation. Compared with the traditional cryptography scheme, the PUF has the characteristics of no storage of a secret key, generation after use, low overhead and the like, and is more suitable for scenes with limited equipment resources, such as the Internet of things, edge computing and the like. Existing PUFs can be classified into strong PUFs and weak PUFs according to the size of excitation-response pairs (CRPs) space. The strong PUFs have a large number of CRPs, and are widely applied to equipment authentication of the Internet of things. Although limited CRPs make weak PUFs unsuitable for authentication protocols that require a large number of exposed CRPs, it also makes them resistant to machine learning modeling attacks and is therefore widely used in key generation, device tagging, key preprocessing, etc. However, several typical PUFs, such as Static Random-Access Memory (SRAM) PUFs, oscillator PUFs, and glitch PUFs, which are susceptible to response inversion caused by environmental factors, need to be enhanced in reliability in practical applications.
Disclosure of Invention
The invention mainly aims to provide a two-state physical unclonable function circuit, aiming at solving the technical problem of generating a key with high reliability. The circuit can be configured to respond to a more stable state by the state configuration stage during the pre-selection phase.
In order to achieve the above object, the present invention provides a two-state physically unclonable function circuit, which includes a signal driving circuit, a plurality of two-state physically unclonable function circuit units, a timing control circuit, and a parallel/serial converter circuit.
Wherein, the first input end of the signal driving circuit is used for receiving an external serial excitation signal, the second input end of the signal driving circuit is used for receiving an external serial configuration signal, the third input end of the signal driving circuit is connected with the first output end of the time sequence control circuit, the first input end and the second input end of the binary physical unclonable function circuit unit are respectively connected with the first output end and the second output end of the signal driving circuit, the third input end of the binary physical unclonable function circuit unit is used for receiving an external pre-charge signal, the output end of the binary physical unclonable function circuit unit is connected with the output ends of other units at the same stage and the first input end of the parallel/serial converter circuit, and the first input end of the time sequence control circuit is used for receiving a clock signal, the second input end of the time sequence control circuit is used for receiving a control signal, and the second input end of the parallel/serial converter circuit is connected with the second output end of the time sequence control circuit; the signal driving circuit is used for converting the received serial excitation signal and the serial configuration signal into a parallel signal excitation signal and a parallel configuration signal respectively, and correspondingly inputting the parallel signal excitation signal and the parallel configuration signal into each two-state physical unclonable function circuit unit; the double-state physical unclonable function circuit unit is used for acquiring response according to the parallel excitation signal and the parallel configuration signal; the time sequence control circuit is used for ensuring that the circuit works according to the designed time sequence; the parallel/serial converter circuit is used for realizing serial output of the multi-bit parallel response signal.
Wherein, the said binary state physics unclonable function circuit unit includes: the circuit comprises a state configuration circuit, an amplifier chain circuit and a response reading circuit; the input end of the state configuration circuit is connected with the first output end of the signal driving circuit, the input end of the amplifier chain circuit is connected with the output end of the state configuration circuit, the first input end of the response reading circuit is used for receiving a pre-charging signal, the second input end of the response reading circuit is connected with the second output end of the signal driving circuit, and the third input end of the response reading circuit is connected with the output end of the amplifier chain circuit; the state configuration circuit is used for controlling a current path according to a configuration signal so as to switch the working state of the two-state physical unclonable function circuit, when the configuration signal meets an inverter type PUF condition, the two-state physical unclonable function circuit unit is in the inverter type PUF state, and when the configuration signal meets a leakage type PUF condition, the two-state physical unclonable function circuit unit is in the leakage type PUF state; the amplifier chain circuit amplifies the output signal of the state configuration circuit to obtain bit response; the response sensing circuit is initialized according to the precharge signal and outputs a response signal according to the excitation signal.
In order to achieve the above object, the state configuration circuit includes: the device comprises a phase inverter I1, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the input end of the phase inverter I1 is connected with the input end of a configuration signal, and the output end of the phase inverter is connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube; the source electrode of the first PMOS tube is connected with a power supply terminal, the drain electrode of the first PMOS tube is simultaneously connected with the source electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the configuration signal input end; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the first NMOS, the drain electrode of the third NMOS and the output end of the state configuration circuit, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube and the output end of the phase inverter 11; the source electrode of the third PMOS tube is connected with the power supply terminal, the drain electrode of the third PMOS tube is connected with the second PMOS drain electrode, the first NMOS drain electrode, the third PMOS drain electrode and the output end of the state configuration circuit, and the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube and the source electrode of the second PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the third PMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube and the CON; the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS and the grid electrode of the third NMOS, the source electrode of the second NMOS tube is connected with the grounding terminal, and the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube and the output end of the phase inverter I1; the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the first NMOS tube and the output end of the state configuration circuit, meanwhile, the grid electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the third NMOS tube is connected with the grounding terminal.
The amplifier chain circuit comprises: the source electrode of the fourth PMOS tube is connected with the power supply terminal, the drain electrode of the fourth PMOS tube is simultaneously connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fourth NMOS tube and the output end of the state configuration circuit; the source electrode of the fourth NMOS tube is connected with the grounding terminal, the drain electrode of the fourth NMOS tube is simultaneously connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fifth NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth PMOS tube and the output end of the state configuration circuit; the source electrode of the fifth PMOS tube is connected with the power supply terminal, the drain electrode of the fifth PMOS tube is simultaneously connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube; the source electrode of the fifth NMOS tube is connected with the grounding terminal, the drain electrode of the fifth NMOS tube is simultaneously connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube, and the grid electrode of the fifth NMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube; the source electrode of the sixth PMOS tube is connected with the power supply terminal, the drain electrode of the sixth PMOS tube is simultaneously connected with the drain electrode of the sixth NMOS tube and the output end of the amplifier chain circuit, and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube; and the source electrode of the sixth NMOS tube is connected with the grounding terminal, the drain electrode of the sixth NMOS tube is simultaneously connected with the drain electrode of the sixth PMOS tube and the output end of the amplifier chain circuit, and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube.
The response sensing circuit includes: the device comprises a seventh PMOS tube, a seventh NMOS tube and an eighth NMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a power supply terminal, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube and the output end of the response reading circuit, and the grid electrode of the seventh PMOS tube is connected with a pre-charging end; the source electrode of the seventh NMOS tube is connected with the grounding terminal, the drain electrode of the seventh NMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the seventh NMOS tube is connected with the output end of the state configuration circuit; and the source electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the seventh PMOS and the output end of the response reading circuit, and the grid electrode of the eighth NMOS tube is connected with the input end of the excitation signal.
Drawings
Fig. 1 is a schematic diagram of a circuit structure of an m-level x n-bit two-state physically unclonable function according to an embodiment of the present invention;
FIG. 2 is a state configuration circuit according to an embodiment of the present invention;
FIG. 3 is an amplifier chain circuit according to an embodiment of the present invention;
FIG. 4 is a response sensing circuit in an embodiment of the present invention;
FIG. 5 is a block diagram of a binary physical unclonable function circuit bit allocation strategy according to an embodiment of the present invention;
description of reference numerals:
1 a signal driving circuit;
2 a two-state physical unclonable function circuit unit;
3 a time sequence control circuit;
4 a parallel/serial converter circuit;
5 a state configuration circuit;
6 amplifier chain circuit;
7 responsive to the sensing circuit;
a first input terminal of the signal driving circuit A;
a second input end of the B signal driving circuit;
a CLK clock signal input;
a MODE control signal input terminal;
an OUT serial response output terminal;
the EN1 signal drives a circuit enable terminal;
EN2 parallel/serial converter circuit enable terminal;
CON parallel configuration signal input end
WL parallel excitation signal input
PRE precharge terminal
Vy0 state configuration circuit output terminal
Vy3 amplifier chain circuit output terminal
PB response read circuit output
I1 inverter
PM1～PM7 PMOS
NM1～NM8 NMOS
VDD Power supply terminal
GND grounding terminal
m two-state physical unclonable function circuit order
n binary physical unclonable function circuit output bit number
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and not limited to the embodiments set forth herein.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
As shown in fig. 1, the m-level x n-bit two-state physically unclonable function circuit includes: the circuit comprises a signal driving circuit 1, m × n two-state physical unclonable function circuit units 2, a time sequence control circuit 3 and a parallel/serial converter circuit 4.
The first input end A and the second input end B of the signal driving circuit are respectively used for receiving an external serial excitation signal and an external serial configuration signal, the third input end EN1 of the signal driving circuit is connected with the first output end of the time sequence control circuit, and the third input end of the signal driving circuit is used for receiving an enabling signal of the time sequence control circuit.
The first input terminal CON and the second input terminal WL of the two-state physically unclonable function circuit unit are respectively connected to the first output terminal and the second output terminal of the signal driving circuit, the third input terminal PRE of the two-state physically unclonable function circuit unit is used for receiving an external precharge signal, the output terminal PB of the two-state physically unclonable function circuit unit is connected to the output terminals of the m-1 other two-state physically unclonable function circuit units on the same stage and the first input terminal of the parallel/serial converter circuit, and the output terminal of the two-state physically unclonable function circuit unit is used for outputting a 1-bit parallel response signal.
The first input end CLK of the time sequence control circuit is used for receiving a working clock, and the second input end MODE of the time sequence control circuit is used for receiving a control signal.
The first input end of the parallel/serial converter circuit is connected with the output ends of the plurality of the binary physical unclonable function circuit units, the second input end of the parallel/serial converter circuit is connected with the second output end of the time sequence control circuit, the second input end EN2 of the signal driving circuit is used for receiving an enabling signal of the time sequence control circuit, and the output end OUT of the parallel/serial converter circuit is used for outputting an n-bit serial response signal.
As shown in fig. 1 to 4, the two-state physically unclonable function circuit unit includes: a state configuration circuit 5, an amplifier chain circuit 6, and a response sensing circuit 7.
The input end of the state configuration circuit CON is connected with the first output end of the signal driving circuit, and the input end of the state configuration circuit is used for receiving a parallel configuration signal; the input end of the amplifier chain circuit is connected with the output end Vy0 of the state configuration circuit; a first input PRE of said response sensing circuit is adapted to receive a PRE-charge signal, a second input WL of said response sensing circuit is coupled to a second output of said signal driving circuit, a second input of said response sensing circuit is adapted to receive a parallel stimulus signal, and a third input of said response sensing circuit is coupled to an output Vy3 of said amplifier chain circuit.
It should be noted that the two-state physically non-functional circuit has two operating states: an inverter type PUF state when the inverter type PUF condition is satisfied, and a leakage type PUF state when the leakage type PUF condition is satisfied. According to the configuration signal, the two-phase inverter type PUF state and the leakage type PUF state are switched.
As shown in fig. 5, each square represents a unit of the binary physically unclonable function circuit, and the upper number "1" or "0" represents that the unit is configured to be in an inverter type PUF state or a leakage type PUF state, respectively. In the pre-selection stage, the two-state physical unclonable function circuit units are all configured to be in a leakage type PUF state with lower power consumption, and if the 2 nd cell is unstable when the external environment changes, bit configuration strategy processing can be applied, and output stability is judged according to the reconfiguration. If the bit is configured to the inverter type PUF state to become output stable, the bit is configured to the inverter type PUF state output response when actually used, otherwise it is masked or discarded. The bit configuration strategy not only improves the reliability of the PUF, but also can greatly reduce the shielding or discarding bit number of the PUF unit and improve the utilization rate of the dual-state physical unclonable function circuit unit.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (5)

1.一种双态物理不可克隆函数电路，包括：信号驱动电路、若干个双态物理不可克隆函数电路单元、时序控制电路、并行/串行转换器电路；其中，所述的信号驱动电路第一输入端用于接收外部串行激励信号，所述的信号驱动电路第二输入端用于接收外部串行配置信号，所述的信号驱动电路第三输入端与所述的时序控制电路第一输出端相连，所述的双态物理不可克隆函数电路单元第一输入端、第二输入端分别与所述的信号驱动电路第一输入端、第二输入端相连，所述的双态物理不可克隆函数电路单元第三输入端用于接收外部预充电信号，所述的双态物理不可克隆函数电路单元输出端与其同一级的其他单元输出端、所述的并行/串行转换器电路第一输入端相连，所述的时序控制电路第一输入端用于接收时钟信号，所述的时序控制电路第二输入端用于接收控制信号，所述的并行/串行转换器电路第二输入端与所述的时序控制电路第二输出端相连；所述信号驱动电路，用于将接收的串行激励信号和串行配置信号分别转换为并行信号激励信号和并行配置信号，并将并行信号激励信号和并行配置信号对应地输入每个双态物理不可克隆函数电路单元；所述双态物理不可克隆函数电路单元，用于根据并行激励信号和并行配置信号获取响应；所述时序控制电路，用于确保本电路按设计的时序工作；所述并行/串行转换器电路，用于实现多比特并行响应信号的串行输出。1. A dual-state physical unclonable function circuit, comprising: a signal driving circuit, several dual-state physical unclonable function circuit units, a timing control circuit, and a parallel/serial converter circuit; An input terminal is used to receive an external serial excitation signal, the second input terminal of the signal driving circuit is used to receive an external serial configuration signal, and the third input terminal of the signal driving circuit is connected to the first input terminal of the timing control circuit. The output terminals are connected to each other, and the first input terminal and the second input terminal of the two-state physical non-clonable function circuit unit are respectively connected to the first input terminal and the second input terminal of the signal driving circuit. The third input terminal of the clone function circuit unit is used to receive an external precharge signal, the output terminal of the two-state physical unclonable function circuit unit is the output terminal of other units in the same stage, and the parallel/serial converter circuit first The input terminals are connected to each other, the first input terminal of the timing control circuit is used for receiving the clock signal, the second input terminal of the timing control circuit is used for receiving the control signal, and the second input terminal of the parallel/serial converter circuit is used for receiving the clock signal. connected with the second output end of the timing control circuit; the signal driving circuit is used to convert the received serial excitation signal and serial configuration signal into parallel signal excitation signal and parallel configuration signal respectively, and drive the parallel signal The signal and the parallel configuration signal are correspondingly input to each dual-state physical unclonable function circuit unit; the dual-state physical unclonable function circuit unit is used to obtain a response according to the parallel excitation signal and the parallel configuration signal; the time sequence control circuit uses To ensure that the circuit works according to the designed time sequence; the parallel/serial converter circuit is used to realize the serial output of multi-bit parallel response signals. 2.根据权利要求1所述的一种双态物理不可克隆函数电路，其特征在于，所述的双态物理不可克隆函数电路单元包括：状态配置电路、放大器链电路、响应读出电路；所述状态配置电路输入端与上述的信号驱动电路第一输出端相连，所述放大器链电路输入端与状态配置电路输出端相连，所述的响应读出电路第一输入端用于接收外部预充电信号，所述的响应读出电路第二输入端与上述的信号驱动电路信号第二输出端相连，所述的响应读出电路第三输入端与所述的放大器链电路输出端相连；所述的状态配置电路，用于根据配置信号控制电流路径，从而切换所述双态物理不可克隆函数电路的工作状态，当配置信号满足反相器型PUF条件时，双态物理不可克隆函数电路单元处于反相器型PUF状态，当配置信号满足漏电型PUF条件时，双态物理不可克隆函数电路单元处于漏电型PUF状态，所述的状态配置电路输出带工艺偏差的信号；所述的放大器链电路对状态配置电路输出信号进行放大；所述的响应读出电路根据预充电信号初始化，并根据激励信号输出响应。2. A dual-state physical unclonable function circuit according to claim 1, wherein the dual-state physical unclonable function circuit unit comprises: a state configuration circuit, an amplifier chain circuit, and a response readout circuit; The input end of the state configuration circuit is connected to the first output end of the above-mentioned signal driving circuit, the input end of the amplifier chain circuit is connected to the output end of the state configuration circuit, and the first input end of the response readout circuit is used for receiving external precharge The second input terminal of the response readout circuit is connected to the signal second output terminal of the above-mentioned signal drive circuit, and the third input terminal of the response readout circuit is connected to the output terminal of the amplifier chain circuit; the The state configuration circuit is used to control the current path according to the configuration signal, so as to switch the working state of the two-state physical unclonable function circuit. When the configuration signal satisfies the inverter-type PUF condition, the two-state physical unclonable function circuit unit is in Inverter-type PUF state, when the configuration signal satisfies the leakage-type PUF condition, the two-state physical unclonable function circuit unit is in the leakage-type PUF state, and the state configuration circuit outputs a signal with process deviation; the amplifier chain circuit The output signal of the state configuration circuit is amplified; the response readout circuit is initialized according to the precharge signal, and outputs the response according to the excitation signal. 3.根据权利要求2所述的一种双态物理不可克隆函数电路，其特征在于，所述的状态配置电路包括：反相器11，第一PMOS管，第二PMOS管，第三PMOS管，第一NMOS管，第二NMOS管，第三NMOS管，其中，所述反相器I1输入端与配置信号输入端相连，反相器输出端与第二PMOS管栅极、第二NMOS管栅极相连；所述第一PMOS管源极与电源端子相连，漏极同时与第二PMOS管源极、第三PMOS管栅极相连，其栅极与第一NMOS管栅极、配置信号输入端相连；所述第二PMOS管源极与第一PMOS管漏极相连，漏极与第三PMOS漏极、第一NMOS漏极、第三NMOS漏极、所述状态配置电路输出端相连，同时其栅极与第二NMOS管栅极、反相器I1输出端相连；所述第三PMOS管源极与电源端子相连，漏极与第二PMOS漏极、第一NMOS漏极、第三PMOS漏极、所述状态配置电路输出端相连，同时其栅极与第一PMOS管漏极、第二PMOS管源极相连；所述第一NMOS管漏极与第二PMOS漏极、第三NMOS漏极、第三PMOS漏极相连，源极与第二NMOS管漏极、第三NMOS栅极相连，同时其栅极与第一PMOS管栅极、CON相连；所述第二NMOS管漏极与第一NMOS源极、第三NMOS栅极相连，源极与接地端子相连，其栅极与第二PMOS管栅极、反相器I1输出端相连；所述第三NMOS管漏极与第二PMOS漏极、第三PMOS漏极、第一NMOS漏极、所述状态配置电路输出端相连，同时其栅极与第一NMOS管源极、第二NMOS管漏极相连，源极与接地端子相连。3. A dual-state physical unclonable function circuit according to claim 2, wherein the state configuration circuit comprises: an inverter 11, a first PMOS tube, a second PMOS tube, and a third PMOS tube , the first NMOS tube, the second NMOS tube, and the third NMOS tube, wherein the input end of the inverter I1 is connected to the input end of the configuration signal, and the output end of the inverter is connected to the gate of the second PMOS tube, the second NMOS tube The gate is connected to the gate; the source of the first PMOS tube is connected to the power supply terminal, and the drain is connected to the source of the second PMOS tube and the gate of the third PMOS tube at the same time, and the gate of the first NMOS tube is connected to the gate and the configuration signal input The source of the second PMOS tube is connected to the drain of the first PMOS tube, and the drain is connected to the drain of the third PMOS, the drain of the first NMOS, the drain of the third NMOS, and the output terminal of the state configuration circuit, At the same time, its gate is connected to the gate of the second NMOS tube and the output end of the inverter I1; the source of the third PMOS tube is connected to the power supply terminal, and the drain is connected to the second PMOS drain, the first NMOS drain, the third The PMOS drain is connected to the output end of the state configuration circuit, and the gate is connected to the first PMOS drain and the second PMOS source; the first NMOS drain is connected to the second PMOS drain, the third The NMOS drain and the third PMOS drain are connected, the source is connected to the second NMOS drain and the third NMOS gate, and the gate is connected to the first PMOS gate and CON; the second NMOS drain The electrode is connected to the first NMOS source and the third NMOS gate, the source is connected to the ground terminal, and its gate is connected to the second PMOS gate and the output end of the inverter I1; the drain of the third NMOS tube is connected to the The second PMOS drain, the third PMOS drain, the first NMOS drain, and the output terminal of the state configuration circuit are connected to each other, while the gate is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor, and the source is connected to the connected to the ground terminal. 4.根据权利要求2所述的一种双态物理不可克隆函数电路，其特征在于，所述的放大器链电路包括：第四PMOS管，第五PMOS管，第六PMOS管，第四NMOS管，第五NMOS管，第六NMOS管，其中，所述第四PMOS管源极与电源端子相连，漏极同时与第四NMOS管漏极、第五PMOS管栅极、第五NMOS管栅极相连，栅极与第四NMOS管栅极、上述的状态配置电路输出端相连；所述第四NMOS管源极与接地端子相连，漏极同时与第四PMOS管漏极、第五PMOS管栅极、第五NMOS管栅极相连，栅极与第四PMOS管栅极、上述的状态配置电路输出端相连；所述第五PMOS管源极与电源端子相连，漏极同时与第五NMOS管漏极、第六PMOS管栅极、第六NMOS管栅极相连，栅极与第五NMOS管栅极、第四PMOS漏极、第四NMOS漏极相连；所述第五NMOS管源极与接地端子相连，漏极同时与第五PMOS管漏极、第六PMOS管栅极、第六NMOS管栅极相连，栅极与第五PMOS管栅极、第四PMOS漏极、第四NMOS漏极相连；所述第六PMOS管源极与电源端子相连，漏极同时与第六NMOS管漏极、所述放大器链电路输出端相连，栅极与第六NMOS管栅极、第五PMOS漏极、第五NMOS漏极相连；所述第六NMOS管源极与接地端子相连，漏极同时与第六PMOS管漏极、所述放大器链电路输出端相连，栅极与第六PMOS管栅极、第五PMOS漏极、第五NMOS漏极相连。4. A dual-state physical unclonable function circuit according to claim 2, wherein the amplifier chain circuit comprises: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, and a fourth NMOS tube , the fifth NMOS tube, the sixth NMOS tube, wherein the source of the fourth PMOS tube is connected to the power supply terminal, and the drain is simultaneously connected to the drain of the fourth NMOS tube, the gate of the fifth PMOS tube, and the gate of the fifth NMOS tube The gate is connected to the gate of the fourth NMOS tube and the output terminal of the above state configuration circuit; the source of the fourth NMOS tube is connected to the ground terminal, and the drain is connected to the drain of the fourth PMOS tube and the gate of the fifth PMOS tube at the same time. The gate is connected to the gate of the fifth NMOS tube, and the gate is connected to the gate of the fourth PMOS tube and the output terminal of the above-mentioned state configuration circuit; the source of the fifth PMOS tube is connected to the power supply terminal, and the drain is connected to the fifth NMOS tube at the same time. The drain, the gate of the sixth PMOS tube, and the gate of the sixth NMOS tube are connected, and the gate is connected to the gate of the fifth NMOS tube, the drain of the fourth PMOS, and the drain of the fourth NMOS; the source of the fifth NMOS tube is connected to The ground terminal is connected to the ground terminal, and the drain is connected to the drain of the fifth PMOS tube, the gate of the sixth PMOS tube, and the gate of the sixth NMOS tube, and the gate is connected to the gate of the fifth PMOS tube, the drain of the fourth PMOS tube, and the drain of the fourth NMOS tube. The source of the sixth PMOS tube is connected to the power terminal, the drain is connected to the drain of the sixth NMOS tube and the output end of the amplifier chain circuit, and the gate is connected to the gate of the sixth NMOS tube and the drain of the fifth PMOS tube. The source of the sixth NMOS tube is connected to the ground terminal, the drain is connected to the drain of the sixth PMOS tube and the output end of the amplifier chain circuit at the same time, and the gate is connected to the gate of the sixth PMOS tube The pole, the fifth PMOS drain, and the fifth NMOS drain are connected. 5.根据权利要求2所述的一种双态物理不可克隆函数电路，其特征在于，所述的响应读出电路包括：第七PMOS管，第七NMOS管，第八NMOS管，其中，所述第七PMOS管源极与电源端子相连，漏极与第八NMOS管漏极、所述的响应读出电路输出端相连，栅极与预充电端相连；所述第七NMOS管源极与接地端子相连，漏极与第八NMOS管源极相连，栅极与上述的状态配置电路输出端相连；所述第八NMOS管源极与第七NMOS管漏极相连，漏极与第七PMOS漏极、所述的响应读出电路输出端相连，栅极与激励信号输入端相连。5. A dual-state physical unclonable function circuit according to claim 2, wherein the response readout circuit comprises: a seventh PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, wherein all the The source of the seventh PMOS tube is connected to the power supply terminal, the drain is connected to the drain of the eighth NMOS tube, the output terminal of the response readout circuit is connected, and the gate is connected to the precharge terminal; the source of the seventh NMOS tube is connected to the The ground terminal is connected to the ground terminal, the drain is connected to the source of the eighth NMOS transistor, and the gate is connected to the output terminal of the above state configuration circuit; the source of the eighth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain is connected to the seventh PMOS transistor The drain is connected to the output end of the response readout circuit, and the gate is connected to the input end of the excitation signal.
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