CN113363308A - Groove type VDMOS and groove type IGBT of P channel - Google Patents

Groove type VDMOS and groove type IGBT of P channel Download PDF

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Publication number
CN113363308A
CN113363308A CN202010147879.8A CN202010147879A CN113363308A CN 113363308 A CN113363308 A CN 113363308A CN 202010147879 A CN202010147879 A CN 202010147879A CN 113363308 A CN113363308 A CN 113363308A
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channel
island
type
islands
vdmos
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CN113363308B (en
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王学良
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GTA Semiconductor Co Ltd
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SHANGHAI ADVANCED SEMICONDUCTO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The invention discloses a groove type VDMOS and a groove type IGBT of a P channel, wherein the groove type VDMOS of the P channel comprises an n base area, at least one P island is embedded in a channel of the n base area, the P island is a P type area, and the P type area is formed by adopting P type semiconductor elements. According to the groove type VDMOS and the groove type IGBT with the P channel, the P island is buried in the channel of the n base area of the device, so that the Vth range of the device can be effectively adjusted, and the consistency is better. The number of p-islands depends on the specific application requirements, and the higher the number of p-islands buried, the higher the Vth value of the device.

Description

Groove type VDMOS and groove type IGBT of P channel
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a Trench-type (Trench) VDMOS (vertical double-diffused metal oxide semiconductor field effect Transistor) and a Trench-type IGBT (Insulated Gate Bipolar Transistor) of a P channel.
Background
Fig. 1 is a schematic cross-sectional view of a cell structure of a P-channel trench-type VDMOS in the prior art, which includes a polysilicon gate, a Source, and a Drain. In addition, the transistor also comprises a p region, a p drift region, gate oxides (gate oxide layers) formed along two sides and the bottom side of the polysilicon gate at the middle position above the p drift region, n bases (n base regions) symmetrically arranged on two sides of the gate oxides above the p drift region, a p + Source region arranged at the position where the upper layer of each n base is adjacent to the gate oxides, an n + body region arranged at the position where the upper layer of each n base is adjacent to the p + Source region, and an ILD (insulating layer) between the metal layer of Source and the polysilicon gate.
Fig. 2 is a schematic cross-sectional view of a cell structure of a P-channel trench IGBT in the prior art, which includes a polysilicon gate, a Cathode, and an Anode. In addition, the transistor also comprises an n region positioned above the metal layer of the Catode from bottom to top, a gate oxide formed along the two sides and the bottom side of the polysilicon gate at the middle position above the p drift, n bases symmetrically arranged on the p drift and positioned on the two sides of the gate oxide, a p + Anode region arranged at the upper layer of each n base and adjacent to the gate oxide, an n + body region arranged at the upper layer of each n base and adjacent to the p + Anode region, and an ILD positioned between the metal layer of the Anode and the polysilicon gate.
Vth (turn-on voltage) is an important parameter of VDMOS devices and IGBT devices, and when the gate-source voltage is greater than Vth, the hole concentration of the N-base surface under the gate is higher than the electron concentration, so that the N-type semiconductor inversion is P-type to form an inversion layer, and further a P-channel is formed. How to adjust the Vth of the device and its uniformity has been a concern in the industry.
In the prior art, Vth is regulated and controlled mainly from the concentration of n base and the thickness of gate oxide. From the concentration adjustment of n base, the adjustable range of Vth thereof is limited by LATCH UP (anti-LATCH-UP) capability; the adjustable range of Vth is limited by the gate oxide technology in the manner of adjusting from the gate oxide thickness. How to effectively adjust the controllable range and consistency of Vth of a trench type VDMOS and a trench type IGBT of a P channel is an urgent problem to be solved.
Disclosure of Invention
The invention aims to overcome the defects that the controllable range and consistency of Vth of a groove type VDMOS and a groove type IGBT for adjusting a P channel in the prior art are required to be improved, and provides the groove type VDMOS and the groove type IGBT for the P channel, which can effectively adjust the range of Vth of a device and have better consistency.
The invention solves the technical problems through the following technical scheme:
the invention provides a trench-type VDMOS (vertical double-diffused metal oxide semiconductor) with a P channel, which comprises an n base region, wherein at least one P island is embedded in the channel of the n base region, the P island is a P-type region, and the P-type region is formed by adopting a P-type semiconductor element.
In the scheme, the p island is embedded in the channel of the n base region, so that the Vth range of the device can be effectively adjusted, and the consistency is better. The p island can be formed by utilizing photolithography boards of different layers of the device when an appropriate layer is manufactured, that is, the specific manufacturing steps of the p island are not limited by the scheme, as long as the position of the finally generated p island is in the channel of the n base region. The number of P islands depends on the specific application requirements, and the larger the number of P islands buried, the higher the Vth value of the P-channel trench-type VDMOS. The Vth of the trench-type VDMOS with the P channel on the same wafer tends to be consistent on one side, and the Vth value of the trench-type VDMOS with the P channel added into the P island on the other side is more consistent with an expected value.
Preferably, the p-type semiconductor element includes at least one of boron, aluminum, gallium, indium, and thallium.
Preferably, a plurality of p islands are buried in the channel of the n base region, and the p islands are arranged at intervals.
In the scheme, the number of the p islands is multiple, and the p islands are arranged at intervals. Adjustment of the range and uniformity of values of the required Vth is achieved by adjusting the spacing between p islands, the dose of the elements, and the junction depth.
Preferably, each p island is formed by at least one of boron, aluminum, gallium, indium and thallium.
In the scheme, elements adopted by each p island can be the same or different.
The invention provides a P-channel trench IGBT, which comprises an n base region, wherein at least one P island is embedded in a channel of the n base region, the P island is a P-type region, and the P-type region is formed by adopting P-type semiconductor elements.
In the scheme, the p island is embedded in the channel of the n base region, so that the Vth range of the device can be effectively adjusted, and the consistency is better. The p island can be formed by utilizing photolithography boards of different layers of the device when an appropriate layer is manufactured, that is, the specific manufacturing steps of the p island are not limited by the scheme, as long as the position of the finally generated p island is in the channel of the n base region. The number of P islands depends on the specific application requirements, and the larger the number of P islands buried, the higher the Vth value of the P-channel trench IGBT. The Vth of the trench type IGBT with the P channel on the same wafer tends to be consistent on one side, and the Vth value of the trench type IGBT with the P channel added into the P island is more consistent with an expected value on the other side.
Preferably, the p-type semiconductor element includes at least one of boron, aluminum, gallium, indium, and thallium.
Preferably, a plurality of p islands are buried in the channel of the n base region, and the p islands are arranged at intervals.
In the scheme, the number of the p islands is multiple, and the p islands are arranged at intervals. Adjustment of the range and uniformity of values of the required Vth is achieved by adjusting the spacing between p islands, the dose of the elements, and the junction depth.
Preferably, each p island is formed by at least one of boron, aluminum, gallium, indium and thallium.
In the scheme, elements adopted by each p island can be the same or different.
The positive progress effects of the invention are as follows:
according to the groove type VDMOS and the groove type IGBT with the P channel, the P island is buried in the channel of the n base area of the device, so that the Vth range of the device can be effectively adjusted, and the consistency is better. The number of p-islands depends on the specific application requirements, and the higher the number of p-islands buried, the higher the Vth value of the device.
Drawings
Fig. 1 is a schematic cross-sectional view of a cell structure of a P-channel trench-type VDMOS in the prior art.
Fig. 2 is a schematic cross-sectional view of a cell structure of a P-channel trench IGBT in the prior art.
Fig. 3 is a schematic cross-sectional view of a cell structure of a P-channel trench VDMOS in embodiment 1 of the invention.
Fig. 4 is a schematic cross-sectional view of a cell structure of a P-channel trench IGBT according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
Fig. 3 is a schematic cross-sectional view of a cell structure of the P-channel trench VDMOS, which includes a polysilicon gate, a Source, and a Drain. In addition, the transistor also comprises a p region 1, a p drift, a gate oxide formed along two sides and the bottom side of the polysilicon gate at the middle position above the p drift, a p drift, n bases symmetrically arranged on two sides of the gate oxide above the p drift, a p + Source region 3 arranged at the upper layer of each n base adjacent to the gate oxide, an n + body region 2 arranged at the upper layer of each n base adjacent to the p + Source region 3, and an ILD between the metal layer of Source and the polysilicon gate. In this embodiment, at least one p island 4 is buried in the channel of the n base region, the p island 4 is a p-type region, and the p-type region is formed by using a p-type semiconductor element. Wherein the p-type semiconductor element includes at least one of boron, aluminum, gallium, indium, and thallium.
In this embodiment, a plurality of p islands 4 are buried in the channel of the n base region, and the p islands 4 are arranged at intervals. Each p island 4 is formed using at least one of boron, aluminum, gallium, indium, and thallium. Adjustment of the range and uniformity of values of Vth required is achieved by adjusting the spacing between p islands 4, the dose of the elements and the junction depth. In this embodiment, the elements used in each of the p islands 4 may be the same or different.
In this embodiment, the Vth range of the device can be effectively adjusted and the uniformity is better by burying the p island 4 in the channel of the n base region. The p island 4 may be formed by photolithography of different layers of the device when an appropriate layer is fabricated, that is, the present embodiment does not limit the specific fabrication steps of the p island 4, as long as the position of the finally-generated p island 4 is in the channel of the n base region. The number of P islands 4 depends on the specific application requirements, and the higher the number of P islands 4 buried, the higher the Vth value of the P-channel trench-type VDMOS. The Vth of the trench-type VDMOS having the P channel on the same wafer tends to be uniform on one hand, and the Vth of the trench-type VDMOS having the P channel added to the P island 4 on the other hand more conforms to an expected value.
Example 2
Fig. 4 is a schematic cross-sectional view of a cell structure of the P-channel trench IGBT, including a polysilicon gate, a Cathode, and an Anode. In addition, the transistor also comprises an n region 5, a p drift, a gate oxide formed along two sides and the bottom side of the polysilicon gate at the middle position above the p drift, an n base symmetrically arranged on two sides of the gate oxide above the p drift, a p + Anode region 7 arranged at the upper layer of each n base adjacent to the gate oxide, an n + body region 6 arranged at the upper layer of each n base adjacent to the p + Anode region 7, and an ILD between the metal layer of the Anode and the polysilicon gate. In this embodiment, at least one p island 8 is buried in the channel of the n base region, the p island 8 is a p-type region, and the p-type region is formed by using a p-type semiconductor element. Wherein the p-type semiconductor element includes at least one of boron, aluminum, gallium, indium, and thallium.
In this embodiment, a plurality of p islands 8 are buried in the channel of the n base region, and the p islands 8 are arranged at intervals. Each p island 8 is formed using at least one of boron, aluminum, gallium, indium, and thallium. Adjustment of the range and uniformity of values of Vth required is achieved by adjusting the spacing between p islands 8, the dose of the elements and the junction depth. In the present embodiment, the elements used in each of the p islands 8 may be the same or different.
In this embodiment, the Vth range of the device can be effectively adjusted and the uniformity is better by burying the p island 8 in the channel of the n base region. The p island 8 may be formed by photolithography of different layers of the device when an appropriate layer is fabricated, that is, the present embodiment does not limit the specific fabrication steps of the p island 8, as long as the position of the finally-generated p island 8 is in the channel of the n base region. The number of P-islands 8 depends on the specific application requirements, whereas the higher the number of P-islands 8 buried, the higher the Vth value of a P-channel trench IGBT. The Vth of the trench type IGBT having a P channel on the same wafer tends to be uniform on one hand, and the Vth of the trench type IGBT having a P channel added to the P island 8 on the other hand more conforms to an expected value.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (8)

1. The trench-type VDMOS with the P channel comprises an n base area, and is characterized in that at least one P island is embedded in the channel of the n base area, the P island is a P-type area, and the P-type area is formed by adopting a P-type semiconductor element.
2. The P-channel trench VDMOS of claim 1, wherein the P-type semiconductor element comprises at least one of boron, aluminum, gallium, indium, and thallium.
3. The P-channel trench VDMOS of claim 1, wherein a plurality of the P islands are buried in the channel of the n-base region, and the P islands are spaced apart from each other.
4. The P-channel trench VDMOS of claim 3, wherein each of the P-islands is formed using at least one of boron, aluminum, gallium, indium, and thallium.
5. The trench type IGBT with the P channel comprises an n base area and is characterized in that at least one P island is embedded in the channel of the n base area, the P island is a P-type area, and the P-type area is formed by adopting P-type semiconductor elements.
6. The P-channel trench IGBT according to claim 5, wherein the P-type semiconductor element comprises at least one of boron, aluminum, gallium, indium, and thallium.
7. The P-channel trench IGBT according to claim 5, wherein a plurality of the P islands are buried in the channel of the n base region and are arranged at intervals.
8. The P-channel trench IGBT according to claim 7, wherein each of the P islands is formed using at least one of boron, aluminum, gallium, indium, and thallium.
CN202010147879.8A 2020-03-05 2020-03-05 P-channel trench VDMOS and trench IGBT Active CN113363308B (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0452817A1 (en) * 1990-04-20 1991-10-23 Kabushiki Kaisha Toshiba Semiconductor device with MOS-transistors and method of manufacturing the same
JP2001094097A (en) * 1999-09-21 2001-04-06 Denso Corp Silicon carbide semiconductor device and fabrication method thereof
JP2003273354A (en) * 2002-03-18 2003-09-26 Fuji Electric Co Ltd Semiconductor device and method for manufacturing the same
US20040222457A1 (en) * 2003-05-07 2004-11-11 Ji-Young Kim Buried channel type transistor having a trench gate and method of manufacturing the same
US20090283823A1 (en) * 2007-08-10 2009-11-19 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN104885227A (en) * 2012-12-28 2015-09-02 三菱电机株式会社 Silicon-carbide semiconductor device and manufacturing method therefor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0452817A1 (en) * 1990-04-20 1991-10-23 Kabushiki Kaisha Toshiba Semiconductor device with MOS-transistors and method of manufacturing the same
JP2001094097A (en) * 1999-09-21 2001-04-06 Denso Corp Silicon carbide semiconductor device and fabrication method thereof
JP2003273354A (en) * 2002-03-18 2003-09-26 Fuji Electric Co Ltd Semiconductor device and method for manufacturing the same
US20040222457A1 (en) * 2003-05-07 2004-11-11 Ji-Young Kim Buried channel type transistor having a trench gate and method of manufacturing the same
US20090283823A1 (en) * 2007-08-10 2009-11-19 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN104885227A (en) * 2012-12-28 2015-09-02 三菱电机株式会社 Silicon-carbide semiconductor device and manufacturing method therefor

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