CN113360086A

CN113360086A - Storage device and method for operating storage device

Info

Publication number: CN113360086A
Application number: CN202110151188.XA
Authority: CN
Inventors: 理查德·N·德格林; 阿特雷·霍斯曼; 斯里尼瓦萨·拉朱·那达库迪提
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2020-03-05
Filing date: 2021-02-03
Publication date: 2021-09-07
Also published as: DE102021100236A1

Abstract

A storage device and a method of operating a storage device are disclosed. The storage device includes: a host interface for receiving host commands from a host device through a storage interface; one or more memory translation layers to perform one or more operations associated with the host command to retrieve one or more data blocks associated with the host command from the storage memory; bitmap circuitry comprising a bitmap for tracking a constrained order of one or more data blocks to be transferred to a host device; and a transfer trigger for triggering a data transfer of the one or more data blocks to the host device in a constrained order based on a state of one or more bits of the bitmap.

Description

Storage device and method for operating storage device

This application claims priority and benefit from united states provisional application No. 62/985,824 entitled "storage device for reducing idle time of a pipeline" filed on 3/5/2020 and united states application No. 16/896,050 filed on 8/6/2020, which are hereby incorporated by reference in their entirety.

Technical Field

Aspects of one or more example embodiments of the present disclosure relate to a storage device, and more particularly, to a storage device including a configurable data transfer trigger and a method of operating the same.

Background

A storage system generally includes a host device and a storage device. The host device may access data stored in the storage device by sending commands to the storage device. For example, a host device may send a read command to a storage device to access data stored in one or more logical blocks of the storage device. In this case, the read command may include stages such as a command issuing stage, a data transfer stage, and a response stage, for example. During the command issuing phase, the host device may issue a read command to the storage device, causing the storage device to retrieve (retrieve) data associated with the read command stored in a logical block of the storage device. The storage device may transmit data corresponding to the read command to the host device during a data transfer phase, and once all of the data has been transmitted to the host device, the storage device may send a response (indicating that all of the data has been successfully transmitted) to the host device during a response phase.

The above information disclosed in this background section is for enhancement of understanding of the background of the disclosure and, therefore, it may contain information that does not form the prior art.

Disclosure of Invention

One or more example embodiments of the present disclosure relate to a storage device including a configurable automatic data transfer trigger. The storage device may track out-of-order completions to automatically trigger in-order data transfers. In some embodiments, the data transfer flip-flops of the storage device may be dynamically configurable to reduce or minimize idle time on the data transfer bus.

According to one or more example embodiments of the present disclosure, a storage device includes: a host interface for receiving host commands from a host device through a storage interface; one or more memory translation layers to perform one or more operations associated with the host command to retrieve one or more data blocks associated with the host command from the storage memory; bitmap circuitry comprising a bitmap for tracking a constrained order of one or more data blocks to be transferred to a host device; and a transfer trigger for triggering a data transfer of the one or more data blocks to the host device in a constrained order based on a state of one or more bits of the bitmap.

In an example embodiment, the one or more data blocks may be retrieved from the storage memory in an order different from the constrained order.

In an example embodiment, consecutive bits from among the one or more bits of the bitmap may correspond to a constrained order.

In an example embodiment, the initial bit from among the consecutive bits may correspond to a first data block from among the one or more data blocks in a constrained order.

In an example embodiment, a next adjacent bit from among the consecutive bits may correspond to a second data block from among the one or more data blocks in a constrained order.

In one example embodiment, the transfer trigger may be configured to: triggering a data transfer in response to a specified number of bits from among the one or more bits of the bitmap, starting with an initial bit, having a state that changes from an initial state.

In one example embodiment, the one or more memory translation layers may be configured to: in response to executing a corresponding operation from among the one or more operations associated with the host command, setting a corresponding bit in the bitmap to have a changed state.

In one example embodiment, the one or more memory translation layers may be configured to: the specified number of bits are set to have changed states in an order different from the constrained order.

In one example embodiment, the bitmap circuit may be configured to dynamically change the specified number of bits according to a threshold.

In one example embodiment, the threshold may set the specified number of bits and the position of the initial bit from among the specified number of bits.

According to one or more example embodiments of the present disclosure, a method for triggering data transfer from a storage device to a host device includes: receiving, by the storage device, a host command from the host device to retrieve data from the storage memory; allocating, by the storage device, a bitmap for host commands; executing, by the storage device, one or more operations associated with the host command to retrieve one or more data blocks from the storage memory; in response to completion of execution of a corresponding operation from among the one or more operations, changing, by the storage device, a state of a corresponding bit from among one or more designated bits in the bitmap; monitoring the designated bit of the bitmap through a storage device; and in response to the designated bits of the bitmap having a state that changes from the initial state, triggering, by the storage device, a data transfer of the one or more data blocks in a constrained order.

In an example embodiment, the one or more operations associated with the host command may be performed to retrieve the one or more data blocks in an order different from the constrained order.

In an example embodiment, the one or more designated bits may correspond to one or more consecutive bits of a bitmap, and the one or more consecutive bits may correspond to a constrained order.

In one example embodiment, the data transfer may be triggered in response to a specified number of bits starting with the initial bit having a changed state.

In one example embodiment, the method may further include: the number of designated bits is changed by the storage device according to the threshold value.

According to one or more example embodiments of the present disclosure, a storage device includes: a storage controller to perform one or more operations associated with a host command received from a host device through a storage interface, the one or more operations to retrieve one or more data blocks associated with the host command from a storage memory; and bitmap circuitry for tracking one or more blocks of data in a constrained order to be transferred to the host device, the bitmap circuitry comprising: an assigned bitmap comprising one or more designated bits corresponding to a constrained order; a comparison bitmap circuit for generating a comparison bitmap according to a count value and a start position of one or more designated bits in a bitmap indicating allocation; and a trigger bitmap circuit for comparing the allocated bitmap with the comparison bitmap to determine the status of specified bits in the allocated bitmap, and for triggering data transfer of the one or more data blocks in a constrained order to the host device in accordance with the status of the specified bits. The trigger bitmap circuit is for triggering a data transfer in response to the designated bit having a state changed from an initial state.

In one example embodiment, the storage controller may be configured to: the state of the corresponding bit from among the designated bits is changed to the changed state in response to completion of the corresponding operation from among the one or more operations, and the one or more operations may be completed in an order different from the constrained order.

Drawings

The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the attached drawings.

Fig. 1 is a system diagram of a storage system according to one or more example embodiments of the present disclosure.

Fig. 2 is a block diagram of a storage device according to one or more example embodiments of the present disclosure.

Fig. 3 is a more detailed block diagram of a storage device according to one or more example embodiments of the present disclosure.

Fig. 4 is a block diagram of a transmit trigger circuit according to one or more example embodiments of the present disclosure.

Fig. 5 is a schematic circuit diagram illustrating a mask bitmap circuit according to one or more example embodiments of the present disclosure.

Fig. 6 is a schematic circuit diagram illustrating a comparison bitmap circuit according to one or more example embodiments of the present disclosure.

Fig. 7 is a schematic circuit diagram illustrating a trigger bitmap circuit according to one or more example embodiments of the present disclosure.

Fig. 8 is a flow diagram of a method for triggering data transfer in accordance with one or more example embodiments of the present disclosure.

Detailed Description

Example embodiments will hereinafter be described in more detail with reference to the accompanying drawings, wherein like reference numerals denote like elements throughout. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects and features of the disclosure to those skilled in the art. Thus, processes, elements, and techniques may not be described that are not necessary for a complete understanding of the aspects and features of the present disclosure by one of ordinary skill in the art. Unless otherwise indicated, like reference numerals refer to like elements throughout the drawings and written description, and thus, the description thereof may not be repeated.

The storage device may execute a single read command issued from the host device by performing one or more read operations to retrieve (retrieve) data corresponding to the read command stored in one or more logical blocks of the storage device. For example, depending on the size of the data corresponding to a single read command, the storage device may perform multiple read operations to retrieve a portion or block of data from the logical block. In this case, depending on the workload of the storage device, read operations may be completed out of order so that data portions or data blocks retrieved from the logical block may be received out of order. However, the storage device may send data associated with a single read command to the host device in an appropriate order (e.g., a predetermined order or a specific order (e.g., a constrained order)) (e.g., from a lowest Logical Block Address (LBA) to a highest LBA).

For example, the storage device may execute a read command using a host-to-device command frame, one or more device-to-host data frames, and a device-to-host response frame. A command frame for a read command may specify a starting LBA and LBA count, and one data frame may transfer up to, for example, 1024 bytes of data. In this case, if the read command requires multiple data frames to be transferred to the host device, the data frames may be transferred in a predetermined order (e.g., from the lowest LBA to the highest LBA). In addition, the storage device may perform multiple read operations to execute a single read command, such that each read operation fetches, for example, a portion or block of data (e.g., a page of data) associated with the single read command from a corresponding logical block. However, read operations may be completed out of order according to the workload of the storage device, such that data portions or data blocks are fetched out of order by the predetermined order in which the data is transferred to the host device. In this case, the storage device may convert the out-of-order completion of operations into an in-order delivery of data frames to send the data frames to the host device in a predetermined order.

Further, the storage device may transfer the ordered data frames to the host device over a connection established between the storage device and the host device such that the connection may be opened and closed as needed or desired. In this case, the connection may be switched by the circuit so that when the connection is broken, the connection may not be shared with other host devices and/or other storage devices. Since connection resources may be limited, efficient use of connections may be desirable to improve or maximize performance. Further, when one of the host device and the storage device determines that there are no more data frames to send, the connection may be downgraded from a full-duplex state (e.g., a bidirectional data transfer direction) to a half-duplex state (e.g., a unidirectional data transfer direction). In the half-duplex state, the connection may become idle, resulting in wasted bandwidth. Thus, it may be desirable to keep the connection as short as possible to reduce or minimize the half-duplex state, but not so short that the overhead of connection establishment becomes dominant.

According to one or more example embodiments of the present disclosure, a storage device may include a hardware module (e.g., a bitmap circuit) to track out-of-order operation completions to be converted into ordered data frame transfers. For example, in some embodiments, the hardware module may include an array of bitmaps, and each bitmap may correspond to a single host command (e.g., a single read command). In this case, each bit of the bitmap may correspond to one operation (e.g., one read operation) from among multiple operations (e.g., multiple read operations) that may be performed to execute a single host command (e.g., a single read command). In other words, each bit may correspond to a data portion or block (e.g., a page of data) that is retrieved as a result of completion of a corresponding operation (e.g., a corresponding read operation) from among multiple operations (e.g., multiple read operations) associated with a single host command (e.g., a single read command). When each of a data portion or a data block (e.g., a page of data) is received as a result of completion of a corresponding operation, the state of the corresponding bit in the bitmap may be changed from an initial state to a changed state (e.g., from 0 to 1). In this case, because the data portions or data blocks may be read out of order, the bits in the bitmap may change to changing states out of order. The transfer of data to the host device may be automatically triggered in response to a sufficient number of bits (e.g., consecutive bits) from among the bits of the corresponding bitmap, starting with an initial bit (e.g., the least significant bit), having a changed state, which may indicate that the data is ready to be transferred to the host device in an appropriate order. In one example, a bitmap may be used to track the retrieval of each block of data to be transferred to the host device. For example, a bitmap may be used to track whether the retrieval of each block of data to be transferred to the host device is complete, and if the retrieval of each block of data to be transferred to the host device is complete, the data transfer may be triggered.

According to one or more example embodiments of the present disclosure, a hardware module (e.g., a bitmap circuit) may have dynamically configurable data transfer triggers to improve or maximize bus utilization and/or bus efficiency. For example, in some embodiments, a sufficient number of consecutive bits for automatically triggering a data transfer may be dynamically configured according to a suitable or desired threshold, such that the burst size of the data transfer may be varied differently. In such a case, the threshold may minimize or reduce bus idle time, for example, by ensuring that an appropriate amount of data is ready to be sent before the connection is broken, for example, the threshold may be set to minimize or reduce connection establishment overhead, and/or by ensuring that data is ready to be transferred before the connection is broken, but not so much data is sent on a single connection, for example. For example, the threshold may be dynamically adjusted at start time, at run time, and/or on a per command basis as needed or desired based on performance, application, and/or implementation of the storage device and/or storage system, etc. Accordingly, idle time on the data transfer bus may be reduced, half-duplex status connections may be reduced, and performance may be improved.

In some embodiments, the storage device includes a hardware module (e.g., bitmap circuitry) for automatically triggering data transfers without using firmware or software. Managing data transfers using firmware or software may increase complexity, may be difficult to adjust, and/or may be difficult to maintain. On the other hand, a hardware module according to some embodiments of the present disclosure may automatically trigger data transfer according to the state of the bits of the corresponding bitmap, and the data transfer triggers may be dynamically configured as needed or desired. Furthermore, hardware modules may increase parallelism, while using firmware or software may be more serial processing. Thus, the hardware module (e.g., bitmap circuit) may improve performance and may increase flexibility of the storage device.

Briefly, a storage system 100 in accordance with one or more embodiments of the present disclosure may include a host device (e.g., a host computer) 102 and a storage device 104. The host device 102 may issue a command to the storage device 104 such that the storage device 104 retrieves data associated with the command stored in the storage device 104. For example, the host device 102 may be communicatively connected to the storage device 104 (e.g., via the storage interface 110) and may issue a read command to the storage device 104 such that data corresponding to the read command is retrieved (e.g., read) from the storage device 104 and sent to the host device 102. Once all of the data has been successfully sent to the host device 102, the storage device 104 may send an appropriate response (indicating that all of the data associated with the read command has been successfully sent) to the host device 102.

In one or more example embodiments, the storage device 104 may include a hardware module (e.g., BITMAP circuit (BITMAP circuit)118) for tracking out-of-order operation completions and automatically triggering in-order data frame transfers. For example, in some embodiments, the hardware module may include an array of bitmaps and auxiliary logic. Each bitmap may include n bits (where n is a natural number greater than 0) representing data to be transferred for a single read command. For example, each bit may represent a portion or block of data (e.g., a page of data) to be read from storage 102 (e.g., from storage memory 116). In other words, each bitmap may correspond to a mapping of bits for a single read command, where each bit represents a read status of one data portion or data block corresponding to the single read command. The hardware module may identify a bit number corresponding to an initial bit (e.g., the least significant bit) in a single burst of data to be transmitted and may set the size of the burst in bits. The hardware module may automatically trigger a data transfer to the host device 102 once an appropriate or desired number of consecutive bits (e.g., starting from the initial or least significant bits) from among the bits of the corresponding bitmap have a changed state from the initial state, which may indicate that data is ready to be transferred to the host device in the appropriate order.

In more detail, referring to fig. 1, the host device 102 may include a host processor 106 and a host memory 108. The host processor 106 may be a general purpose processor of the host device 102, such as a Central Processing Unit (CPU) core, for example. The host memory 108 may be considered a high-performance main memory (e.g., primary memory) of the host device 102. For example, in some embodiments, host memory 108 may include (or may be) volatile memory, such as Dynamic Random Access Memory (DRAM), for example. However, the present disclosure is not so limited, and the host memory 108 may include (or may be) any suitable high-performance primary memory (e.g., primary memory) replacement for the host device 102 as will be known to those of skill in the art. For example, in other embodiments, host memory 108 may be a relatively high performance non-volatile memory, such as NAND flash memory, Phase Change Memory (PCM), resistive RAM, spin transfer torque RAM (sttram), any suitable memory based on PCM technology, memristor technology, and/or resistive random access memory (ReRAM), and may include, for example, chalcogenide, and the like.

The storage device 104 may be considered a secondary memory that may permanently store data accessible by the host device 102. In this context, storage 104 may include (or may be) relatively slow memory when compared to the high performance memory of host memory 108. For example, in some embodiments, the storage device 104 may be a secondary memory of the host device 102, such as a Solid State Drive (SSD), for example. However, the present disclosure is not so limited, and in other embodiments, the storage device 104 may include (or may be) any suitable storage device, such as, for example, a magnetic storage device (e.g., a Hard Disk Drive (HDD), etc.), an optical storage device (e.g., a blu-ray disc drive, a Compact Disc (CD) drive, a Digital Versatile Disc (DVD) drive, etc.), and/or other kinds of flash memory devices (e.g., a USB flash drive, etc.), among others. In various embodiments, the storage device 104 may conform to a large form factor standard (e.g., a 3.5 inch hard drive form factor), a small form factor standard (e.g., a 2.5 inch hard drive form factor), an m.2 form factor, and/or an e1.s form factor, among others. In other embodiments, the storage device 104 may conform to any suitable or desired derivative (derivative) of these form factors. For convenience, the storage device 104 may be described below in the context of an SSD, but the disclosure is not so limited.

Storage device 104 may be communicatively coupled to host device 102 via storage interface 110. The storage interface 110 may facilitate communication between the host device 102 and the storage device 104 (e.g., using connectors and protocols). In some embodiments, the storage interface 110 may facilitate the exchange of storage requests and responses between the host device 102 and the storage device 104. In some embodiments, the storage interface 110 may facilitate data transfer to and from the host memory 108 of the host device 102 through the storage device 104. For example, in one embodiment, the storage interface 110 (e.g., connectors and protocols thereof) may include (or may conform to) Small Computer System Interface (SCSI) and/or serial attached SCSI (sas), and the like. However, the disclosure is not so limited, and in other embodiments, the storage interface 110 (e.g., the connectors and their protocols) may conform to other suitable storage interfaces, such as, for example, peripheral component interconnect express (PCIe), remote direct memory access over ethernet (RDMA), Serial Advanced Technology Attachment (SATA), fibre channel, non-volatile memory express (NVMe), and/or NVMe over fiber (NVMe-af), among others. In other embodiments, the storage interface 110 (e.g., connectors and protocols thereof) may include (or may conform to) various general-purpose interfaces, such as, for example, ethernet, Universal Serial Bus (USB), and the like. For convenience, the storage interface 110 may be described below in the context of a SAS interface, although the disclosure is not so limited.

In some embodiments, storage device 104 may include a host interface 112, a storage controller 114, and a storage memory 116. The host interface 112 may be connected to the storage interface 110 and may be responsive to input/output (I/O) requests received from the host device 102 through the storage interface 110. For example, the host interface 112 may receive a command (e.g., a read command) from the host device 102 through the storage interface 110 and may send the command to the storage controller 114 to retrieve data associated with the command from the storage memory 116. Storage controller 114 may provide an interface for controlling storage memory 116 and providing access to and from storage memory 116. For example, storage controller 114 may include at least one processing circuit embedded thereon for interfacing with storage memory 116. The processing circuitry may include, for example, digital circuitry (e.g., a microcontroller, microprocessor, digital signal processor, or logic device (e.g., a Field Programmable Gate Array (FPGA) and/or an Application Specific Integrated Circuit (ASIC), etc.) capable of executing data access instructions (e.g., via firmware and/or software)) to provide access to and from data stored in storage memory 116 in accordance with the data access instructions. For example, the data access instructions may include any suitable data storage and retrieval algorithm (e.g., read/write) instructions or the like. The storage memory 116 may permanently store data received from the host device 102 in a plurality of logical blocks. For example, in one embodiment, storage memory 116 may comprise non-volatile memory, such as NAND flash memory, for example. However, the present disclosure is not so limited, and storage memory 116 may include any suitable memory depending on the type of storage device 104 (e.g., magnetic, and/or optical disk, etc.).

Although the host interface 112 and the storage controller 114 are shown as separate components of the storage device 104, the disclosure is not so limited. For example, the host interface 112 and the storage controller 114 are shown as separate components to distinguish between a front end of the storage device 104 receiving commands from the host device 102 and a back end of the storage device 104 retrieving (e.g., reading) data associated with the commands from the storage memory 116. Thus, in various embodiments, the host interface 112 may be integrated with the storage controller 114 (e.g., as an Integrated Circuit (IC)), may be implemented separately from the storage controller 114 and attached to the storage device 104 (e.g., as a system on a chip (SOC), etc.).

In one or more example embodiments, the storage 104 may also include a bitmap circuit 118 and a transfer circuit 120. The bitmap circuitry 118 can track out-of-order operation completion and can automatically trigger transmission of ordered (e.g., constrained order) data frames. The transmit circuit 120 may receive a trigger (e.g., a trigger bit) from the bitmap circuit 118 to transmit data to the host device 102 in a predetermined order for corresponding commands. For example, in one embodiment, the bitmap circuitry 118 may comprise an array of bitmaps, and each bitmap may correspond to a single host command. Each bit in the bitmap corresponding to a single host command may represent a portion or block of data (e.g., a page of data) to be read from storage memory 116. For example, a data portion or data block may be the smallest unit of data (such as a page of data) that can be read from storage memory 116 by one read operation. For a non-limiting example, if a single read command requires 5 pages of data to be read from storage memory 116 (e.g., from a logical block of storage memory 116), then 5 bits (e.g., 5 consecutive bits) in the corresponding bitmap may correspond to the 5 pages of data to be read from storage memory 116. When each of the 5 pages of data are read from storage memory 116 in any order (e.g., when each corresponding read operation is completed in any order), the corresponding bit in the bitmap may be changed. Once each of the 5 bits is changed, bitmap circuit 118 may trigger the transfer of data corresponding to a single read command to transfer circuit 120.

In some embodiments, the bitmap circuit 118 may be implemented as a hardware module (e.g., electronic circuit) communicatively coupled to the host interface 112 and the storage controller 114. For example, in one embodiment, the bitmap circuit 118 may be implemented as an IC that is attached to the storage device 104 (or mounted on the storage device 104) (e.g., the bitmap circuit 118 may be embedded on the same board or the same circuit board as the storage device 104). For example, the bitmap circuit 118 may be implemented on the storage device 104 (e.g., may be attached to the storage device 104 or mounted on the storage device 104). However, the present disclosure is not so limited, for example, in another embodiment, the bitmap circuit 118 may be implemented on a circuit board separate from the circuit board of the storage device 104 (e.g., a printed circuit board PCB) and may be communicatively connected to the storage device 104.

Although the transmit circuit 120 is shown as a separate component of the storage device 104, the disclosure is not so limited. For example, the transmit circuitry 120 is shown as a separate component to distinguish the transmission of data from the triggering of the transmission. Thus, in various embodiments, for example, the transmit circuitry 120 may be implemented as part of the host interface 112 and/or as part of the bitmap circuitry 118.

In short, the host device 102 may send commands to the storage device 104 through the storage interface 110. The commands may include LBAs such that storage device 104 executes the commands according to the LBAs on data stored in storage memory 116 (e.g., in one or more logical blocks of storage memory 116). For example, the LBA may include a starting LBA and an LBA count. The storage device 104 may execute the command by performing a plurality of operations, and the operations may be completed in any order depending on the workload of the storage device 104. Once the appropriate number of operations are completed, the storage device 104 may transfer data to the host device 102 corresponding to the command in an appropriate order (e.g., a predetermined order or a particular order) (e.g., from the lowest LBA to the highest LBA).

In more detail, referring to fig. 2, the host interface 112 may receive commands from the host device 102 through the storage interface 110. For example, the command may be a read command, but the disclosure is not limited thereto. The host interface 112 may send a command to the storage controller 114 to perform one or more operations associated with the command, and may allocate a bitmap in the bitmap circuit 118 for the command. The storage controller 114 may perform one or more operations associated with the command in any order according to the workload and may change the state of each bit in the assigned bitmap as each operation is completed.

For example, the storage controller 114 may include one or more memory translation layers 202_1 and 202_2 (e.g., flash translation layers), which may be generally referred to as memory translation layers 202 (see fig. 3), each memory translation layer 202 may be connected to one or more NAND dies 204_1 and 204_2 of the storage memory 116. In this case, data associated with the command can be stored in any one or more of the NAND dies 204_1 and 204_2, such that any one or more of the memory translation layers 202 can perform the operation associated with the read command to fetch a portion or block of data (e.g., a page of data) from their respective NAND dies. Each memory translation layer 202 can include a queue for any number of operations for its respective one or more NAND dies, such that one or more operations associated with a command can be completed in any order according to the queue of the memory translation layer 202. Thus, one or more operations associated with a read command can be completed in any order such that a data portion or block associated with the command can be read from the NAND dies 204_1 and 204_2 in any order.

Bitmap circuitry 118 may track the state of bits in an assigned bitmap and may trigger an automatic data transfer in response to a sufficient number of bits (e.g., a sufficient number of consecutive bits) starting from an initial bit (e.g., the least significant bit) having a changed state. For example, the assigned bitmap may have a plurality of consecutive bits, and each bit may correspond to one operation from among a plurality of operations associated with the command. In this case, because operations may be completed out of order, the bits in the assigned bitmap may change out of order corresponding to out of order operation completions. Thus, consecutive bits may correspond to a predetermined order of portions or blocks of data to be sent to the host device 102, such that a sufficient number of consecutive bits starting with the initial bit having a changed state may indicate that the data is ready to be transferred to the host device in an appropriate order (e.g., in a predetermined order).

For a non-limiting example, when a read command requires 3 pages of data to be read from the NAND dies 204_1 and 204_2 to be sent to the host device 102 in a predetermined order from the first, second, and third pages, three consecutive bits may be specified in the allocated bitmap to correspond to the 3 pages of data. In this case, an initial bit (e.g., a least significant bit) from among three consecutive bits may correspond to the first page, a next bit from among three consecutive bits may correspond to the second page, and a last bit from among three consecutive bits may correspond to the third page, so that a predetermined order of 3-page data may be maintained according to the order of bits. Because 3 pages of data can be read from the NAND dies 204_1 and 204_2 in any order, the storage controller 114 can change the state of the 3 bits in the allocated bitmap in any order. However, because data may be sent to the host device 102 in a predetermined order, the transfer of data may not be triggered at least until the initial bit (or some configurable number of consecutive bits from the initial bit) has a changed state (indicating that the data of the corresponding page has been received).

In some embodiments, the bitmap circuit 118 may have a configurable data transfer trigger for controlling the burst size of data to be sent to the host device 102. For example, the bitmap circuit 118 may have a configurable threshold for setting the number of appropriate bits starting from the initial bit that may have changed state before triggering a data transfer. The threshold may be dynamically adjusted to improve the performance of the storage device 104. For example, the threshold may be dynamically adjusted to reduce connection setup overhead, reduce idle time on the data transfer bus, and/or reduce half-duplex status connections, etc. Thus, performance may be improved by dynamically adjusting the threshold values as needed or desired. The bitmap circuit 118 may track the status of each bit in the allocated bitmap for a single command, and once an appropriate number of bits from the initial bits in the allocated bitmap have changed status, the bitmap circuit 118 may trigger the transmit circuit 120 to transmit data to the host device in a predetermined order within a single burst.

Referring to fig. 3, in some embodiments, the host interface 112 may include a scheduling circuit 302. The host interface 112 may receive a host command from the host device 102 and the scheduling circuitry 302 may issue a request to the storage controller 114 to perform one or more operations associated with the host command. For example, when the host command is a read command, scheduling circuitry 302 may issue a read request to storage controller 114 to perform one or more read operations associated with the read command, such that each read operation retrieves a portion or block of data (e.g., a page of data) associated with the read command from storage memory 116.

In some embodiments, the scheduling circuitry 302 may identify the pages of data that may be read in order to perform a single read command, and may issue a read request to the storage controller 114 to fetch the pages of data in threshold size blocks corresponding to a single transfer burst from the storage memory 116 (e.g., from the NAND dies 204_1 and 204_ 2). For example, in some embodiments, scheduling circuitry 302 may generate a data structure (e.g., a Direct Memory Access (DMA) descriptor) DD for each page to be read, and may send a DD index corresponding to the data structure DD to storage controller 114 to read the data of the corresponding page from storage memory 116 (e.g., from NAND dies 204_1 and 204_ 2). In some embodiments, scheduling circuitry 302 may send multiple read requests (e.g., multiple DD indices) to storage controller 114 for threshold size blocks that satisfy a single transfer burst size such that a corresponding threshold number of pages are read from storage memory 116 at a time. For example, if the threshold is set to 8, such that 8 consecutive pages of data are transferred to the host device 102 at a time, the scheduling circuit 302 may generate a data structure DD for each of the 8 pages and may send a corresponding DD index for the 8 pages to the storage controller 114 to read the 8 pages of data from the storage memory 116.

In some embodiments, the scheduling circuitry 112 may issue a set of read requests to the storage controller 114 to read multiple pages of data before a previous data transfer is complete. For example, once a threshold size block of data associated with a read request is ready to be sent to the host device 102, the scheduling circuitry 302 may issue a next set of read requests to the storage controller 114 to read a next threshold size block of data from the storage memory 116. In this case, the next set of read requests may be for the same read command, or for a different command. For a non-limiting example, a single read command may require 15 read operations to fetch 15 pages of data from the storage memory 116, and the threshold may be set to 8, such that once the 8 consecutive bits of the allocated bitmap corresponding to the first 8 pages, starting from the initial bit, have changed state, the first 8 pages may be transferred to the host device 102 at once (e.g., during one open connection). In this case, when the current 8 pages are being transferred to the host device 102, the scheduling circuit 302 may issue the next 7 read requests in parallel to the storage controller 114 to fetch the next 7 pages to be transferred to the host device 102 during the next transfer burst. Thus, parallelism may be improved, which may result in better performance.

In some embodiments, for example, when more consecutive pages of data for a single host command are ready to be sent at the end of a single transfer burst, scheduling circuitry 302 may extend the single transfer burst to include more pages of data in the single transfer burst. Returning to our 15-page data example, in some embodiments, when data of the last page (e.g., page 8) is being transmitted to the host device 102 in a first transfer burst, if data of the first page (e.g., page 9) is ready to be transmitted within a second transfer burst, then the scheduling circuitry 302 may expand the first transfer burst to include data of the first page (e.g., page 9) of the second transfer burst. Thus, connection setup overhead may be reduced.

In some embodiments, scheduling circuitry 302 may allocate a bitmap in bitmap circuitry 118 for each host command, such that bitmap circuitry 118 may track the completion of out-of-order read operations for each host command. For example, in some embodiments, scheduling circuitry 302 may assign a bitmap to a single host command, and may set a relative starting position of data transfers (e.g., a position indicating an initial bit) in the bitmap and a count of the number of bits in the bitmap that may have changed state for triggering ordered (e.g., constrained order) data transfers for the single host command. For example, the count value may correspond to the number of read requests issued to the storage controller 114 within a single transfer burst, such that the count value determines the transfer burst size (e.g., data transfer threshold size) in bits. Thus, in some embodiments, the count value and relative starting position may be dynamically set to control the threshold size, which corresponds to the number of appropriate bits for triggering a data transfer that may have a changed state. In one embodiment, the corresponding bit in the corresponding bitmap may be initially set to an initial state that may be initialized, for example, at power-on.

Although the scheduling circuit 302 is shown as being part of the host interface 112, the disclosure is not so limited. For example, in various embodiments, the scheduling circuitry 302 may be implemented as separate circuitry (e.g., electronic circuitry) coupled to the host interface 112 and the storage controller 114, may be implemented as part of the host interface 112 and part of the storage controller 114, and so forth. In another embodiment, the scheduling circuit 302 may be implemented in firmware or software, for example, as part of the host interface 112 and/or as part of the storage controller 114.

In some embodiments, when the read request is completed by the storage controller 114 (e.g., by the memory translation layer 202), the storage controller 114 (or the corresponding memory translation layer 202) may change the corresponding bit in the bitmap to have a changed state (indicating that the data of the corresponding page has been read). For example, in some embodiments, the storage controller 114 (or corresponding memory translation layer 202) may provide the bitmap circuit 118 with a ready index (indicating that a page of data (e.g., a particular bit in the bitmap) corresponding to a particular data structure DD is now available). In some embodiments, portions or blocks of data (e.g., pages of data) read from storage memory 116 may be stored in a buffer, such that transfer circuit 120 may send the data from the buffer to host device 102. In this case, the storage controller 114 (or corresponding memory translation layer 202) may also send a buffer index (indicating the location of the page of data for data transfer) to the bitmap circuit 118.

Bitmap circuitry 118 may monitor designated bits (e.g., a threshold number of bits from the initial bits) in a bitmap currently in use (e.g., a bitmap currently assigned to a host command) and may detect a bitmap in which the designated bits have changed state. When the bitmap circuit 118 detects a bitmap in which designated bits have changed states, the bitmap circuit 118 may trigger the transmit circuit 120 to transmit corresponding data in a predetermined order, and may initialize the bits in the bitmap to their initial states for use by subsequent transmissions or subsequent commands. In one embodiment, if dispatch circuit 302 issues a set of read requests to storage controller 114 to read multiple pages of data before a previous data transfer is complete, storage controller 114 may change the bit state before a subsequent data transfer is specified so that data may already be available once the next data transfer is specified so that the next data transfer may be triggered immediately once the previous data transfer is complete.

For example, in some embodiments, bitmap circuitry 118 may include a count status register 304, a ready bitmap register 306, a buffer index register 308, and transfer trigger circuitry (or referred to as a transfer trigger or data transfer trigger) 310. In one embodiment, the count status register 304 may be set by the scheduling circuitry 302 to allocate a bitmap for host commands. In one embodiment, the count state register 304 may be a 2D array, where each row represents a data transfer index (TR index) corresponding to a single host command. For example, each row may include a count value corresponding to a threshold number of bits that may be set before triggering a corresponding data transfer for a single host command, and a relative start index of bits indicating a relative start position of the initial bits in the allocated bitmap.

In one embodiment, the ready bitmap register 306 may be set according to a ready index provided by the storage controller 114 (or corresponding memory translation layer 202) to change bits in the corresponding bitmap upon completion of the read operation. For example, in one embodiment, the ready bitmap register 306 may be a 2D array, where each row corresponds to a particular TR index (e.g., a particular host command). Each row may comprise a bitmap (e.g., a 64-bit bitmap) comprising a number of bits corresponding to a maximum number of read requests that may be generated by scheduling circuitry 302 within a single transmit burst. Whenever the storage controller 114 provides a ready index (e.g., by writing the ready index into a Special Function Register (SFR)), the bitmap circuit 118 may change the state of the corresponding bit in the corresponding bitmap (indicating that the corresponding data portion or block of data (e.g., a page of data) for that bit is ready to be sent) (e.g., according to the TR index).

In some embodiments, the buffer index register 308 may be set by the storage controller 114 (or corresponding memory translation layer 202) indicating the location of data ready to be sent. For example, when storage controller 114 reads a particular portion or block of data (e.g., a page of data) from storage memory 116, the read data may be stored in a buffer to be retrieved during a corresponding data transfer. Thus, in some embodiments, buffer index register 308 may include a buffer index to indicate the location of data to be transferred during a corresponding data transfer.

In some embodiments, the transfer trigger circuit 310 may determine whether an appropriate number of bits (e.g., consecutive bits) in the corresponding bitmap of the ready bitmap register 306 have changed status (indicating that the data corresponding to the bits is ready for transfer). For example, in some embodiments, the transfer trigger circuitry 310 may monitor specified bits (e.g., identified based on the relative starting position and count value) of a currently used bitmap (e.g., a bitmap currently assigned to a host command), and may detect a bitmap in which the specified bits (e.g., a threshold number of bits) have changed state. In response to detecting a bitmap having designated bits with changed status, transfer trigger circuitry 310 may automatically trigger the transfer of data corresponding to the bitmap. For example, in some embodiments, transfer trigger circuit 310 may set a trigger bit corresponding to the assigned bitmap to transfer circuit 120 (e.g., according to the TR index) to trigger a corresponding data transfer. The transfer trigger circuit 310 will be described in more detail below with reference to fig. 4 to 7.

The transmit circuitry 120 may transmit data for the corresponding host command to the host device 102 according to a trigger (e.g., a trigger bit) from the bitmap circuitry 118. For example, the transfer circuit 120 may include a transfer register 312, a context generator 314, and a buffer reset flip-flop 316. The transfer register 312 may be a SFR that includes a trigger bitmap for initiating a data transfer when a corresponding bit (e.g., trigger bit) in the trigger bitmap is set according to a corresponding TR index received from the transfer trigger circuit 310. The context generator may order the data corresponding to the bitmaps in a predetermined order to initiate transfer of the data to the host device 102 in the predetermined order. Upon successful transmission of the data, the buffer reset trigger 316 may release (e.g., may reset) the buffer for the transmitted data so that the buffer may be used for subsequent transmissions.

Fig. 4 is a block diagram of a transmit trigger circuit according to one or more example embodiments of the present disclosure. Fig. 5 is a schematic circuit diagram illustrating a mask bitmap circuit according to one or more example embodiments of the present disclosure. Fig. 6 is a schematic circuit diagram illustrating a comparison bitmap circuit according to one or more example embodiments of the present disclosure. Fig. 7 is a schematic circuit diagram illustrating a trigger bitmap circuit according to one or more example embodiments of the present disclosure.

Referring to fig. 4, the transfer trigger circuit 310 may include a mask bitmap circuit 402, a comparison bitmap circuit 404, and a trigger bitmap circuit 406. In short, the mask bitmap circuit 402 may toggle the count value and relative starting position in the count status register 304 for a particular host command (e.g., for a particular TR index) to generate a mask bitmap that represents the count value in bits relative to the relative starting position. The compare bitmap circuit 404 may generate a compare bitmap from the mask bitmap, which may be used to compare the count value to the designated bits with changed status in the corresponding bitmap of the ready bitmap register 306. The trigger bitmap circuit 406 may compare the comparison bitmap with a corresponding bitmap (e.g., a corresponding DD ready bitmap) to generate trigger bits for automatically triggering data transfers.

In more detail, referring to fig. 5, in some embodiments, the mask bitmap circuit 402 may generate the mask bitmap 502 from the count value and relative starting position (e.g., relative starting index) stored in a particular row of the count status register 304. For example, in FIG. 5, count state [0] through count state [255] may represent a row of count state register 304. In some embodiments, the mask bitmap 502 may be used to handle an end condition (wrap up condition). For example, in one embodiment, if the bitmap in the ready bitmap register 306 is a 64-bit bitmap, and the corresponding count value is 64 and the corresponding relative starting index is 63, the mask bitmap 502 may be a 128-bit bitmap (e.g., a bitmap including M [0] to M [127 ]). In this case, when the comparison bitmap is generated from the mask bitmap, the comparison bitmap may be generated as a 64-bit bitmap (e.g., a bitmap including C [0] to C [63 ]), such that the comparison bitmap may be compared with a corresponding 64-bit bitmap (e.g., a corresponding DD ready bitmap) in the ready bitmap register 306. In some embodiments, the comparison bitmap may be generated, for example, by masking a bitwise OR (OR) of the upper 64 bits and lower 64 bits of the bitmap followed by negation (e.g., inversion). For example, bit 63 in the mask bitmap 502 may be set to the initial bit (e.g., bit 0 or least significant bit) of a corresponding comparison bitmap having an appropriate number of consecutive bits from the initial bit corresponding to the other bits in the designated bit (e.g., a threshold number of bits).

In some embodiments, the mask bitmap circuit 402 may select one of the rows of the count state register 304 based on the TR index received from either of the scheduling circuit 302 and the storage controller 114. For example, because the scheduling circuit 302 and the storage controller 114 perform separate processes, the TR indices may be received from either of the scheduling circuit 302 and the storage controller 114 in any order. Scheduling circuitry 302 may provide the TR index, for example, when the bitmap is allocated for host commands as discussed above. For example, scheduling circuitry 302 may provide a TR index to assign a bitmap to a new host command, to set a threshold (e.g., a count value and/or relative starting position) for a next transfer of data associated with an existing host command, to allocate a bitmap for one or more read-ahead requests, and/or to extend a burst size for a data transfer corresponding to a particular host command, etc. For example, when the ready index is provided, the storage controller 114 may provide the TR index so that the corresponding bitmap in the ready bitmap register 306 may be compared to determine whether the appropriate number of bits in the corresponding bitmap have changed state.

For example, in some embodiments, mask bitmap circuit 402 may include a first Multiplexer (MUX)504, a Finite State Machine (FSM)506, a second MUX 508, a count left shift circuit 510, a subtractor circuit 512, and a start left shift circuit 514. The first MUX 504 may select one of a first TR index (e.g., the first TR index supplied by the scheduling circuit 302) or a second TR index (e.g., the second TR index supplied by the storage controller 114) as the selection signal for the second MUX 508. In some embodiments, first MUX 504 may select one of the first TR index and the second TR index according to an arbitration signal provided by FSM 506. For example, because the first TR index and the second TR index may be received in any order as discussed above, an arbitration signal may be provided to, for example, handle situations when the first TR index and the second TR index are received simultaneously or substantially simultaneously. In this case, the arbitration signal can be controlled according to the state of FSM 506. For example, in one embodiment, because the storage controller 114 may operate at SFR writes, the storage controller 114 may be given a higher priority than the scheduling circuit 302.

Still referring to FIG. 5, in some embodiments, the second MUX 508 may select a row from among the rows of the count state register 304 according to the first TR index or the second TR index. As discussed above, each row in the count status register 304 may include a count value and a relative starting position for a bit in the corresponding bitmap, which may be taken from the TR index. Count left shift circuit 510 may convert the number of count values into a bitmap. For example, count left shift circuit 510 may generate an array of bits having a value of 0 followed by a count number of 1 (e.g., 1< < count). Assuming, for a non-limiting example, that the count value is 5, count left shift circuit 510 may generate an array of bits having a value of "100000" (e.g., 1< <5 ═ 100000 ").

Subtractor circuit 512 may convert the output of count left shift circuit 510 to generate a number of bits corresponding to the count value having a bit value of 1. For example, subtractor circuit 512 may subtract a value of 1 (e.g., 1< < count value-1) from the output of count left shift circuit 510. Returning to a non-limiting example of a count value of 5, subtractor circuit 512 may subtract 1 from "100000" output from count left shift circuit 510, such that subtractor circuit generates a bitmap having a number of consecutive bits corresponding to the count value with bit value 1 (e.g., 100000-1 ═ 11111).

Start left shift circuit 514 may convert the output of the subtractor circuit according to the relative start position to generate mask bitmap 502. For example, the start left shift circuit 514 may left shift the output of the subtractor circuit 512 by an amount relative to the start position. Returning to a non-limiting example of a count value of 5, if the relative start position is 0, the start left shift circuit 514 may left shift the output of the subtractor circuit 512 (e.g., "11111") by the relative start position 0 (e.g., 11111< <0 ═ 11111).

Referring to fig. 6, in some embodiments, the comparison bitmap circuit 404 may generate a comparison bitmap 602 from the mask bitmap 502 for comparison with the allocated bitmap of the ready bitmap register 306. For example, in some embodiments, the comparison bitmap circuit 404 may include a plurality of logic gates (e.g., 604_1 through 604_64) and a plurality of inverters (e.g., 606_1 through 606_ 64). For example, in some embodiments, each of the plurality of logic gates may be an or gate for performing a 2-bit or operation between the high and low bits of the mask bitmap 502. In this case, for example, a first OR gate 604_1 may perform an OR operation between the first bit M [0] and the 65 th bit M [64] of the mask bitmap 502, a second OR gate 604_2 may perform an OR operation between the 2 nd bit M [1] and the 66 th bit M [65] of the mask bitmap 502, and so on, such that the 64 th OR gate 604_64 performs an OR operation between the 64 th bit M [63] and the 128 th bit M [127] of the mask bitmap 502. Thus, the OR gate may remove the end condition as discussed above. The output of each of the or gates may be inverted by a corresponding one of the inverters. Thus, the comparison bitmap 602 may be generated to have a full bit value of 1, in addition to those designated bits (designated bits may be generated to have a bit value of 0) corresponding to a portion or block of data (e.g., a page of data) to be read by the storage controller 114 (or corresponding memory translation layer 202).

Referring to fig. 7, in some embodiments, the trigger bitmap circuit 406 may compare the comparison bitmap 602 with the allocated bitmap of the ready bitmap register 306 to generate a trigger bit for triggering a data transfer. For example, as discussed above, each time the storage controller 114 (or corresponding memory translation layer 202) sends a ready index corresponding to a page of data read from the storage memory 116 (e.g., by writing the ready index into the SFR), the state of the corresponding bit in the allocated bitmap of the ready bitmap register 306 may be set to have a changed state. Trigger bitmap circuitry 406 may compare bits in the corresponding bitmap of ready bitmap register 306 with bits in comparison bitmap 602 to determine whether a specified bit of the allocated bitmap of ready bitmap register 306 corresponding to a portion or block of data (e.g., a page of data) to be read by storage controller 114 (or corresponding memory translation layer 202) has an altered state.

For example, in some embodiments, the trigger bitmap circuitry 406 may include bitwise OR circuitry 704, a reduction AND gate (reduction AND gate)706, AND a Demultiplexer (DMUX) 708. The bitwise or circuit 704 may perform a bitwise or operation between bits of the comparison bitmap 602 and bits of the allocated bitmap of the ready bitmap register 306. The reduction and gate 706 may perform an and operation on the outputs of the bitwise or circuit 704, and if each of the outputs of the bitwise or circuit 704 has a value of 1, the reduction and gate 706 may output a 1, which may indicate that all ready indices have been received, or if any of the outputs of the bitwise or circuit is a 0, the reduction and gate 706 may additionally output a 0. For example, because the comparison bitmap 602 may have a full bit value of 1 except for those designated bits (designated bits may have a value of 0) corresponding to portions or blocks of data (e.g., a page of data) to be read by the storage controller 114 (or corresponding memory translation layer 202), the bitwise or circuit 704 may output a full 1 (indicating that all ready indices have been received) if all designated bits in the allocated bitmap of the ready bitmap register 306 have changed state (e.g., a value of 1). On the other hand, if any specified bit in the allocated bitmap still has an initial state (e.g., bit value 0), the bit-wise or circuit 704 may output a 0 for those bit comparisons. Thus, reduction and gate 706 may output a 1 if all ready indices have been received (which sets the corresponding bit in ready bitmap register 306 to have a value of 1), or reduction and gate 706 may additionally output a 0 if at least one of the designated bits still has an initial state (e.g., indicating that the ready index for that bit has not been received).

DMUX 708 may assign the output from reduction AND gate 706 to a corresponding bit in trigger bitmap 702. The corresponding bit in the trigger bitmap 702 may be selected according to the TR index (e.g., the first TR index or the second TR index selected by the arbitration signal), and if the corresponding bit (e.g., according to a 1 output by the and gate 706) is set to 1, the corresponding bit in the trigger bitmap 702 (e.g., the bit identified based on the TR index) may be set to 1 to automatically trigger the transfer circuit 310 to initiate a data transfer for the corresponding host command in an ordered (e.g., constrained order). Accordingly, data transfers may be automatically initiated according to the state of a specified bit in the allocated bitmap of the ready bitmap register 306.

Fig. 8 is a flow diagram of a method for triggering data transfer in accordance with one or more example embodiments of the present disclosure. However, the present disclosure is not limited to the order or number of operations of the method 800 shown in fig. 8, and may be varied to any desired order or number of operations as recognized by one of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method may include fewer operations or additional operations. Further, the operations illustrated in method 800 may be performed by any suitable one or any suitable combination of the components of one or more of the example embodiments described above.

Referring to FIG. 8, a method 800 begins and at operation 805, a host command may be received from a host device to retrieve data from a storage memory. For example, in some embodiments, the host command may be a read command, although the disclosure is not so limited. The host command may be received by the storage device from the host device through the storage interface. For example, in some embodiments, the host interface 112 may receive host commands from the host device 102 through the storage interface 110.

In some embodiments, at operation 810, a bitmap may be assigned for host commands. For example, in some embodiments, the host interface 112 or the scheduling circuitry 302 may send one or more requests to the storage controller 114 to perform one or more operations to retrieve one or more portions or blocks of data (e.g., pages of data) associated with the host command from the storage memory 116 (e.g., from one or more logical blocks of the storage memory 116). In this case, the host interface 112 or the scheduling circuitry 302 may assign a bitmap (e.g., of the ready bitmap register 306) to the host command (e.g., according to the TR index), and may send one or more data structures (e.g., DMA descriptors) DD to the storage controller 114 to perform one or more operations according to the one or more data structures DD. In some embodiments, the host interface 112 or the scheduling circuitry 302 may provide a count value (e.g., a count value corresponding to the number of requests issued to the storage controller 114) and a relative starting index (corresponding to the initial bit) for the bits in the allocated bitmap, such that the designated bits in the allocated bitmap may be identified from the number of requests (or the number of data structures DD) issued to the storage controller.

In some embodiments, at operation 815, an operation from among the one or more operations may be performed to retrieve the data portion or data block from storage memory. For example, the storage controller 114 (or a corresponding one of the memory translation layers 202) may perform an operation from among the one or more operations according to a request (or data structure DD) from among the one or more requests. In some embodiments, the state of the corresponding bit (e.g., one of the designated bits) may be changed in the allocated bitmap at operation 820. For example, in some embodiments, when an operation from among the one or more operations completes, the storage controller (or a corresponding one of the memory translation layers 202) may change the state of a corresponding bit in the allocated bitmap (e.g., by issuing a corresponding ready index).

At operation 825, designated bits of the allocated bitmap may be monitored to determine whether the designated bits have changed state. For example, in some embodiments, the trigger bitmap circuit 406 may compare a corresponding comparison bitmap to a corresponding ready bitmap (e.g., an assigned bitmap) to determine whether all designated bits have changed status. If any of the specified bits do not have an altered state at operation 825 (e.g., if any of the specified bits still have an initial state) (e.g., no at operation 825), the method 800 may loop back to operation 815 to monitor the state of the specified bits upon completion of one or more operations. On the other hand, if all of the designated bits have changed state (e.g., yes at operation 825), an ordered data transfer may be triggered at operation 830 and data may be transferred to the host device at operation 835. For example, in some embodiments, data associated with host commands may be sent in a predetermined order (e.g., in a constrained order) regardless of the order in which the operations are completed. Once the data is transferred to the host device, the storage device may send a response indicating that the data has been successfully sent, and the method 800 may end.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated and/or simplified for clarity. It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" … … modify an entire list of elements when followed by a list of elements without modifying individual elements in the list.

As used herein, the terms "substantially," "about," and the like are used as approximate terms and not as degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of the present disclosure, the use of "may" refer to "one or more embodiments of the present disclosure. As used herein, the terms "using," using, "and" used "may be considered synonymous with the terms" utilizing, "" utilizing, "and" utilized.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Although a few example embodiments have been described, those skilled in the art will readily appreciate that various modifications are possible in example embodiments without departing from the spirit and scope of the disclosure. It will be understood that the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments, unless described otherwise. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed herein, and that various modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A storage device, the storage device comprising:

a host interface for receiving host commands from a host device through a storage interface;

one or more memory translation layers to perform one or more operations associated with the host command to retrieve one or more data blocks associated with the host command from the storage memory;

bitmap circuitry comprising a retrieved bitmap for tracking each of the one or more blocks of data to be transferred to the host device; and

a transfer trigger for triggering a data transfer of the one or more data blocks to the host device in a constrained order based on a state of one or more bits of the bitmap.

2. The storage device of claim 1, wherein the one or more data blocks are retrieved from the storage memory in an order different from the constrained order.

3. The storage device of claim 1, wherein consecutive bits from among the one or more bits of the bitmap correspond to a constrained order.

4. The storage device of claim 3, wherein an initial bit from among the sequential bits corresponds to a first data block from among the one or more data blocks in a constrained order.

5. The storage device of claim 4, wherein a next adjacent bit from among consecutive bits corresponds to a second data block from among the one or more data blocks in a constrained order.

6. The storage device of any one of claims 1 to 5, wherein the transfer trigger is configured to: triggering a data transfer in response to a specified number of bits from among the one or more bits of the bitmap, starting with an initial bit, having a state that changes from an initial state.

7. The storage device of claim 6, wherein the one or more memory translation layers are configured to: in response to executing a corresponding operation from among the one or more operations associated with the host command, setting a corresponding bit in the bitmap to have the changed state from the initial state.

8. The storage device of claim 7, wherein the one or more memory translation layers are configured to: setting the specified number of bits to have the changed state from the initial state in an order different from the constrained order.

9. The storage device of claim 6, wherein the bitmap circuit is configured to dynamically change the specified number according to a threshold.

10. The storage device of claim 9, wherein a threshold is used to set the specified number and a position of an initial bit from among the specified number of bits.

11. A method for triggering a data transfer from a storage device to a host device, the method comprising:

receiving a host command from a host device through a storage device to retrieve data from a storage memory;

allocating, by the storage device, a bitmap for host commands;

executing, by the storage device, one or more operations associated with the host command to retrieve one or more data blocks from the storage memory;

in response to completion of execution of a corresponding operation from among the one or more operations, changing, by the storage device, a state of a corresponding bit from among one or more designated bits in the bitmap;

monitoring, by a storage device, the one or more designated bits of a bitmap; and

triggering, by the storage device, a data transfer of the one or more data blocks in a constrained order in response to the one or more designated bits of the bitmap having a state that changes from the initial state.

12. The method of claim 11, wherein the one or more operations associated with a host command are performed to fetch the one or more data blocks in an order different from a constrained order.

13. The method of claim 11, wherein the one or more designated bits correspond to one or more contiguous bits of a bitmap and the one or more contiguous bits correspond to a constrained order.

14. The method of claim 13, wherein an initial bit from among the one or more consecutive bits corresponds to a first data block from among the one or more data blocks in a constrained order.

15. The method of claim 14, wherein a next adjacent bit from among the one or more consecutive bits corresponds to a second data block from among the one or more data blocks in a constrained order.

16. A method as claimed in any one of claims 11 to 15, wherein the data transfer is triggered in response to a specified number of bits starting with an initial bit having said state changed from the initial state.

17. The method of any of claims 11 to 15, further comprising:

changing, by the storage device, the number of the one or more designated bits in accordance with a threshold.

18. The method of claim 17, wherein a threshold is used to set the number of the one or more designated bits and the position of an initial bit from among the one or more designated bits.

19. A storage device, the storage device comprising:

a storage controller to perform one or more operations associated with a host command received from a host device through a storage interface, the one or more operations to retrieve one or more data blocks associated with the host command from a storage memory; and

bitmap circuitry for tracking retrieval of each of the one or more blocks of data to be transferred to the host device, the bitmap circuitry comprising:

an assigned bitmap comprising one or more designated bits corresponding to a constrained order;

a comparison bitmap circuit for generating a comparison bitmap according to a count value and a start position of the one or more designated bits in the bitmap indicating allocation; and

a trigger bitmap circuit for comparing the allocated bitmap with the comparison bitmap to determine the status of the one or more designated bits in the allocated bitmap, and for triggering a data transfer of the one or more data blocks in a constrained order to the host device in dependence on the status of the one or more designated bits,

wherein the trigger bitmap circuit is to trigger a data transfer in response to the one or more designated bits having a state changed from an initial state.

20. The storage device of claim 19, wherein the storage controller is configured to: in response to completion of a corresponding operation from among the one or more operations, changing a state of a corresponding bit from among the one or more specified bits to the changed state from the initial state, and

wherein the one or more operations are completed in an order different from the constrained order.