CN113348407A - Display panel and display device - Google Patents
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- CN113348407A CN113348407A CN201980079793.1A CN201980079793A CN113348407A CN 113348407 A CN113348407 A CN 113348407A CN 201980079793 A CN201980079793 A CN 201980079793A CN 113348407 A CN113348407 A CN 113348407A
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Abstract
A display panel (10) and a display device, the display panel (10) comprising: the pixel structure comprises a driving layer (20), pixel units (30) and a signal shielding layer (40), wherein the driving layer (20) is provided with an electrode wire assembly (50); the pixel unit (30) comprises a pixel electrode layer (31), wherein the pixel electrode layer (31) is laminated on the driving layer (20); the signal shielding layer (40) is laminated between the driving layer (20) and the pixel unit (30) and is used for shielding the interference of the signal flowing through the electrode wire assembly (50) to the pixel electrode layer (31). Therefore, the influence of the signal flowing through the electrode wire assembly (50) on the voltage or the current in the pixel electrode layer (31) can be reduced, so that the signal crosstalk phenomenon of the display panel (10) is improved, and the display effect of the display panel (10) is improved.
Description
The embodiment of the application relates to the technical field of display, in particular to a display panel and a display device.
The overlap capacitance between the metal wiring and the cathode in the existing display panel is large, and signal crosstalk is easy to occur. When the metal wiring is connected with a high-frequency signal, the voltage of the cathode is easily influenced and fluctuates, so that the display effect of the display panel is influenced.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can improve the display effect of the display panel.
The embodiment of the application solves the technical problem and provides the following technical scheme:
a display panel, comprising:
a driving layer provided with an electrode line assembly;
a pixel unit including a pixel electrode layer laminated on the driving layer;
and the signal shielding layer is stacked between the driving layer and the pixel unit and is used for shielding the interference of the signal flowing through the electrode wire assembly on the pixel electrode layer.
Optionally, a plane where the driving layer is located is a projection plane, and an orthogonal projection of the signal shielding layer on the projection plane at least partially covers the electrode wire assembly.
Optionally, the electrode wire assembly comprises:
the plurality of first electrode wires are sequentially arranged on the driving layer;
the plurality of second electrode wires are sequentially arranged on the driving layer;
wherein, the orthographic projection of the signal shielding layer on the projection plane at least covers a part of the plurality of first electrode wires and/or the plurality of second electrode wires.
Optionally, the signal shielding layer comprises:
the orthographic projection of the first signal shielding layer on the projection plane covers all the first electrode wires;
and the orthographic projection of the second signal shielding layer on the projection plane covers all the second electrode wires.
Optionally, the first signal shielding layer includes a plurality of first signal shielding portions, each of the first signal shielding portions covers a corresponding one of the first electrode lines in an orthogonal projection of the projection plane, and one end of each of the first signal shielding portions is connected to the same preset potential.
Optionally, the second signal shielding layer includes a plurality of second signal shielding portions, each of the second signal shielding portions covers a corresponding one of the second electrode lines in an orthogonal projection of the projection plane, and one end of each of the second signal shielding portions is connected to the same preset potential.
Optionally, any two first electrode lines in the plurality of first electrode lines are parallel to each other, any two second electrode lines in the plurality of second electrode lines are parallel to each other, and any one second electrode line in the plurality of second electrode lines intersects with any one first electrode line in the plurality of first electrode lines;
any one of the second signal shielding parts and any one of the first signal shielding parts have overlapping parts.
Optionally, one end of each first signal shielding part extends out of the display area of the display panel;
alternatively, the first and second electrodes may be,
one end of each second signal shielding part extends out of the display area of the display panel.
Optionally, the first electrode lines are data lines, and the second electrode lines are scan lines;
alternatively, the first and second electrodes may be,
the first electrode lines are scanning lines, and the second electrode lines are data lines.
Optionally, the signal shielding layer is connected to a preset potential.
Optionally, the preset potential is a ground potential.
Optionally, the pixel electrode layer is a cathode.
Optionally, the driving layer comprises:
a switch array layer provided with the electrode line assembly;
a passivation layer stacked on the switch array layer;
the substrate is stacked on the passivation layer and is far away from the switch array layer; and
and the pixel electrode layer is laminated on the pixel defining layer and is far away from the substrate.
Optionally, the substrate is patterned to form the signal shielding layer.
Optionally, the driving layer further includes a first insulating layer stacked between the switch array layer and the passivation layer, and the signal shielding layer is stacked between the first insulating layer and the passivation layer.
Optionally, the driving layer further includes a second insulating layer stacked between the substrate and the pixel defining layer, and the signal shielding layer is stacked between the second insulating layer and the pixel defining layer.
The embodiment of the application solves the technical problem and provides the following technical scheme:
a thin film transistor substrate comprises the thin film transistor.
The embodiment of the application solves the technical problem and provides the following technical scheme:
a display device comprising a display panel as described above.
Compared with the prior art, in the display panel provided by the embodiment of the application, the driving layer is provided with the electrode wire assembly, the pixel unit comprises the pixel electrode layer, the pixel electrode layer is stacked on the driving layer, the signal shielding layer is stacked between the driving layer and the pixel unit, and the signal shielding layer is used for shielding the interference of the signal flowing through the electrode wire assembly to the pixel electrode layer, so that the influence of the signal on the voltage or the current in the pixel electrode layer can be reduced, the signal crosstalk phenomenon of the display panel is improved, and the display effect of the display panel is improved.
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below. It is obvious that the drawings described below are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1a is a schematic cross-sectional view of a display panel provided in an embodiment of the present application;
fig. 1b is a schematic layout diagram of electrode line assemblies, a pixel electrode layer and a signal shielding layer in a display panel according to an embodiment of the present disclosure;
fig. 1c is a schematic diagram of the embodiment of the present application, in which a plane where the driving layer is located is a projection plane, and a signal shielding layer performs orthographic projection on the projection plane;
fig. 2 is a schematic layout diagram of electrode line assemblies, a pixel electrode layer and a signal shielding layer in a display panel according to another embodiment of the present disclosure;
fig. 3a is a schematic cross-sectional view of a display panel cut along the AA ″ direction at an overlapping portion of a signal shielding layer, a first routing layer, and a second routing layer according to an embodiment of the present disclosure;
fig. 3b is a schematic cross-sectional view of the display panel cut along the AA ″ direction at the overlapping portion of the signal shielding layer, the first routing layer and the second routing layer according to another embodiment of the present disclosure;
fig. 3c is a schematic cross-sectional view of the display panel cut along the AA ″ direction at the overlapping portion of the signal shielding layer, the first routing layer and the second routing layer according to still another embodiment of the present disclosure.
In order to facilitate an understanding of the present application, the present application is described in more detail below with reference to the accompanying drawings and specific embodiments. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. The terms "vertical", "horizontal", "left", "right", "inside", "outside" and the like used in the present specification are for illustrative purposes only and express only a substantial positional relationship, for example, with respect to "vertical", if a positional relationship is not strictly vertical for the purpose of achieving a certain object, but is substantially vertical, or utilizes the property of being vertical, it belongs to the category of "vertical" described in the present specification.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It is to be understood that, as shown herein, the positional relationship between one or more layers of the substance involved in the embodiments of the present application, such as the terms "stacked" or "formed" or "applied" or "disposed", is expressed using terms such as: any terms such as "stacked" or "formed" or "applied" may cover all manner, kinds and techniques of "stacked". For example, sputtering, plating, molding, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, Hybrid Physical-Chemical Vapor Deposition (HPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
The structural shape of the thin film transistor provided in the embodiments of the present application may be square, rectangular, circular, or diamond, etc., and it is understood that "circular" herein includes an approximate circular shape, and the structural shape of the thin film transistor provided by a person skilled in the art makes other substitutions or modifications according to the content described herein, and the thin film transistor having a certain structural shape should fall within the scope of the embodiments of the present application.
Referring to fig. 1a and fig. 1b together, a display panel 10 according to an embodiment of the present disclosure includes: a driving layer 20, a pixel unit 30 and a signal shielding layer 40.
Based on different driving technologies, or based on different structural designs or material selections of the pixel units, the display panel 10 provided in this embodiment may be a TFT screen (TFT Thin Film Transistor), a TFD screen (TFD Thin Film Diode), a UFB screen (Ultra Film Bright, UFB), an STN Screen (STN), an OLED screen (Organic Light-Emitting Diode, OLED), an AMOLED screen (Active Matrix/Organic Light-Emitting Diode, AMOLED Active Matrix Organic Light-Emitting Diode), and so on.
The display panel 10 includes a display area 11, and the display area 11 is used for displaying an image generated by the plurality of pixel units 30.
The driving layer 20 is used for driving the pixel units 30 to display images, wherein the driving layer 20 may adopt any suitable driving structure, for example, the driving layer 20 may adopt a thin film transistor array substrate composed of a bottom gate thin film transistor, a thin film transistor array substrate composed of a top gate thin film transistor, or even a thin film transistor array substrate composed of a double gate thin film transistor with a mixed bottom gate and a mixed top gate.
The driving layer 20 is provided with an electrode line assembly 50, and the electrode line assembly 50 is used to transmit a scan signal and/or a data signal, for example, when the electrode line assembly 50 is applied with the scan signal to gate a corresponding thin film transistor in the driving layer 20, the data signal may be output to a corresponding pixel unit 30. The layout of the electrode line assembly 50 in the driving layer 20 can be defined according to actual business requirements.
The pixel unit 30 is used for displaying an image, wherein the pixel unit 30 may be an LCD pixel unit or an OLED pixel unit, for example, when the pixel unit is an OLED pixel unit, the pixel unit 30 includes an anode, an organic functional layer, a cathode, a polarizer, a touch module, and the like. The organic functional layer may be composed of the following structural layers in sequence: a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer.
In the present embodiment, the pixel unit 30 includes a pixel electrode layer 31, and the pixel electrode layer 31 is stacked on the driving layer 20. The pixel electrode layer 31 serves as an electrode to which a voltage is applied, and when a positive voltage is applied to the pixel electrode layer 31, the pixel electrode layer 31 serves as an anode. When a negative voltage is applied to the pixel electrode layer 31, the pixel electrode layer 13 is a cathode.
The signal shielding layer 40 is stacked between the driving layer 20 and the pixel unit 30, and the signal shielding layer 40 is used for shielding a signal flowing through the electrode line assembly 50 from interfering with the pixel electrode layer 31, for example, the signal is a high-frequency signal or an enable signal, and the high-frequency signal or the enable signal greatly affects the stability and reliability of the voltage or the current in the pixel electrode layer 31 if the shielding effect of the signal shielding layer 40 is lacked. By the shielding effect of the signal shielding layer 40, the voltage or current in the pixel electrode layer 31 is relatively stable and reliable, so as to display a reliable and good image.
In some embodiments, the signal shielding layer 40 is made of a metal material or a metal oxide.
In general, the signal shielding layer 40 can shield the interference of the signal flowing through the electrode line assembly 50 to the pixel electrode layer, so as to reduce the influence of the high-frequency signal to the voltage or current in the pixel electrode layer 31, thereby improving the signal crosstalk phenomenon of the display panel 10, and further improving the display effect of the display panel 10.
Generally, no matter the pixel electrode layer 31 is used as an anode or a cathode, since an overlap capacitance is formed between the pixel electrode layer 31 and the pixel electrode layer 31, when a high frequency signal flows through the electrode line assembly 50, the high frequency signal affects the voltage or current stability of the pixel electrode layer 31.
In the present embodiment, referring to fig. 1c, in order to better achieve the shielding effect, the plane where the driving layer 20 is located is the projection plane 20a, and the orthogonal projection 20b of the signal shielding layer 40 on the projection plane covers the electrode wire assembly 50. When a high frequency signal flows through the electrode line assembly 50, since the signal shielding layer 40 is disposed directly above the electrode line assembly 50, that is, the signal shielding layer 40 is disposed directly between the electrode line assembly 50 and the pixel electrode layer 31, the signal shielding layer 40 can shield the high frequency signal from influencing the voltage or current in the pixel electrode layer 31.
It is noted that in fig. 1b or 1c, in order to intuitively embody that the orthographic projection of the signal shielding layer 40 on the projection plane can cover the electrode wire assembly 50, the width of the orthographic projection is larger than the width of the electrode wire assembly 50, it is understood that, in some embodiments, the shape or width of the orthographic projection may be better adapted to the shape or width of the electrode wire assembly 50.
It will be appreciated that in fig. 1c the orthographic projection of the signal shielding layer 40 in the projection plane is entirely covering the electrode wire assembly 50. In some embodiments, the orthographic projection of the signal shielding layer 40 on the projection plane may also partially cover the electrode wire assembly 50.
In some embodiments, the signal shielding layer 40 is connected to a predetermined potential, wherein the predetermined potential is any suitable constant potential, for example, the predetermined potential is a ground potential. Since the signal shielding layer 40 is connected to the same preset potential, it can be ensured that when the signal shielding layer 40 shields the high-frequency signal, the signal shielding layer 40 has a uniform reference potential, so as to avoid interference of local current or harmful magnetic field generated by the high-frequency signal, thereby reliably improving interference of the signal shielding layer 40 shielding the high-frequency signal to the pixel electrode layer 31.
Generally, the metal layer routing scheme of most display panels is as follows: according to the layout structure, the cathode is closest to the data line, the overlap capacitance between the cathode and the data line is relatively large, and high-frequency signals are relatively easy to couple with the voltage or current of the cathode, thereby causing signal crosstalk. When the pixel electrode layer 31 is a cathode, the signal shielding layer 40 can shield the display panel provided by the present embodiment to have a better display effect than most of the display panels in the prior art.
In some embodiments, referring to fig. 2, the electrode wire assembly 50 includes: a plurality of first electrode lines 501 and a plurality of second electrode lines 502.
The plurality of first electrode lines 501 are sequentially arranged on the driving layer 20, and the plurality of second electrode lines 502 are sequentially arranged on the driving layer 20, wherein when the first electrode lines 501 are data lines, the second electrode lines 502 are scanning lines. When the first electrode lines 501 are scan lines, the second electrode lines 502 are data lines.
In the present embodiment, the orthographic projection of the signal shielding layer 40 on the projection plane at least covers a portion of the plurality of first electrode lines 501 and/or the plurality of second electrode lines 502, that is, it is understood that the orthographic projection of the signal shielding layer 40 on the projection plane may cover one or more of the plurality of first electrode lines 501, may cover one or more of the plurality of second electrode lines 502, may cover one or more of the plurality of first electrode lines 501 and one or more of the plurality of second electrode lines 502, and may cover the entire number of first electrode lines 501 and/or the entire number of second electrode lines 502.
With this structure, it is assumed that the first electrode lines 501 are scan lines and the second electrode lines 502 are data lines, and on one hand, when the signal shielding layer 40 covers a portion of the plurality of first electrode lines 501 or the plurality of second electrode lines 502 in the front projection of the projection plane, it can shield high frequency signals from the data lines or the scan lines. On the other hand, when the signal shielding layer 40 covers a portion of the first electrode lines 501 and the second electrode lines 502 in the front projection of the projection plane, it can shield the high frequency signals from the data lines and the scan lines at the same time, thereby greatly improving the display effect of the display panel 10.
In some embodiments, with continued reference to fig. 2, the signal shielding layer 40 includes: a first signal shielding layer 41 and a second signal shielding layer 42.
The orthographic projection of the first signal shielding layer 41 on the projection plane covers all the first electrode lines 501, and the orthographic projection of the second signal shielding layer 42 on the projection plane covers all the second electrode lines 502.
Adopt layered shielding structure, it can set up first signal shielding layer 41 and second signal shielding layer 42 respectively following the structure of walking of first electrode line 501 and second electrode line 502 adaptively, consequently, it can better shield the interference of the high frequency signal that comes from all kinds, each electrode line to pixel electrode layer 31.
In some embodiments, referring to fig. 2, the first signal shielding layer 41 includes a plurality of first signal shielding portions 411, an orthogonal projection of each first signal shielding portion 411 on the projection plane covers a corresponding first electrode line 501, one end of each first signal shielding portion 411 extends out of the display area 11 of the display panel 10, and one end of each first signal shielding portion 411 is connected to the same preset potential.
The second signal shielding layer 42 includes a plurality of second signal shielding portions 421, an orthogonal projection of each second signal shielding portion 421 on the projection plane covers a corresponding second electrode line 502, one end of each second signal shielding portion 421 extends out of the display area 11 of the display panel 10, and one end of each second signal shielding portion 421 is connected to the same preset potential.
With such a shielding structure, each first electrode line 501 or second electrode line 502 corresponds to a respective signal shielding portion, so that interference of high-frequency signals from various electrode lines on the pixel electrode layer 31 can be better shielded.
In some embodiments, the first electrode lines 501 and the second electrode lines 502 are routed in a "well" shape, that is, any two first electrode lines 501 of the plurality of first electrode lines 501 are parallel to each other, any two second electrode lines 502 of the plurality of second electrode lines 502 are parallel to each other, any one second electrode line 502 of the plurality of second electrode lines 502 intersects with any one first electrode line 501 of the plurality of first electrode lines 501, for example, the second electrode lines 502 are perpendicular to the first electrode lines 501.
When the layout of the signal shielding portions is performed based on the routing structures of the first electrode lines 501 and the second electrode lines 502, the overlapping portion 43 exists between any one of the second signal shielding portions 421 and any one of the first signal shielding portions 411, that is, the first signal shielding portions 411 and the second signal shielding portions 421 may be masked on the same layer structure, so that the overlapping portion 43 exists between any one of the second signal shielding portions 421 and any one of the first signal shielding portions 411.
With such a shielding structure, on one hand, when high-frequency signals of the first electrode line 501 and the second electrode line 502 need to be shielded, the design difficulty and layout difficulty increased by the need of constructing the first signal shielding part 411 and the second signal shielding part 421 of different levels are avoided. On the other hand, since the first signal shielding part 411 and the second signal shielding part 421 are designed at the same layer at the same time, it is possible to reduce material costs.
The display panel provided in the embodiments of the present application will be described in detail below with reference to the deformed structure of the driving layer and the position relationship between the signal shielding layers, and it should be understood that the description or the drawings are not intended to limit the scope of the embodiments of the present application.
Referring to fig. 3a, the driving layer 20 includes: a switch array layer 21, a passivation layer 22, a substrate 23, and a pixel defining layer 24.
The switch array layer 21 is used for receiving a scan signal or a data signal to drive the pixel unit 30 to display an image. For example, in some embodiments, please continue to refer to fig. 3a, the switch array layer 21 includes a thin film transistor substrate 211, a first routing layer 212, an interlayer dielectric layer 213, and a second routing layer 214, which are sequentially stacked, wherein the first routing layer 212 has a first electrode line 501, the second routing layer 214 has a second electrode line 502, the first electrode line 501 can be used as a scan line, and the second electrode line 502 can be used as a data line.
The thin film transistor substrate 211 may use a flexible substrate such as a material including thin glass, a metal foil, or a plastic base having a flexible structure including a resin such as Polyimide (PI), Polycarbonate (PC), polyethylene glycol terephthalate (PET), Polyethersulfone (PES), polyethylene film (PEN), Fiber Reinforced Plastic (FRP), or the like coated on both sides of a base film, for example, or a rigid substrate. The rigid substrate may be, but is not limited to, a glass substrate, a metal substrate, or a ceramic substrate.
The interlayer dielectric layer 213 can protect the thin film transistor from moving particles or other undesired impurity charges, can attract impurity charges from the electrode terminal, and can prevent the thin film transistor from being affected by the impurity charges and the like.
A passivation layer 22 is stacked on the switching array layer 21, and the passivation layer 22 contributes to improvement of electrical characteristics of the thin film transistor. The passivation layer 22 may be a silicon nitride insulating layer having excellent photoelectric properties, mechanical properties, and strong resistance to diffusion of impurity particles and water vapor permeation. The thinner silicon nitride insulating layer is not easy to block the diffusion phenomenon, and the concentration of the contaminant at the interface of the active layer is reduced with the increase of the thickness of the passivation layer 22, but when the thickness exceeds a critical value, the concentration of the contaminant will not be greatly reduced to reach a minimum value, and thus the thickness of the passivation layer 22 is set to be 100-400 nm. In some embodiments, the passivation layer 22 may also adopt a single-layer silicon dioxide (SiO2) or a double-layer silicon dioxide/silicon nitride (SiO2/SiNx) structure or an organic film layer structure.
The substrate 23 is stacked on the passivation layer 22 and away from the switch array layer 21, the substrate 23 is a transparent glass substrate, and the substrate 23 includes Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Indium Tin Zinc Oxide (ITZO), and the like.
The pixel defining layer 24 is stacked on the substrate 23 away from the passivation layer 22, and the pixel electrode layer 31 is stacked on the pixel defining layer 24 away from the substrate 23. The pixel defining layer 24 defines the location of the pixel cells 30, wherein the shape of the pixel defining layer 24 may be any suitable shape, such as trapezoidal, inverted trapezoidal, rectangular, square, and so forth.
In some embodiments, the signal shielding layer 40 is masked within the substrate 23, i.e., the substrate 23 is patterned to form the signal shielding layer 40 described above. The user can create a new pattern of the signal shielding layer 40 on the substrate 23, avoiding the original substrate pattern. Alternatively, the user may also re-create a reticle that re-lays out the substrate pattern and the pattern of the signal shielding layer 40. In the present embodiment, the signal shielding layers 40 are connected in series and to the ground potential.
Designing the signal shielding layer 40 in this manner can reduce the thickness of the driving layer 20 because the signal shielding layer 40 is patterned in the substrate 23 without adding a layer structure additionally.
In some embodiments, a different point from the above-described embodiments is that the signal shielding layer 40 may be separately provided as a layer structure at a corresponding position. For example, referring to fig. 3b, the driving layer 20 further includes a first insulating layer 25, the first insulating layer 25 is stacked between the switch array layer 21 and the passivation layer 22, and the signal shielding layer 40 is stacked between the first insulating layer 25 and the passivation layer 22. In the present embodiment, the signal shielding layers 40 are connected in series and to the ground potential.
The first insulating layer 25 may have a single-layer silicon oxide (SiO2) or double-layer silicon oxide/silicon nitride (SiO2/SiNx) structure or an organic film structure.
In the signal shielding layer 40, in addition to a shielding portion that can correspond to the covered electrode line assembly 50, a remaining metal portion in the signal shielding layer 40 may constitute a pixel capacitance with the first wiring layer 21 or the second wiring layer 214. By designing the signal shielding layer 40 in such a manner, on one hand, it can shield the interference of high-frequency signals, and on the other hand, it can increase the pixel capacitance and improve the display effect.
In some embodiments, a different point from the above-described embodiments is that the signal shielding layer 40 may be separately provided as a layer structure at another corresponding position. For example, referring to fig. 3c, the driving layer 20 further includes a second insulating layer 26, the second insulating layer 26 is stacked between the substrate 23 and the pixel defining layer 24, and the signal shielding layer 40 is stacked between the second insulating layer 26 and the pixel defining layer 24. In the present embodiment, the signal shielding layers 40 are connected in series and to the ground potential.
The second insulating layer 26 may have a single-layer silicon oxide (SiO2) or double-layer silicon oxide/silicon nitride (SiO2/SiNx) structure or an organic film structure.
In the present embodiment, since the passivation layer 22, the substrate 23 and the second wiring layer 214 are sequentially spaced by the signal shielding layer 40 and the second wiring layer 214, relatively, the distance between the signal shielding layer 40 and the second wiring layer 214 is relatively long, which can reduce the interference of electrons in the signal shielding layer 40 to the second electrode line 502 carrying high frequency signals, i.e. with such design, the signal shielding layer 40 at a long distance can reduce the impedance of the second electrode line 502 compared to the signal shielding layer 40 at a short distance.
As another aspect of the embodiments of the present application, embodiments of the present application provide a display device. In this embodiment, the display panel described in the above embodiments can be selected as the display device.
The signal shielding layer in the display panel can shield high-frequency signals in the electrode wire assembly, so that the influence of the high-frequency signals on the voltage in the pixel electrode layer is reduced, the signal crosstalk phenomenon of the display device is improved, and the display effect of the display device is improved.
Those skilled in the art will appreciate that the processes and materials described in the various embodiments herein are merely exemplary and that the embodiments herein may be used with any processes or materials developed in the future that are suitable for use herein.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; within the context of the present application, where technical features in the above embodiments or in different embodiments can also be combined, the steps can be implemented in any order and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (17)
- A display panel, comprising:a driving layer provided with an electrode line assembly;a pixel unit including a pixel electrode layer laminated on the driving layer;and the signal shielding layer is stacked between the driving layer and the pixel unit and is used for shielding the interference of the signal flowing through the electrode wire assembly on the pixel electrode layer.
- The display panel according to claim 1, wherein a plane on which the driving layer is located is a projection plane, and an orthogonal projection of the signal shielding layer on the projection plane at least partially covers the electrode line assembly.
- The display panel of claim 2, wherein the electrode line assembly comprises:the plurality of first electrode wires are sequentially arranged on the driving layer;the plurality of second electrode wires are sequentially arranged on the driving layer;wherein, the orthographic projection of the signal shielding layer on the projection plane at least covers a part of the plurality of first electrode wires and/or the plurality of second electrode wires.
- The display panel according to claim 3, wherein the signal shielding layer comprises:the orthographic projection of the first signal shielding layer on the projection plane covers all the first electrode wires;and the orthographic projection of the second signal shielding layer on the projection plane covers all the second electrode wires.
- The display panel according to claim 4,the first signal shielding layer comprises a plurality of first signal shielding parts, each first signal shielding part is arranged on the projection plane, the orthographic projection of the projection plane covers a corresponding first electrode wire, and one end of each first signal shielding part is connected to the same preset potential.
- The display panel according to claim 5,the second signal shielding layer comprises a plurality of second signal shielding parts, each second signal shielding part is arranged on the projection plane, the orthographic projection of the projection plane covers a corresponding second electrode wire, and one end of each second signal shielding part is connected to the same preset potential.
- The display panel according to claim 6,any two first electrode wires in the plurality of first electrode wires are parallel to each other, any two second electrode wires in the plurality of second electrode wires are parallel to each other, and any one second electrode wire in the plurality of second electrode wires is intersected with any one first electrode wire in the plurality of first electrode wires;any one of the second signal shielding parts and any one of the first signal shielding parts have overlapping parts.
- The display panel according to claim 6,one end of each first signal shielding part extends out of the display area of the display panel;alternatively, the first and second electrodes may be,one end of each second signal shielding part extends out of the display area of the display panel.
- The display panel according to claim 3,the first electrode lines are data lines, and the second electrode lines are scanning lines;alternatively, the first and second electrodes may be,the first electrode lines are scanning lines, and the second electrode lines are data lines.
- The display panel according to claim 1, wherein the signal shielding layer is connected to a preset potential.
- The display panel according to claim 10, wherein the predetermined potential is a ground potential.
- The display panel according to claim 1, wherein the pixel electrode layer is a cathode.
- The display panel according to any one of claims 1 to 12, wherein the driving layer comprises:a switch array layer provided with the electrode line assembly;a passivation layer stacked on the switch array layer;the substrate is stacked on the passivation layer and is far away from the switch array layer; andand the pixel electrode layer is laminated on the pixel defining layer and is far away from the substrate.
- The display panel according to claim 13, wherein the substrate is patterned to form the signal shielding layer.
- The display panel according to claim 13, wherein the driving layer further comprises a first insulating layer stacked between the switch array layer and the passivation layer, and the signal shielding layer is stacked between the first insulating layer and the passivation layer.
- The display panel according to claim 13, wherein the driving layer further comprises a second insulating layer stacked between the substrate and the pixel defining layer, and wherein the signal shielding layer is stacked between the second insulating layer and the pixel defining layer.
- A display device characterized by comprising the display panel according to any one of claims 1 to 16.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2019/081277 WO2020199164A1 (en) | 2019-04-03 | 2019-04-03 | Display panel and display device |
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| Publication Number | Publication Date |
|---|---|
| CN113348407A true CN113348407A (en) | 2021-09-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201980079793.1A Pending CN113348407A (en) | 2019-04-03 | 2019-04-03 | Display panel and display device |
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| Country | Link |
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| CN (1) | CN113348407A (en) |
| WO (1) | WO2020199164A1 (en) |
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| CN106353945A (en) * | 2016-11-18 | 2017-01-25 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof and display device |
| CN206096715U (en) * | 2016-10-24 | 2017-04-12 | 京东方科技集团股份有限公司 | Array baseplate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104597643A (en) * | 2015-01-30 | 2015-05-06 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof, and display device |
| KR102421629B1 (en) * | 2017-07-05 | 2022-07-18 | 삼성디스플레이 주식회사 | Display apparatus and method of manufacturing the same |
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2019
- 2019-04-03 CN CN201980079793.1A patent/CN113348407A/en active Pending
- 2019-04-03 WO PCT/CN2019/081277 patent/WO2020199164A1/en active Application Filing
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| CN102033367A (en) * | 2009-09-25 | 2011-04-27 | 北京京东方光电科技有限公司 | Display substrate and manufacturing method thereof |
| CN105185791A (en) * | 2015-09-28 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN109154758A (en) * | 2016-05-31 | 2019-01-04 | 伊英克公司 | Backboard for electro-optic displays |
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| WO2020199164A1 (en) | 2020-10-08 |
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Application publication date: 20210903 |