CN113346965B

CN113346965B - Receiver and channel estimation method

Info

Publication number: CN113346965B
Application number: CN202010135217.9A
Authority: CN
Inventors: 李彦邦; 黄亮维
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-03-02
Filing date: 2020-03-02
Publication date: 2023-08-08
Anticipated expiration: 2040-03-02
Also published as: CN113346965A

Abstract

The application discloses a receiver and a channel estimation method. The equalizer circuit is used for processing the first data signal according to the control signal to generate a second data signal. The radio frequency interference elimination circuit system is used for detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information and outputting a correction signal according to the radio frequency interference information to correct the second data signal. The channel estimation circuitry is configured to analyze a plurality of signal components of the second data signal and to generate a control signal using a power ratio of one of the signal components according to the radio frequency interference information.

Description

Receiver and channel estimation method

Technical Field

The present invention relates to a receiver, and more particularly, to a receiver capable of estimating a channel and a channel estimation method thereof.

Background

Equalizer circuits are commonly used in receivers to compensate for channel attenuation. In order to be able to correctly compensate for the channel attenuation, the receiver has to evaluate the channel length. In practice, the receiver may be subject to other noise (e.g., crosstalk, radio frequency interference, etc.) to produce inaccurate channel length estimation results. This can cause the equalizer circuit to provide inaccurate compensation.

Disclosure of Invention

In some embodiments, the receiver includes equalizer circuitry, radio frequency interference cancellation circuitry, and channel estimation circuitry. The equalizer circuit is used for processing the first data signal according to the control signal to generate a second data signal. The radio frequency interference elimination circuit system is used for detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information and outputting a correction signal according to the radio frequency interference information to correct the second data signal. The channel estimation circuitry is configured to analyze a plurality of signal components of the second data signal, the plurality of signal components including a first signal component and a second signal component, each of the plurality of signal components including the first signal component and the second signal component, calculate a power ratio of each of the plurality of signal components and the second signal component, generate channel estimation information based on the radio frequency interference information and the power ratio, and generate the control signal based on the channel estimation information.

In some embodiments, the channel estimation method comprises the following operations: performing an equalization operation in response to the channel estimation information to process the first data signal into a second data signal; detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information, and outputting a correction signal to correct the second data signal according to the radio frequency interference information; and analyzing a plurality of group signal components in the second data signal, the plurality of group signal components including a first group signal component and a second group signal component, each group signal component including a first signal component and a second signal component; calculating the power ratio of each group of first signal components to the second signal components; generating channel estimation information according to the radio frequency interference information and the power ratio, and generating the control signal according to the channel estimation information.

The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram illustrating a receiver according to some embodiments of the present disclosure; fig. 2 is a schematic diagram illustrating the channel estimation circuitry of fig. 1 according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram illustrating operation of the estimation circuit of FIG. 2 according to some embodiments of the present disclosure; and

fig. 4 is a flow chart illustrating a method of channel estimation according to some embodiments of the present disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The above words are defined in commonly used dictionaries, and any examples of the use of words in this document, including any words discussed herein, are merely examples, and should not be interpreted as limiting the scope and meaning of the present disclosure. Similarly, the present disclosure is not limited to the various embodiments shown in this specification.

As used herein, the terms "coupled" or "connected" refer to two or more elements in physical or electrical contact with each other, or in physical or electrical contact with each other, and also refer to two or more elements operating or acting on each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected in a manner by at least one transistor and/or at least one active and passive component to process signals.

As used herein, the term "and/or" includes any combination of one or more of the listed associated items. The terms first, second, third, etc. are used herein to describe and distinguish between components. Accordingly, a first component may also be referred to herein as a second component without departing from the intent of the present disclosure. For ease of understanding, like components in the various figures will be designated with the same reference numerals.

Fig. 1 is a schematic diagram illustrating a receiver 100 according to some embodiments of the present disclosure. In some embodiments, the receiver 100 may be applied to the IEEE 802.3 (2.5 GBASE-T/5GBASE-T/10G BASE-T, etc.) specification. In some embodiments, the receiver 100 may be applied to a gigabit Ethernet (Giga Ethernet) system.

The receiver 100 includes an analog-to-digital converter circuit 101, an adder circuit 102, an echo cancellation circuit 103, a near-end crosstalk (NEXT) cancellation circuit 104, a far-end crosstalk (FEXT) cancellation circuit 105, an equalizer circuit 106, an adder circuit 107, a data decision maker (slicer) circuit 110, radio frequency interference (radio frequency interference, RFI) cancellation circuitry 120, and channel estimation circuitry 130.

The echo cancellation circuit 103, NEXT cancellation circuit 104, and FEXT cancellation circuit 105 operate as noise cancellation circuitry. The echo cancellation circuit 103 may generate a correction signal SC1 to reduce the effect of the echo signal of the channel itself. NEXT cancellation circuit 104 may generate correction signal SC2 to reduce near-end crosstalk from adjacent channels of the same device. FEXT cancellation circuit 105 may generate correction signal SC3 to reduce remote crosstalk from other channels of another device.

The analog-to-digital converter circuit 101 converts the input signal SIN into a data signal S1. The adder circuit 102 adds the data signal S1, the correction signal SC1 and the correction signal SC2 to generate a data signal S2. The equalizer circuit 106 sets its internal circuit parameters (e.g., low band bandwidth, high band bandwidth, low band gain, high band gain, etc.) according to the control signal SCH, and processes the data signal S2 to generate a data signal S3. In some embodiments, equalizer circuit 106 may perform an equalization operation on data signal S2 to compensate for signal distortion due to the channel. The adder circuit 107 adds the data signal S3, the correction signal SC3 and the correction signal SC4 to generate a data signal S4. The data decider circuit 110 generates a data signal S5 according to the data signal S4.

The RFI cancellation circuitry 120 detects the presence of the RFI signal from the data signal S4 and generates a correction signal SC4 to reduce the effect of the RFI signal. In some embodiments, the RFI cancellation circuitry 120 includes RFI detection circuitry 122 and RFI cancellation circuitry 124. The RFI detection circuitry 122 may analyze the data signal S4 to detect an RFI signal.

The RFI detection circuit 122 may calculate a correlation (correlation) between the data signal S4 and the delay signal corresponding to the data signal S4 to output an accumulated value (not shown) and compare the accumulated value with a default threshold to determine whether the RFI signal is present. If the accumulated value is greater than a predetermined threshold (not shown), the RFI detection circuitry 122 confirms that an RFI signal is present. The RFI detection circuit 122 further performs a frequency bin (also referred to as a "frequency bin" or "frequency bin") search operation according to the accumulated value to identify the frequency fmi and the power VRFI of the RFI signal and generate the RFI information SCC accordingly. The RFI cancellation circuit 124 generates a correction signal SC4 to the adder circuit 107 to adjust the data signal S4 based on the RFI information SCC to cancel the effect of the RFI signal.

In some embodiments, the RFI cancellation circuit 124 may be a filter circuit that performs a least mean square (least mean square) algorithm based on the RFI information SCC to generate the correction signal SC4.

In some embodiments, the RFI detection circuitry 122 may directly analyze the data signal S1 to generate RFI information SCC. In some embodiments, the RFI detection circuitry 122 may include a kalman (kalman) filter or the like to detect RFI signals. In the example of fig. 1, the RFI detection circuitry 122 detects an RFI signal using the data signal S4 (and/or the data signal S5 processed via the data decider circuitry 110) that has been processed by the noise cancellation circuitry and equalizer circuitry 106. Ideally, the data signal S4 (and/or the data signal S5) is already relatively low in interference such as echo/near-end crosstalk/long-range crosstalk. In this manner, the RFI detection circuit 122 can generate more accurate detection results without using a Kalman filter under different operating environments. The above embodiments regarding the RFI elimination circuitry 120 are for example, and the disclosure is not limited thereto. Various types of RFI cancellation circuitry 120 are within the scope of the present disclosure.

The channel estimation circuitry 130 analyzes the multiple sets of signal components (e.g., SIG1 and SIG2 in fig. 3 below) in the data signal S4 and generates channel estimation information (e.g., SD3 in fig. 2 below) using the power ratio of one of the sets of signal components according to the RFI information SCC. The channel estimation circuitry 130 generates the aforementioned control signal SCH based on the channel estimation information. In this way, the circuit settings of the equalizer circuit 106 may be adjusted in response to the channel estimation information. In some embodiments, the "channel" may be a physical line (cable) between the receiver 100 and other devices. In some embodiments, a channel may be a signal path between the receiver 100 and other devices for transmitting data.

For example, if the channel length is longer, the attenuation of the high frequency signal transmitted via the channel is greater. Under this condition, the larger the compensation amount that the equalizer circuit 106 needs to provide for the high frequency signal. Thus, by analyzing the data signal S4, the channel estimation circuitry 130 may estimate the current channel length to output the control signal SCH, thereby setting the circuit parameters of the equalizer circuit 106. In addition, to avoid the RFI signal causing a false channel length estimation, the channel estimation circuitry 130 may further select one of the plurality of sets of signal components according to the RFI information SCC, and compare the signal powers of the signal components of each set to determine whether the selected set of signal components are valid, so as to generate channel estimation information according to the selected set of signal components. The description will be described later with reference to fig. 2 to 4.

Fig. 2 is a schematic diagram illustrating the channel estimation circuitry 130 of fig. 1 according to some embodiments of the present disclosure. The channel estimation circuitry 130 includes a conversion circuit 231, a multiplier circuit 232, an accumulator circuit 233, an estimation circuit 234, and a control circuit 235.

The conversion circuit 231 converts the data signal S4 into a frequency domain signal SB. In some embodiments, the conversion circuit 231 may perform a fast fourier transform on the data signal S4 to generate the frequency domain signal SB. The multiplier circuit 232 is coupled to the conversion circuit 231 to receive the frequency domain signal SB. Multiplier circuit 232 multiplies frequency domain signal SB with frequency domain signal SB to generate signal SD1. In other words, the signal SD1 corresponds to a frequency response square value of the frequency domain signal SB, which is used to indicate the power of the data signal S4. The accumulator circuit 233 is coupled to the multiplier circuit 232 and is configured to accumulate the signal SD1 for a predetermined period to generate the signal SD2. The signal SD2 corresponds to the sum of the power values of the signal components on the respective frequency bands in the data signal S4.

The estimation circuit 234 is configured to analyze the plurality of signal components (e.g., SIG1 and SIG2 in fig. 3) in the data signal S4 according to the signal SD2, and select one of the plurality of signal components according to the RFI information SCC to generate the channel estimation information SD3 according to the power ratio of the one of the plurality of signal components. The operation of the estimation circuit 234 will be described later with reference to fig. 3 to 4. The control circuit 235 generates a control signal SCH based on the channel estimation information SD3. The channel estimation information SD3 indicates the estimated channel length. In some embodiments, control circuit 235 may store a lookup table storing a plurality of sets of control parameters corresponding to a plurality of sets of channel lengths. The control circuit 235 selects at least one set of control parameters from the lookup table according to the channel estimation information SD 3-and outputs the control signal SCH. The control circuit 235 may be implemented by digital logic circuits, buffer circuits, etc., but is not limited thereto.

In some embodiments, each of the plurality of circuits of the channel estimation circuitry 130 may be implemented by at least one digital signal processing circuit having operational capabilities to perform the operations performed by the embodiments. In some embodiments, some of the circuitry of the channel estimation circuitry 130 (e.g., conversion circuitry 231, multiplier circuitry 232, accumulator circuitry 233, etc.) may be shared with the noise cancellation circuitry and/or RFI cancellation circuitry 120 described above. Thus, the circuit area and cost of the receiver 100 can be further saved.

Fig. 3 is a schematic diagram illustrating the operation of the estimation circuit 234 of fig. 2 according to some embodiments of the present disclosure. In practical applications, the data signal S4 is formed by a plurality of signal components. The estimation circuit 234 may analyze the plurality of signal components of the data signal S4 to generate the channel estimation information SD3. For example, the data signal S4 includes a first set of signal components SIG1, a second set of signal components SIG2, and RFI signals (if any) having a frequency fmi. The first set of signal components SIG1 includes a signal component M01 having a frequency f01 and a signal component M11 having a frequency f11. The second set of signal components SIG2 includes signal component M02 having a frequency f02 and signal component M12 having a frequency f12. The frequency f01 is set lower than the frequency f02, the frequency f02 is set lower than the frequency f11, and the frequency f11 is set lower than the frequency f12. For example, in an example of a specification applied to IEEE 802.32.5G BASE-T, frequency f01 may be about 12.50MHz, frequency f02 may be about 17.19MHz, frequency f11 may be about 50MHz and frequency f12 may be about 54.69MHz. The above values for each frequency are used for illustration, and the present disclosure is not limited thereto.

It should be appreciated that depending on the actual detection results of the RFI cancellation circuitry 120, the frequency fmi of the RFI signal may be between the frequencies, below frequency f01, or above frequency f12. For ease of understanding, in the example of fig. 3, the frequency fmi is higher than the frequency f12, but the present disclosure is not limited thereto.

As shown in fig. 3, for the purpose of performing a spectral analysis on the data signal S4-, the data signal S4 is processed into a signal SD2. In some embodiments, the estimation circuit 234 may perform a frequency interval searching operation on the signal SD2 to calculate the power lf01 of the signal component M01, the power hf11 of the signal component M11, the power lf02 of the signal component M02, and the power hf12 of the signal component M12. For example, the estimation circuit 234 may sum the signal power in at least one frequency interval corresponding to the frequency f01 in the signal SD2 to obtain the power lf01. By analogy, the estimation circuit 234 can obtain the power hf11, the power lf02 and the power hf12. The estimation circuit 234 divides the power lf01 by the power lf11 to obtain a power ratio lf01/hf11 of the first set of signal components SIG 1. The estimation circuit 234 divides the power lf02 by the power hf12 to obtain a power ratio lf02/hf12 of the second set of signal components SIG2.

The higher the frequency of a signal component, the more channel attenuation that the signal component will experience. In other words, the lower the frequency of the signal component, the higher the power of the signal component. In addition, if the length of the channel is longer, the attenuation caused by the channel is more. Thus, the power ratio between the power of the low frequency signal component (e.g., power lf01 or power lf 02) and the power of the high frequency signal component (e.g., power hf11 or power hf 12) may reflect the channel length. The larger the power ratio, the longer the channel length. Conversely, the smaller the power ratio, the shorter the channel length.

In some embodiments, the estimation circuit 234 may determine the power ratio lf01/hf11 or the power ratio lf02/hf12 to use to generate the channel estimation information SD3 according to the RFI information SCC, the power lf01, the power hf11, the power lf 02-and the power hf12. The operation will be described later with reference to operations S403 to S409 of fig. 4. In some embodiments, the estimation circuit 234 stores a lookup table (not shown) that stores a plurality of channel lengths and a corresponding plurality of power ratios. The estimating circuit 234 may compare the selected power ratio with a plurality of power ratios in the lookup table to determine the channel length corresponding to the selected power ratio and output the channel length as the channel estimation information SD3.

In some embodiments, the estimation circuit 234 may be implemented by a state machine performing operations S403-S409 in fig. 3 and 4. In some embodiments, the state machine described above may be implemented by one or more digital signal processing circuits.

Fig. 4 is a flow chart illustrating a method 400 of channel estimation according to some embodiments of the present disclosure. In some embodiments, various operations of the channel estimation method 400 may be performed by the receiver 100 of fig. 1. For example, operations S401 to S402 may be performed by the RFI cancellation circuitry 120, and operations S403 to S409 may be performed by the channel estimation circuitry 130.

In operation S401, the presence of an RFI signal is detected. If an RFI signal is present, operation S402 is performed. Otherwise, if the RFI signal is not present (or the RFI signal power is too low to be detected), operation S403 is performed. In operation S402, a correction signal is generated according to the RFI information to cancel the RFI signal. For example, the RFI detection circuitry 122 may detect the presence of an RFI signal from the data signal S4. If an RFI signal is present, the RFI detection circuit 122 further determines the frequency fRFI and the power VRFI of the RFI signal and generates RFI information SCC accordingly. The RFI cancellation circuit 124 may generate a correction signal SC4 "to adjust the data signal S4 based on the RFI information SCC to reduce the effect of the RFI signal.

In operation S403, the power of the first signal component and the power of the second signal component of each of the plurality of sets of signal components are calculated. In operation S404, it is determined whether the RFI cancellation circuit is activated. If the RFI cancellation circuit 124 is activated, operation S405 is performed. If the RFI cancellation circuit 124 is not activated, operation S406 is performed. In some embodiments, the estimation circuit 234 may determine whether the RFI cancellation circuit 124 is enabled based on the RFI information SCC. For example, if an RFI signal is detected in operation S401, the RFI cancellation circuit 124 may be activated. Conversely, if no RFI signal is detected in operation S401, the RFI cancellation circuit 124 is not activated.

In operation S405, a power ratio of one of the plurality of signal components is selected, wherein a frequency of the signal component included in the selected one of the plurality of signal components is a frequency farthest from a frequency of the RFI signal in the plurality of signal components. In response to the RFI information SCC, the estimation circuit 234 may learn information about the presence of the RFI signal and the frequency fmi. Taking fig. 3 as an example, the RFI signal is present and the frequency f01 in the first set of signal components SIG1 is furthest from the frequency fmi. After the RFI cancellation circuit 124 reduces the effect of the RFI signal, the estimation circuit 234 selects the power ratio lf01/hf11 of the first set of signal components SIG1 for subsequent generation of the channel estimation information SD3. In the event that the presence of an RFI signal is detected, the power calculation of the aforementioned plurality of signal components may be erroneous. For example, if the frequency fRFI is very close to the frequency f12, the signal component M12 is affected by the RFI signal, resulting in a false increase in the power hf12. Thus, if the power ratio lf02/hf12 is used to estimate the channel length, inaccurate results are obtained. In the case where the presence of an RFI signal is detected, since the frequency f01 is the frequency farthest from the frequency fmi, the influence of the RFI signal on the first composition SIG1 is relatively low. Under this condition, the estimation circuit 234 selects the power ratio lf01/hf11 of the first signal SIG1 including the signal component M01 to estimate the channel length.

It is to be understood that the above description is intended to be illustrative, and not restrictive. As previously described, the frequency fmi may be located between the frequencies, below the frequency f01, or above the frequency f12. In another example, if the frequency f02 or the frequency f12 of the second set of signals SIG2 is the frequency farthest from the frequency fmi, the estimation circuit 234 selects the power ratio lf02/hf12 of the second set of signals SIG2 in operation S405.

In operation S406, the powers of the first signal components are compared to determine whether the powers of the first signal components are decreasing in order, and the powers of the second signal components are comparing to determine whether the powers of the second signal components are decreasing in order. If yes, operation S407 is performed. Otherwise, if the power of the plurality of first signal components (or the plurality of second signal components) is not sequentially decreased, operation S408 is performed. In operation S407, a power ratio of a default signal component of the plurality of signal components is selected. In operation S408, the power ratio of another set of signal components is selected according to the comparison result. In operation S409, channel estimation information is generated according to the power ratio of the selected set of signal components.

For example, as shown in fig. 3, the estimation circuit 234 calculates a power lf01 (i.e., the power of the first signal component M01 in the first group of signal components SIG 1), a power hf11 (i.e., the power of the second signal component M11 in the first group of signal components SIG 1), a power lf02 (i.e., the power of the first signal component M02 in the second group of signal components SIG 2), and a power hf12 (i.e., the power of the second signal component M12 in the second group of signal components SIG 2). The estimation circuit 234 may further compare the power lf01 with the power lf02 and compare the power hf11 with the power hf12. As previously described, the higher the frequency of a signal component, the greater the channel attenuation that the signal component is subjected to. Therefore, power lf01 should be greater than power lf02, and power hf11 should be greater than power hf12. Under this condition, the estimation circuit 234 can determine that the powers of the plurality of signal components are correct. In this example, the second set of higher frequency signal components SIG2 may be default set of signal components. Accordingly, the estimation circuit 234 may select the power ratio lf02/hf12 of the second set of signal components SIG2 to generate the channel estimation information SD3.

If the RFI signal is not detected or is not completely eliminated, the residual RFI signal (or other noise) may still affect the signal component M02 or the signal component M12. Under this condition, the power lf02 or the power hf12 may rise incorrectly. Thus, power lf01 would be no greater than power lf02 or power hf11 would be no greater than power hf12-. Based on the comparison, the estimation circuit 234 can determine that the power lf02 and/or the power hf 12-are incorrect and avoid selecting the second set of signal components SIG2. Accordingly, the estimation circuit 234 selects the power ratio of another set of signal components (in this example, the first set of signal components SIG1 with the lowest frequency) to generate the channel estimation information SD3.

Through the above-described operations, it is ensured that the channel estimation circuitry 130 selects an accurate set of signal components under the influence of the RFI signal to generate accurate channel estimation information SD3 based on the set of signal components.

The above embodiments are only exemplified by the 2 sets of signal components SIG1 and SIG2, but the present invention is not limited thereto. According to practical requirements, the channel estimation circuitry 130 may analyze 2 or more signal components to generate the channel estimation information SD3.

The operations of fig. 3 and 4 are merely examples, and are not limited to be performed in the order of this example. The various operations and/or steps described above may be added, substituted, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the present disclosure.

In summary, the receiver and the channel estimation method provided in some embodiments of the present invention can reduce the influence of the RFI signal and generate more accurate channel estimation information under the influence of the RFI signal. Thus, the convergence speed of each circuit in the receiver can be effectively improved.

Although the embodiments of the present disclosure have been described above, these embodiments are not limited thereto, and those skilled in the art can make various changes to the technical features of the present disclosure according to the explicit or implicit disclosure of the present disclosure, and all such changes may fall within the scope of patent protection sought herein, in other words, the scope of patent protection of the present disclosure shall be defined by the claims of the present disclosure.

[ symbolic description ]

100 receiver 101 analog to digital converter circuit

102,107 adder circuit

103 echo cancellation circuit

104 near-end crosstalk (NEXT) cancellation circuit

105 remote crosstalk (FEXT) cancellation circuit

106 equalizer circuit

110 data decision maker circuit

120 Radio Frequency Interference (RFI) cancellation circuitry

122 RFI detection circuit

124 RFI cancellation circuit

Channel estimation circuitry 130

fRFI frequency

S1, S2, S3, S4, S5 data signal

SC1, SC2, SC3, SC4 correction Signal

SCC-RFI information

SCH control signal

SIN: input signal

VRFI: power

231 conversion circuit

232 multiplier circuit

233 accumulator circuit

234 estimation circuit

235 control circuit

SB frequency domain signal

SD1, SD2 Signal

SD3 channel estimation information

f01, f02, f11, f12: frequency

M01, M02, M11, M12 signal component

SIG1 first Signal component

SIG2 second group Signal Components

Channel estimation method 400

S401 to S409 operations

Claims

1. A receiver, comprising:

an equalizer circuit for processing the first data signal according to the control signal to generate a second data signal;

the radio frequency interference elimination circuit system is used for detecting a radio frequency interference signal according to the second data signal to generate radio frequency interference information and outputting a correction signal according to the radio frequency interference information to correct the second data signal;

and a channel estimation circuitry for analyzing a plurality of signal components in the second data signal, the plurality of signal components including a first signal component and a second signal component, each signal component including the first signal component and the second signal component, calculating a power ratio of each of the first signal component and the second signal component, and generating channel estimation information based on the radio frequency interference information and the power ratio, and generating the control signal based on the channel estimation information.

2. The receiver of claim 1, wherein a first frequency of a first signal component of each set of signal components is lower than a second frequency of a second signal component, the first frequency of the first set of signal components is lower than the first frequency of the second set of signal components, and the second frequency of the first set of signal components is lower than the second frequency of the second set of signal components.

3. The receiver of claim 2 wherein if the channel estimation circuitry determines that the radio frequency interference signal is detected based on the radio frequency interference information, selecting the first frequency or the second frequency as the power ratio of the group signal component of the plurality of group signal components that is the frequency furthest from the frequency of the radio frequency interference signal, and generating channel estimation information based on the selected power ratio of the group signal components.

4. The receiver of claim 2 wherein if the channel estimation circuitry determines that the radio frequency interference signal is not detected based on the radio frequency interference information, the channel estimation circuitry is configured to determine whether power of a plurality of first signal components of the plurality of group signal components decreases in sequence and to determine whether power of a plurality of second signal components of the plurality of group signal components decreases in sequence.

5. The receiver of claim 4 wherein if the power of the first plurality of signal components is sequentially decreasing and the power of the second plurality of signal components is sequentially decreasing, a power ratio of a default set of signal components of the plurality of sets of signal components is selected.

6. The receiver of claim 5 wherein the default set of signal components is the second set of signal components.

7. The receiver of claim 5 wherein the channel estimation circuitry selects a power ratio of another one of the plurality of sets of signals to generate the control signal if the power of the plurality of first signal components is not decreasing in sequence or the power of the plurality of second signal components is not decreasing in sequence.

8. The receiver of claim 1 wherein the channel estimation circuitry comprises: a conversion circuit for converting the second data signal into a frequency domain signal;

a multiplier circuit for multiplying the frequency domain signal with the frequency domain signal to generate a first signal;

an accumulator circuit for accumulating the first signal to generate a second signal;

an estimation circuit for analyzing the plurality of group signal components according to the second signal to generate channel estimation information;

and a control circuit for generating the control signal according to the channel estimation information.

9. The receiver of claim 8 wherein the estimation circuit is configured to:

selecting a group of signal components from the plurality of groups of signal components according to the radio frequency interference information;

analyzing a first power of a first signal component and a second power of a second signal component of each of the plurality of group signal components;

and comparing the first power and the second power of each of the plurality of group signal components to determine whether to generate the channel estimation information according to a power ratio of the first power to the second power.

10. A method of channel estimation, comprising:

performing an equalization operation in response to the channel estimation information to process the first data signal into a second data signal;

detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information, and outputting a correction signal according to the radio frequency interference information to correct the second data signal; and analyzing a plurality of group signal components in the second data signal, the plurality of group signal components including a first group signal component and a second group signal component, each group signal component including a first signal component and a second signal component;

calculating the power ratio of each group of first signal components to the second signal components;

generating channel estimation information according to the radio frequency interference information and the power ratio, and generating a control signal according to the channel estimation information.