CN113346965A

CN113346965A - Receiver and channel estimation method

Info

Publication number: CN113346965A
Application number: CN202010135217.9A
Authority: CN
Inventors: 李彦邦; 黄亮维
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-03-02
Filing date: 2020-03-02
Publication date: 2021-09-03
Anticipated expiration: 2040-03-02
Also published as: CN113346965B

Abstract

The application discloses a receiver and a channel estimation method, wherein the receiver comprises an equalizer circuit, a radio frequency interference elimination circuit system and a channel estimation circuit system. The equalizer circuit is used for processing the first data signal according to the control signal to generate a second data signal. The radio frequency interference elimination circuit system is used for detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information, and outputting a correction signal according to the radio frequency interference information to correct the second data signal. The channel estimation circuit system is used for analyzing a plurality of groups of signal components in the second data signal and generating a control signal by using a power ratio of one of the groups of signal components according to the radio frequency interference information.

Description

Receiver and channel estimation method

Technical Field

The present invention relates to a receiver, and more particularly, to a receiver capable of estimating a channel and a channel estimation method thereof.

Background

Equalizer circuits are commonly used in receivers to compensate for channel fading. In order to correctly compensate for channel attenuation, the receiver needs to evaluate the channel length. In practical applications, the receiver may be affected by other noises (such as crosstalk, radio frequency interference, etc.) to generate inaccurate channel length estimation results. This can cause the equalizer circuit to provide inaccurate compensation.

Disclosure of Invention

In some embodiments, the receiver includes an equalizer circuit, radio frequency interference cancellation circuitry, and channel estimation circuitry. The equalizer circuit is used for processing the first data signal according to the control signal to generate a second data signal. The radio frequency interference elimination circuit system is used for detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information and outputting a correction signal according to the radio frequency interference information to correct the second data signal. The channel estimation circuit system is used for analyzing a plurality of groups of signal components in the second data signal and generating a control signal by using a power ratio of one of the groups of signal components according to the radio frequency interference information.

In some embodiments, the channel estimation method comprises the following operations: performing an equalization operation in response to the channel estimation information to process the first data signal into a second data signal; detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information, and outputting a correction signal according to the radio frequency interference information to correct the second data signal; and analyzing a plurality of groups of signal components in the second data signal, and generating channel estimation information by using the power ratio of one of the groups of signal components according to the radio frequency interference information.

The features, implementations and effects of the present disclosure will be described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram illustrating a receiver according to some embodiments of the present disclosure;

fig. 2 is a schematic diagram illustrating the channel estimation circuitry of fig. 1 according to some embodiments of the present disclosure;

FIG. 3 illustrates an operation of the estimation circuit of FIG. 2 according to some embodiments of the present disclosure; and

fig. 4 is a flow chart illustrating a channel estimation method according to some embodiments of the present disclosure.

[ embodiment ] A method for producing a semiconductor device

All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries are provided, and any use of the words discussed herein in this disclosure is by way of example only and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the disclosure is not limited to the various embodiments shown in this specification.

As used herein, a "coupled" or "connected" means that two or more elements are in direct or indirect physical or electrical contact with each other, or that two or more elements are in mutual operation or action. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a certain manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like may be used herein to describe and distinguish various elements. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the disclosure. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

Fig. 1 is a schematic diagram illustrating a receiver 100 according to some embodiments of the present disclosure. In some embodiments, receiver 100 may be implemented in the IEEE 802.3(2.5GBASE-T/5GBASE-T/10G BASE-T, etc.) specification. In some embodiments, the receiver 100 may be used in a gigabit Ethernet (Giga Ethernet) system.

The receiver 100 includes an analog-to-digital converter circuit 101, an adder circuit 102, an echo cancellation circuit 103, a near-end crosstalk (NEXT) cancellation circuit 104, a far-end crosstalk (FEXT) cancellation circuit 105, an equalizer circuit 106, an adder circuit 107, a data decider (slicer) circuit 110, Radio Frequency Interference (RFI) cancellation circuitry 120, and channel estimation circuitry 130.

The echo cancellation circuit 103, NEXT cancellation circuit 104, and FEXT cancellation circuit 105 operate as noise cancellation circuitry. The echo cancellation circuit 103 may generate a correction signalS_C1To reduce the effect of the echo signal of the channel itself. The NEXT cancellation circuit 104 can generate a correction signal S_C2To reduce near-end crosstalk from adjacent channels of the same device. The FEXT cancellation circuit 105 may generate a correction signal S_C3To reduce remote crosstalk from other channels of another device.

The analog-to-digital converter circuit 101 converts the input signal S_INAs a data signal S₁. Adder circuit 102 adds up data signal S₁Correcting signal S_C1And a correction signal S_C2To generate a data signal S₂. The equalizer circuit 106 is responsive to the control signal S_CHSets its internal circuit parameters (e.g. low band bandwidth, high band bandwidth, low band gain, high band gain, etc.) and processes the data signal S₂To generate a data signal S₃. In some embodiments, the equalizer circuit 106 may be coupled to the data signal S₂An equalization operation is performed to compensate for signal distortion due to the channel. Adder circuit 107 adds up data signal S₃Correcting signal S_C3And a correction signal S_C4To generate a data signal S₄. The data decision circuit 110 is based on the data signal S₄Generating a data signal S₅。

The RFI cancellation circuitry 120 is responsive to the data signal S₄Detecting the presence of RFI signals and generating a correction signal S_C4To reduce the effects of RFI signals. In some embodiments, the RFI cancellation circuitry 120 includes an RFI detection circuit 122 and an RFI cancellation circuit 124. The RFI detection circuitry 122 may analyze the data signal S₄To detect RFI signals.

The RFI detection circuitry 122 may calculate the data signal S₄And corresponds to the data signal S₄The correlation between the delayed signals (correlation) to output an accumulated value (not shown), and comparing the accumulated value with a predetermined threshold value to confirm the presence or absence of the RFI signal. If the accumulated value is greater than a preset threshold value (not shown), the RFI detection circuit 122 confirms that an RFI signal is present. The RFI detection circuit 122 further performs a frequency bin (also called "frequency bin" or "frequency bin") search operation according to the accumulated value to find out the frequency binIdentifying the frequency f of the RFI signal_RFIAnd power V_RFIAnd generates RFI information S based thereon_CC. The RFI cancellation circuit 124 generates RFI information S based on the RFI information S_CCGenerating a correction signal S_C4To the adder circuit 107 to adjust the data signal S₄To eliminate the effect of RFI signals. In some embodiments, the RFI cancellation circuit 124 may be a filter circuit that is based on the RFI information S_CCPerforming a least mean square (least mean square) algorithm to produce a correction signal S_C4。

In some embodiments, the RFI detection circuit 122 may directly analyze the data signal S₁To generate RFI information S_CC. In some embodiments, the RFI detection circuit 122 may include a kalman (kalman) filter or other circuit to detect the RFI signal. In the example of fig. 1, RFI detection circuit 122 uses data signal S processed by noise cancellation circuitry and equalizer circuit 106₄(and/or the data signal S processed by the data decision circuit 110₅) To detect RFI signals. Ideally, the data signal S₄(and/or data signal S)₅) The interference such as echo/near-end crosstalk/far-end crosstalk is relatively low. As such, RFI detection circuit 122 may produce more accurate detection results without using a kalman filter under different operating environments. The above embodiments of the RFI cancellation circuitry 120 are for illustration and the disclosure is not limited thereto. Various types of RFI cancellation circuitry 120 are contemplated.

The channel estimation circuitry 130 analyzes the data signal S₄Multiple groups of signal components (such as SIG1 and SIG2 in FIG. 3), and based on RFI information S_CCGenerating channel estimation information using the power ratio of one of the sets of signal components (e.g., S in FIG. 2_D3). The channel estimation circuit system 130 generates the aforementioned control signal S according to the channel estimation information_CH. As such, the circuit settings of the equalizer circuit 106 may be adjusted in response to the channel estimation information. In some embodiments of the present invention, the first and second electrodes are,

"channel" can be a physical line (cable) between receiver 100 and other devices. In some embodiments, a "channel" may be the signal path used to transmit data between receiver 100 and other devices.

For example, the longer the channel length, the greater the attenuation of the high frequency signal transmitted through the channel. Under this condition, the greater the amount of compensation that the equalizer circuit 106 needs to provide for the high frequency signal. Thus, by analyzing the data signal S₄The channel estimation circuit 130 estimates the current channel length to output the control signal S_CHThereby setting circuit parameters of the equalizer circuit 106. In addition, to avoid channel length estimation errors caused by RFI signals, the channel estimation circuitry 130 may further determine the channel length based on the RFI information S_CCOne of the plurality of sets of signal components is selected and the signal powers of the respective sets of signal components are compared to determine whether the selected set of signal components is valid, thereby generating channel estimation information based on the selected set of signal components. The description about this will be described later with reference to FIGS. 2 to 4.

Fig. 2 is a schematic diagram illustrating the channel estimation circuitry 130 of fig. 1 according to some embodiments of the present disclosure. The channel estimation circuitry 130 includes a conversion circuit 231, a multiplier circuit 232, an accumulator circuit 233, an estimation circuit 234, and a control circuit 235.

The conversion circuit 231 converts the data signal S₄As a frequency domain signal S_B. In some embodiments, the conversion circuit 231 can convert the data signal S₄Performing a fast Fourier transform to produce a frequency domain signal S_B. The multiplier circuit 232 is coupled to the conversion circuit 231 for receiving the frequency domain signal S_B. Multiplier circuit 232 multiplies frequency domain signal S_BAnd the frequency domain signal S_BTo generate a signal S_D1. In other words, the signal S_D1Equivalent to the frequency domain signal S_BFor indicating the data signal S₄Of the power of (c). The accumulator circuit 233 is coupled to the multiplier circuit 232 and accumulates the signal S for a predetermined period_D1To generate a signal S_D2. Signal S_D2Corresponding to the data signal S₄The sum of the power values of the signal components over the respective frequency bands.

The estimation circuit 234 is used for estimating the S signal_D2Analysing the data signal S₄Plural groups ofSignal components (e.g., SIG1 and SIG2 in FIG. 3), and based on the RFI information S_CCSelecting one of the plurality of sets of signal components to generate channel estimation information S based on a power ratio of the one of the plurality of sets of signal components_D3. The operation of the estimation circuit 234 will be described with reference to FIGS. 3-4. The control circuit 235 estimates the information S according to the channel_D3Generating a control signal S_CH. Channel estimation information S_D3Indicating the estimated channel length. In some embodiments, the control circuit 235 may store a lookup table storing a plurality of sets of control parameters corresponding to a plurality of sets of channel lengths. The control circuit 235 may be configured to estimate the channel S according to the channel estimation information S_D3-Selecting at least one group of control parameters from the lookup table and outputting the control parameters as a control signal S_CH. The control circuit 235 may be implemented by a digital logic circuit, a register circuit, etc., but the present disclosure is not limited thereto.

In some embodiments, each of the plurality of circuits of the channel estimation circuitry 130 may be implemented by at least one digital signal processing circuit having computing capabilities to perform the operations performed by the various embodiments. In some embodiments, portions of the circuitry of the channel estimation circuitry 130 (e.g., the conversion circuitry 231, the multiplier circuitry 232, the accumulator circuitry 233, etc.) may be shared with the aforementioned noise cancellation circuitry and/or RFI cancellation circuitry 120. Thus, the circuit area and cost of the receiver 100 can be further saved.

Fig. 3 is a schematic diagram illustrating operation of the estimation circuit 234 of fig. 2 according to some embodiments of the present disclosure. In practical applications, the data signal S₄Is formed from a plurality of signal components. The estimation circuit 234 may analyze the data signal S₄To generate channel estimation information S_D3. For example, the data signal S₄Includes a first group of signal components SIG1, a second group of signal components SIG2, and a frequency f_RFIIf any. The first set of signal components SIG1 includes a frequency f₀₁Signal component M of₀₁And a frequency of f₁₁Signal component M of₁₁. The second set of signal components SIG2 includes a frequency f₀₂Signal component M of₀₂And a frequency of f₁₂Signal generation ofDivide M₁₂. Frequency f₀₁Set to be lower than the frequency f₀₂Frequency f₀₂Set to be lower than the frequency f₁₁And a frequency f₁₁Set to be lower than the frequency f₁₂. For example, in the example of the specification applied to IEEE 802.32.5G BASE-T, the frequency f₀₁May be about 12.50MHz, frequency f₀₂May be about 17.19MHz, frequency f₁₁May be about 50MHz and frequency f₁₂May be about 54.69 MHz. The above numerical values related to the frequencies are used for example, and the present disclosure is not limited thereto.

It should be appreciated that the frequency f of the RFI signal is dependent upon the actual detection results of the RFI cancellation circuitry 120_RFIMay lie between the above-mentioned frequencies, below frequency f₀₁Or above the frequency f₁₂. For ease of understanding, in the example of FIG. 3, frequency f_RFIIs higher than the frequency f₁₂However, the present disclosure is not limited thereto.

As shown in fig. 3, in order to process the data signal S_4-Performing a spectral analysis on the data signal S₄Is processed into a signal S_D2. In some embodiments, the estimation circuit 234 may be coupled to the signal S_D2Performing a frequency interval search operation to calculate a signal component M₀₁Power lf of₀₁Signal component M₁₁Power hf of₁₁Signal component M₀₂Power lf of₀₂And a signal component M₁₂Power hf of₁₂. For example, the estimation circuit 234 may sum the signal S_D2Middle frequency f₀₁Obtaining the power lf of the signal in the corresponding at least one frequency interval₀₁. By analogy, the estimation circuit 234 can obtain the power hf₁₁Power lf₀₂And power hf₁₂. The estimation circuit 234 outputs the power lf₀₁Divided by power lf₁₁To obtain a power ratio lf of the first set of signal components SIG1₀₁/hf₁₁. The estimation circuit 234 outputs the power lf₀₂Divided by power hf₁₂To obtain a power ratio lf of the second set of signal components SIG2₀₂/hf₁₂。

The higher the frequency of the signal component, the more channel attenuation the signal component undergoes.In other words, the lower the frequency of a signal component, the higher the power of the signal component. In addition, the longer the length of the channel, the more attenuation the channel causes. Thus, the power of the low frequency signal component (e.g. power lf)₀₁Or power lf₀₂) With power of high-frequency signal components (e.g. power hf)₁₁Or power hf₁₂) The power ratio between may reflect the channel length. The larger the power ratio, the longer the channel length. Conversely, the smaller the power ratio, the shorter the channel length.

In some embodiments, the estimation circuit 234 may be based on the RFI information S_CCPower lf₀₁Power hf₁₁Power lf_02-And power hf₁₂Determining the used power ratio lf₀₁/hf₁₁Or power ratio lf₀₂/hf₁₂To generate channel estimation information S_D3. Operations herein will be described later with reference to operations S403 to S409 of fig. 4. In some embodiments, the estimation circuit 234 stores a look-up table (not shown) storing a plurality of channel lengths and a plurality of corresponding power ratios. The estimation circuit 234 compares the selected power ratio with a plurality of power ratios in the lookup table to determine a channel length corresponding to the selected power ratio and outputs the channel length as the channel estimation information S_D3。

In some embodiments, the estimation circuit 234 may be implemented by a state machine executing the operations S403 to S409 in fig. 3 and 4. In some embodiments, the state machine may be implemented by one or more digital signal processing circuits.

Fig. 4 is a flow chart illustrating a channel estimation method 400 according to some embodiments of the present disclosure. In some embodiments, the operations of the channel estimation method 400 may be performed by the receiver 100 of fig. 1. For example, operations S401 to S402 may be performed by RFI cancellation circuitry 120, and operations S403 to S409 may be performed by channel estimation circuitry 130.

In operation S401, whether an RFI signal is present is detected. If the RFI signal is present, operation S402 is performed. Otherwise, if the RFI signal is not present (or if the power of the RFI signal is too small to be detected), operation S403 is performed. In operation S402, an RFI message is generatedA correction signal is generated to cancel the RFI signal. For example, the RFI detection circuitry 122 may be based on the data signal S₄The presence of an RFI signal is detected. If an RFI signal is present, the RFI detection circuit 122 further determines the frequency f of the RFI signal_RFIAnd power V_RFIAnd generates RFI information S based thereon_CC. The RFI cancellation circuitry 124 may be based on the RFI information S_CCGenerating a correction signal S_C4-To adjust the data signal S₄Thereby reducing the effect of RFI signals.

In operation S403, the power of the first signal component and the power of the second signal component of each of the plurality of sets of signal components are calculated. In operation S404, it is determined whether the RFI cancellation circuit is activated. If the RFI cancellation circuit 124 is activated, operation S405 is performed. If the RFI cancellation circuit 124 is not activated, operation S406 is performed. In some embodiments, the estimation circuit 234 may be based on the RFI information S_CCIt is determined whether the RFI cancellation circuit 124 is active. For example, if an RFI signal is detected in operation S401, the RFI cancellation circuit 124 may be activated. On the contrary, if no RFI signal is detected in operation S401, the RFI cancellation circuit 124 is not activated.

In operation S405, a power ratio of one of the signal components is selected, wherein the selected signal component has a frequency farthest from the frequency of the RFI signal. In response to RFI information S_CCThe estimation circuit 234 can know whether the RFI signal exists and the frequency f_RFIThe information of (1). Taking fig. 3 as an example, the RFI signal is present and the frequency f in the first set of signal components SIG1₀₁From frequency f_RFIThe farthest. After the RFI cancellation circuit 124 has reduced the effects of the RFI signal, the estimation circuit 234 selects the power ratio lf of the first set of signal components SIG1₀₁/hf₁₁For subsequent generation of channel estimation information S_D3. In the case where the presence of an RFI signal is detected, the power calculation of the aforementioned multiple signal components may be erroneous. For example, if the frequency f_RFIVery close to the frequency f₁₂Signal component M₁₂Will be affected by the RFI signal, resulting in a power hf₁₂Rising by mistake. Thus, if the power ratio lf is used₀₂/hf₁₂To estimateThe channel length, may yield inaccurate results. In case of detecting the presence of an RFI signal, due to the frequency f₀₁Is a frequency f_RFIAt the most distant frequencies, the first group of components SIG1 is relatively less affected by the RFI signal. Under this condition, the estimation circuit 234 selects the signal component M₀₁Power ratio lf of the first set of signals SIG1₀₁/hf₁₁To estimate the channel length.

It should be understood that the above description is by way of example only and that the present disclosure is not limited thereto. As mentioned previously, frequency f_RFIMay lie between the above-mentioned frequencies, below frequency f₀₁Or above the frequency f₁₂. In other examples, if the frequency f in the second set of signals SIG2₀₂Or frequency f₁₂Is a frequency f_RFIFor the farthest frequency, the estimation circuit 234 selects the power ratio lf of the second set of signals SIG2 in operation S405₀₂/hf₁₂。

In operation S406, the powers of the first signal components are compared to determine whether the powers of the first signal components are sequentially decreased, and the powers of the second signal components are compared to determine whether the powers of the second signal components are sequentially decreased. If so, operation S407 is performed. Otherwise, if the powers of the first signal components (or the second signal components) are not sequentially decreased, operation S408 is performed. In operation S407, a power ratio of a default set of signal components in the plurality of sets of signal components is selected. In operation S408, the power ratio of another signal component of the plurality of signal components is selected according to the comparison result. In operation S409, channel estimation information is generated according to the selected power ratio of the set of signal components.

For example, as shown in FIG. 3, the estimation circuit 234 calculates the power lf₀₁(i.e., the first signal component M of the first set of signal components SIG1₀₁Power of), power hf₁₁(i.e., the second signal component M of the first set of signal components SIG1₁₁Power of), power lf₀₂(i.e., the first signal component M of the second set of signal components SIG2₀₂Power of) and power hf₁₂(i.e., the second signal component M of the second set of signal components SIG2₁₂Power of). The estimation circuit 234 may further compare the power lf₀₁And power lf₀₂And comparing the powers hf₁₁And power hf₁₂. As previously described, the higher the frequency of a signal component, the greater the channel attenuation experienced by that signal component. Therefore, power lf₀₁Should be greater than the power lf₀₂And power hf₁₁Should be greater than the power hf₁₂. Under this condition, the estimation circuit 234 determines that the powers of the signal components are all correct. In this example, the second set of higher frequency signal components SIG2 may be the default set of signal components. Accordingly, the estimation circuit 234 may select the power ratio lf of the second set of signal components SIG2₀₂/hf₁₂To generate channel estimation information S_D3。

If the RFI signal is not detected or not completely cancelled, the residual RFI signal (or other noise) may still affect the signal component M₀₂Or signal component M₁₂. Under this condition, the power lf₀₂Or power hf₁₂Will rise incorrectly. Thus, power lf₀₁Will not be greater than power lf₀₂Or power hf₁₁Will not be greater than the power hf_12-. Based on the comparison result, the estimation circuit 234 determines the power lf₀₂And/or power hf_12-Incorrectly, and should avoid selection of the second set of signal components SIG 2. Accordingly, the estimation circuit 234 selects the power ratio of another signal component (in this case, the first signal component SIG1 with the lowest frequency) to generate the channel estimation information S_D3。

Through the above operations, it is ensured that the channel estimation circuitry 130 selects an accurate set of signal components under the influence of the RFI signal to generate accurate channel estimation information S based on the set of signal components_D3。

The above embodiments only take 2 sets of signal components SIG1 and SIG2 as examples, but the disclosure is not limited thereto. According to actual requirements, the channel estimation circuit system 130 can analyze 2 or more sets of signal components to generate the channel estimation information S_D3。

The operations in fig. 3 and 4 are only examples, and are not limited to being performed in the order in this example. Various operations and/or various steps described above may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner and scope of operation of various embodiments of the disclosure.

In summary, the embodiments of the present disclosure provide a receiver and a channel estimation method that can reduce the influence of RFI signals and generate more accurate channel estimation information under the influence of RFI signals. Thus, the convergence speed of each circuit in the receiver can be effectively improved.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the contents of the present invention, which may fall within the scope of the patent protection sought by the present invention.

[ notation ] to show

100 receiver

101 analog-to-digital converter circuit

102,107 adder circuit

103 echo cancellation circuit

104 near-end crosstalk (NEXT) cancellation circuit

105 remote crosstalk (FEXT) cancellation circuit

106 equalizer circuit

110 data decision maker circuit

120 Radio Frequency Interference (RFI) cancellation circuitry

RFI detection circuit

RFI cancellation Circuit

130 channel estimation circuitry

f_RFIFrequency of

S₁,S₂,S₃,S₄,S₅Data signal

S_C1,S_C2,S_C3,S_C4Correction signal

S_CCRFI information

S_CHControl signal

S_INInput signal

V_RFIPower of

231 conversion circuit

232 multiplier circuit

233 accumulator circuit

234 estimation circuit

235 control circuit

S_BFrequency domain signal

S_D1,S_D2Signal

S_D3Channel estimation information

f₀₁,f₀₂,f₁₁,f₁₂Frequency of

M₀₁,M₀₂,M₁₁,M₁₂Signal component

SIG1 first group of signal components

SIG2 second group of signal components

400 channel estimation method

S401 to S409 operation

Claims

1. A receiver, comprising:

an equalizer circuit for processing a first data signal according to a control signal to generate a second data signal;

a radio frequency interference elimination circuit system for detecting a radio frequency interference signal according to the second data signal to generate radio frequency interference information and outputting a correction signal according to the radio frequency interference information to correct the second data signal; and

channel estimation circuitry analyzes a plurality of groups of signal components in the second data signal and generates the control signal using a power ratio of one of the groups of signal components based on the RF interference information.

2. The receiver of claim 1, wherein each of the sets of signal components includes a first signal component and a second signal component, a first frequency of the first signal component being lower than a second frequency of the second signal component, the first frequency of a first one of the sets of signal components being lower than the first frequency of a second one of the sets of signal components, and the second frequency of the first one of the sets of signal components being lower than the second frequency of the second one of the sets of signal components.

3. The receiver of claim 2 wherein the first frequency or the second frequency of the one of the sets of signal components is a frequency of the sets of signal components that is farthest from a frequency of the RF interference signal if the channel estimation circuitry determines that the RF interference signal is detected based on the RF interference information.

4. The receiver of claim 2 wherein the channel estimation circuitry is further configured to determine whether the power of the first signal components in the plurality of signal components decreases in sequence and to determine whether the power of the second signal components in the plurality of signal components decreases in sequence if the channel estimation circuitry determines that the RF interference signal is not detected based on the RF interference information.

5. The receiver of claim 4 wherein the one of the sets of signal components is a default set of signal components if the power of the first signal components is sequentially decreasing and the power of the second signal components is sequentially decreasing.

6. The receiver of claim 5 wherein the default set of signal components is the second set of signal components.

7. The receiver of claim 5 wherein the channel estimation circuitry selects another one of the sets of signals to generate the control signal if the power of the first signal components is not sequentially decreasing or the power of the second signal components is not sequentially decreasing.

8. The receiver of claim 1 wherein the channel estimation circuitry comprises:

a conversion circuit for converting the second data signal into a frequency domain signal;

a multiplier circuit for multiplying the frequency domain signal and the frequency domain signal to generate a first signal;

an accumulator circuit for accumulating the first signal to generate a second signal;

an estimation circuit for analyzing the plurality of signal components according to the second signal to generate a channel estimation information; and

a control circuit for generating the control signal according to the channel estimation information.

9. The receiver of claim 8 wherein the estimation circuit is configured to:

selecting the one of the sets of signal components from the sets of signal components based on the radio frequency interference information;

analyzing a first power of a first signal component and a second power of a second signal component of each of the sets of signal components; and

comparing the first power of each of the plurality of sets of signal components with the second power of each of the plurality of sets of signal components to determine whether to generate the channel estimation information based on the power ratio.

10. A method for channel estimation, comprising:

performing an equalization operation in response to a channel estimation information to process a first data signal into a second data signal;

detecting a radio frequency interference signal according to the second data signal to output radio frequency interference information, and outputting a correction signal according to the radio frequency interference information to correct the second data signal; and

a plurality of groups of signal components in the second data signal are analyzed, and a power ratio of one of the groups of signal components is used to generate the channel estimation information according to the radio frequency interference information.