CN113345904A - Substrate processing method and semiconductor device manufactured by the same - Google Patents
Substrate processing method and semiconductor device manufactured by the same Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000003672 processing method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 113
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 113
- 239000010937 tungsten Substances 0.000 claims abstract description 113
- 238000006243 chemical reaction Methods 0.000 claims abstract description 65
- 239000013078 crystal Substances 0.000 claims abstract description 48
- 230000006911 nucleation Effects 0.000 claims abstract description 36
- 238000010899 nucleation Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 26
- 230000007704 transition Effects 0.000 claims description 22
- 238000011065 in-situ storage Methods 0.000 claims description 7
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- 239000010410 layer Substances 0.000 description 176
- 239000007789 gas Substances 0.000 description 80
- 230000003746 surface roughness Effects 0.000 description 10
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- 238000000151 deposition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000011800 void material Substances 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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Abstract
A substrate processing method according to an aspect of the present invention includes: loading the substrate having the groove into the chamber; forming a nucleation layer containing tungsten (W) on an inner wall of the groove; forming a first tungsten bulk layer on the nucleation layer to partially fill the interior of the groove; forming a crystalline conversion layer on the first tungsten bulk layer; and forming a second tungsten bulk layer with grain size relatively smaller than that of the first tungsten bulk layer on the crystal conversion layer so as to completely fill the inside of the groove.
Description
Technical Field
The present invention relates to the manufacture of semiconductor devices, and more particularly, to a substrate processing method for forming a tungsten thin film on a substrate having a recess, and a semiconductor device manufactured by the substrate processing method.
Background
Recently, with the demand for high capacity and low power consumption of memory devices, research on a new generation of memory devices that do not require refresh while being nonvolatile is being conducted. Such a new-generation Memory device is required to have high integration of a DRAM (Dynamic Random Access Memory), non-volatility of a flash Memory, high speed of an SRAM (Static RAM), and the like. As a new-generation Memory device, PRAM (Phase change RAM), NFGM (Nano Floating Gate Memory), PoRAM (Polymer RAM), MRAM (Magnetic RAM), FeRAM (Ferroelectric RAM), RRAM (Resistive RAM), and the like have been proposed as a new-generation Memory device that meets the above requirements.
Further, as the integration degree of the semiconductor device increases, the design rule of the components of the semiconductor device is decreasing. The formation process of a plurality of wirings and a plurality of Buried electrodes (BC) interposed therebetween in a highly scaled semiconductor device becomes more and more complicated and difficult. For example, a pattern defect is caused in a subsequent process because a step is formed due to a structural difference between a cell (cell) region and a peripheral (peri) region.
In particular, in the case where tungsten (W) metal is used as a lower wiring in a NAND device of cop (cell On peri) structure, it is necessary to have low resistivity. While tungsten metal should deposit a tungsten (W) thin film having a relatively large Grain Size (Grain Size) in order to have low resistivity. In this case, there is a problem that the possibility that defects (defects) such as seams (seam) or voids (void) may occur after CMP (Chemical Mechanical Polishing) is very high.
In addition, in the case of depositing a tungsten thin film having a relatively small grain size, the inside of the pattern can be densely filled, but there is a problem in that the resistivity of the thin film is increased.
Disclosure of Invention
(problem to be solved)
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a substrate processing method capable of forming a tungsten thin film having a low resistivity in a semiconductor device, and a semiconductor device manufactured by the substrate processing method. However, such problems are merely exemplary and should not be construed as limiting the scope of the present invention.
(means for solving the problems)
A substrate processing method according to an aspect of the present invention may include: loading the substrate having the groove into the chamber; forming a nucleation layer containing tungsten (W) on an inner wall of the groove; forming a first tungsten bulk layer on the nucleation layer to partially fill the interior of the groove; forming a crystalline conversion layer on the first tungsten bulk layer; and forming a second tungsten bulk layer with grain size relatively smaller than that of the first tungsten bulk layer on the crystal conversion layer so as to completely fill the inside of the groove.
According to the substrate processing method, the step of forming the crystal conversion layer may include applying WF6Gas and B2H6Supplying a gas into the chamber to form the crystalline conversion layer. The crystalline transition layer may perform the function of forming small grains of a second tungsten bulk layer of the second tungsten bulk layer for initializing grains of the second tungsten bulk layer to be subsequently deposited.
According to the substrate processing method, the step of forming the crystalline conversion layer may include: in the connection of WF6Gas and B2H6After the step of supplying gas into the chamber to form the crystal transition layer, WF is supplied6Gas and SiH4A step of continuously supplying gas into the chamber to form the crystal conversion layer.
According to the substrate processing method, the step of forming the crystalline conversion layer may include adding H in addition to the source gas2A step of supplying a gas into the chamber to form the crystal conversion layer.
According to the substrate processing method, the step of forming the nucleation layer, the step of forming the first tungsten bulk layer, the step of forming the crystal conversion layer, and the step of forming the second tungsten bulk layer may be steps formed by an in-situ (in-situ) process within the chamber.
According to the substrate processing method, the crystal conversion layer may have
To
The thickness range of (a).
According to the substrate processing method, the step of forming the crystalline conversion layer may be performed before the opening of the recess region is blocked by the first tungsten bulk layer.
According to the substrate processing method, the crystal conversion layer may be formed before the opening of the groove region is blocked 1/2 to 2/3 region by the first tungsten bulk layer.
According to the substrate processing method, the forming the nucleation layer may include applying WF to the nucleation layer6Gas and B2H6Supplying a gas into the chamber to form the nucleation layer.
According to the substrate processing method, the step of forming the first tungsten bulk layer may include applying WF6Gas and H2Supplying a gas into the chamber to form the first tungsten bulk layer.
According to the substrate processing method, the step of forming the second tungsten bulk layer may include applying WF6Gas and H2Supplying a gas into the chamber to form the second tungsten bulk layer.
A semiconductor device according to another aspect of the present invention may include: a substrate having a groove; a nucleation layer containing tungsten (W) and formed on an inner wall of the groove; a first tungsten bulk layer formed on the nucleation layer to partially fill the inside of the groove; a crystalline conversion layer formed on the first tungsten bulk layer; and a second tungsten bulk layer having a grain size relatively smaller than that of the first tungsten bulk layer and formed on the crystal transition layer to fill the inside of the groove entirely.
According to the halfThe crystal conversion layer may have
To
The thickness range of (a).
According to the semiconductor device, the crystalline conversion layer is formed within the region 1/2 to 2/3 of the width inside the groove region.
(Effect of the invention)
According to an embodiment of the present invention configured as described above, there can be provided a substrate processing method capable of forming a tungsten thin film having low resistivity and no seam (seam) or void (void) in a semiconductor device, and a semiconductor device manufactured using the substrate processing method. Of course, the scope of the present invention is not limited to this effect.
Drawings
Fig. 1 is a process flow diagram schematically illustrating a substrate processing method according to an embodiment of the present invention.
Fig. 2 is a view schematically showing the structure of a semiconductor device for explaining a substrate processing method according to an embodiment of the present invention.
Fig. 3 is a picture of analyzing a minute structure of a sample of a semiconductor device manufactured by the substrate processing method of the experimental example of the present invention with a scanning electron microscope.
Detailed Description
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Embodiments of the present invention are provided so that the present invention will be more fully informed to those having ordinary skill in the art that the following embodiments may be varied into various other forms, and the scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In addition, the thickness or size of each layer is exaggerated in the drawings for convenience and clarity of description.
Embodiments of the present invention will be described below with reference to the drawings schematically showing preferred embodiments of the present invention. In the figures, the deformation of the illustrated shape can be predicted, for example, according to manufacturing techniques and/or tolerances (tolerance). Thus, the embodiments of the inventive concept are not to be construed as being limited to the specific shapes of regions illustrated in the present specification, and should include shape variations such as those caused by manufacturing.
Fig. 1 is a process flow diagram schematically illustrating a substrate processing method according to an embodiment of the present invention.
Referring to fig. 1, a substrate processing method S100 may sequentially perform processes of a step S110 of loading a substrate, a step S120 of forming a nucleation layer, a step S130 of forming a first tungsten bulk layer, a step S140 of forming a crystal conversion layer, a step S150 of forming a second tungsten bulk layer, and a step S160 of removing the substrate. A detailed description of each step will be described below with reference to fig. 2. On the other hand, the substrate processing method S100 may further include a purge and pump-down step between the steps.
In addition, the steps S120 through S150 of forming the nucleation layer to the second tungsten bulk layer may be performed by an in-situ (in-situ) process within the chamber. As an example, the in-situ process refers to performing these steps in series in a first chamber within a single apparatus consisting of more than one chamber.
As another example, the manner in which each step is performed within a respective chamber may be included.
May include a manner of performing step S130 of forming a first tungsten bulk layer in the second chamber after performing step S120 of forming a nucleation layer in the first chamber, and then performing step S150 of forming a second tungsten bulk layer in the fourth chamber after performing step S140 of forming a crystal conversion layer in the third chamber. In the case of performing in-situ, a step of exposing to atmospheric pressure between a deposition process and an etching process may be prevented or minimized, thus preventing formation of an unnecessary oxide film, and an effect of maximizing efficiency of the process may be expected.
Fig. 2 is a view schematically showing the structure of a semiconductor device for explaining a substrate processing method according to an embodiment of the present invention.
First, referring to (b) to (d) of fig. 2, in the case of a NAND device of a cop (cell On peri) structure, a nucleation layer 210 containing tungsten (W) and tungsten bulk layers 220a and 220b may be sequentially deposited and filled On inner walls of a groove (hole) formed On the substrate 100 having an aspect ratio of about 1: 1 to 1: 1.5. Here, the substrate 100 may include, for example, a wafer (wafer), and the groove may have inner walls whose cross sections face each other and a bottom surface connecting the inner walls. The inner wall may be formed perpendicular to the bottom surface, but may be formed to be inclined at a predetermined inclination from the bottom surface. Further, the recess may include a hole shape or a structure formed to be elongated by a trench formation.
On the other hand, as shown in fig. 2 (b), when the crystal grains of the tungsten (W) bulk layer 220a are small, the Gap-fill (Gap-fill) characteristic and the junction characteristic are improved, but there is a problem that the resistivity is very high. In the case where tungsten (W) metal is used as the lower wiring, it is necessary to have low resistance characteristics, and therefore, in order to reduce contact resistance (contact resistance) at the interface, the grain size of the tungsten (W) bulk layer 220b must be large as shown in fig. 2 (c). However, in this case, although the resistivity is improved, the Gap-fill (Gap-fill) characteristic and the junction characteristic may be relatively deteriorated. Further, since the CMP process is performed later, as shown in (D) of fig. 2, a defect D such as a seam (seam) or void (void) may occur on the upper surface of the tungsten bulk layer.
In order to solve the problem, in the present invention, a crystalline transition layer is interposed to enable a grain size of a tungsten bulk layer to be changed between process steps of depositing the tungsten bulk layer, and thus a resistivity improvement effect can be expected without a defect problem after a CMP process.
Referring to (a) of fig. 2, the semiconductor device may include: a substrate 100 having a groove; a nucleation layer 210 containing tungsten (W) and formed on an inner wall of the groove; a first tungsten bulk layer 220 formed on the nucleation layer 210 to partially fill the inside of the groove; a crystalline transition layer 230 formed on the first tungsten bulk layer 220; and a second tungsten bulk layer 240 having a grain size relatively smaller than that of the first tungsten bulk layer 220 and formed on the crystalline transition layer 230 to fill the inside of the groove entirely.
In particular, a substrate processing method for manufacturing a semiconductor device may load a substrate 100 having a groove into a process chamber. A nucleation layer 210 comprising tungsten (W) may then be formed on the inner walls of the recess.
As an example, the nucleation layer 210 may be formed by an Atomic Layer Deposition (ALD) method in which source gases, purge gases, reaction gases, etc. are supplied on the substrate. The ald method is not only applicable to a time division method in which deposition is performed by discontinuously supplying source gases, purge gases, reaction gases, and the like into a chamber in which the substrate 100 is disposed according to time, but also applicable to a space division method in which deposition is performed by sequentially moving the substrate in a system in which the source gases, the purge gases, the reaction gases, and the like are continuously supplied while spatially separating them.
The nucleation layer 210 may be a WF6Gas and B2H6The gases are alternately supplied into the process chamber. Here, H may be added in addition to the gas in performing the process of forming the nucleation layer 2102Gas is selectively supplied into the chamber.
A tungsten-preventing layer (not shown) may also be formed prior to forming the nucleation layer 210. The tungsten barrier layer prevents diffusion of tungsten within the substrate, for example, using sequential deposition of Ti/TiN or in addition sequential deposition of metal and nitride layers.
Then, a first tungsten bulk layer 220 partially filling the inside of the groove may be formed on the nucleation layer 210. As an example, the first tungsten bulk layer 220 may be formed using a Chemical Vapor Deposition (CVD) process, and may also be formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD). Will be at WF6Gas and H2A selected one of the gases or a mixture of these gases is supplied into the chamber, and a first tungsten bulk layer 220 may be formed on the nucleation layer 210.
Unlike the past, the first tungsten bulk layer 220 fills only a portion of the inside of the groove, and then the crystalline transformation layer 230 may be formed on the first tungsten bulk layer 220. The crystal conversion layer 230 is formed before the opening of the recess region is completely blocked by the first tungsten bulk layer 220. For example, the crystalline transition layer 230 may be formed before the width inside the groove region is filled with the 1/2-2/3 region by the first tungsten bulk layer 220. Here, the width refers to a distance between side walls of the groove, and in the case where the side walls of the groove are inclined, the width refers to a distance between side walls of the uppermost portion of the groove. That is, the crystal transition layer 230 is introduced before the central portion of the recess region is filled first, and the central portion of the recess region is densely filled with a film having a small grain size, so that defects occurring at the central portion of the recess region can be minimized.
The crystal conversion layer 230 may have
To
The thickness range of (a). If, the thickness of the crystalline transition layer 230 is less than
In the case of (2), the grain size of the second tungsten bulk layer 240 to be deposited thereafter is not changed. On the contrary, if greater than
The grain size and surface roughness of the second tungsten bulk layer 240 are hardly changed and thus the thickness of the transcrystalline layer 230 can be set
To
On the other hand, the crystal conversion layer 230 may be formed using the same method as the method of forming the nucleation layer 210, i.e., an atomic layer deposition method (ALD). As an example, WF is defined6Gas and B2H6Gas is alternately supplied into the chamber toA crystalline transition layer 230 is formed on the first tungsten bulk layer 220.
As another example, the crystalline conversion layer 230 may be formed in two processes. In the connection of WF6Gas and B2H6After alternately supplying gas into the chamber to form the crystal transition layer 230, WF is applied6Gas and SiH4The crystal conversion layer 230 may be formed by alternately supplying the gases continuously into the chamber. In summary, WF is defined6Gas and B2H6After the gas is alternately supplied into the chamber to form the crystal transition layer 230, the supply of the gas B is interrupted2H6Gas supply in which SiH is continuously supplied4Gas, or simultaneous supply of B2H6Gas and SiH4The crystal transition layer 230 may be formed while the gas is being formed. Here, SiH is increased4The gas can further have an effect of more easily guiding the change in the grain size of the second tungsten bulk layer 240.
On the other hand, in the embodiment, H may be added in addition to the supplied gas on the way of performing the process of forming the crystal conversion layer 2302Gas is supplied within the chamber. H2The gas may be supplied with WF as a source gas at the beginning6The gas may be continuously supplied until the moment when the deposition process of the crystal conversion layer 230 is finished, or may be intermittently supplied at every step of supplying the gas. Said H2The gas prevents oxidation of the tungsten film and the flow rate of each process supply gas is kept constant, thereby shortening the gas stabilization time and further shortening the process time.
Finally, in order to fill the inside of the groove completely, a second tungsten bulk layer 240 having a relatively smaller grain size than the first tungsten bulk layer 220 may be formed on the crystalline transformation layer 230. The second tungsten bulk layer 240 may be formed by performing the same process as the first tungsten bulk layer 220. As an example, WF is defined6Gas and H2Gas is supplied into the chamber to form a second tungsten bulk layer 240 on the crystalline transition layer 230, thereby completely filling the recess.
After the second tungsten bulk layer 240 is formed, a cmp (chemical Mechanical polishing) process is performed after the substrate 100 is removed from the process chamber, and a portion of the layer including tungsten formed above the uppermost surface of the substrate 100 is etched and removed.
Hereinafter, experimental examples for aiding understanding of the present invention will be described with reference to the accompanying drawings. However, the following examples are only for the understanding of the present invention, and the present invention should not be limited only by the following experimental examples.
Experimental example 1
As a comparative example sample having a tungsten bulk layer manufactured by a conventional substrate processing method, B2H6Gas and WF6Gas supply to form a nucleation layer on a wafer substrate followed by supply of WF6Gas and H2Gas forms
A tungsten bulk layer of thickness.
Experimental example 2
As a sample for comparison with experimental example 1, a nucleation layer and a tungsten bulk layer were formed in the same manner as in experimental example 1. Thereafter, supply B2H6Gas and WF6Gas forms on the tungsten bulk layer
A crystalline conversion layer of thickness.
Experimental example 3
As a sample for comparison with experimental example 1 and experimental example 2, a nucleation layer and a tungsten bulk layer were formed in the same manner as in experimental example 2. Thereafter, in place of B2H6Gas supply SiH4Gas and WF6Gas, formed on the tungsten bulk layer
A crystalline conversion layer of thickness.
Experimental example 4
The nucleation layer, the tungsten bulk layer, and the crystal transition layer were formed in the same manner as in experimental example 2. Thereafter, WF is supplied6Gas and H2Gas is additionally formed on the crystalline conversion layer
A tungsten bulk layer of thickness.
Experimental example 5
As a sample for comparison with experimental example 4, a nucleation layer, a tungsten bulk layer, and a crystal transition layer were formed in the same manner as in experimental example 3. Thereafter, WF is supplied6Gas and H2Gas, additionally formed on the crystalline conversion layer
A tungsten bulk layer of thickness.
Here, the tungsten bulk layer was deposited under a vacuum of 300torr, and the kind of gas of the crystal conversion layer and the surface and cross-sectional microstructure before/after deposition of the crystal conversion layer were compared by Scanning Electron Microscope (SEM) analysis.
Fig. 3 is a picture of analyzing a minute structure of a sample of a semiconductor device manufactured by the substrate processing method of the experimental example of the present invention with a scanning electron microscope.
The resistivity and RMS values of the experimental samples were comparatively analyzed. Table 1 below collates the physical properties of the individual samples.
TABLE 1
Referring to fig. 3, it can be confirmed that: the conditions of experimental examples 1 to 3 were not changed much. On the contrary, in the case of experimental example 4, if B is used2H6Gas and WF6When the tungsten bulk layer is formed after the gas forms the crystal transition layer, new crystal grains grow, and thus the crystal grain size of the upper layer portion becomes small. Then, it can be confirmed that: the situation of experiment example 5 is that if SiH is used4Gas and WF6Forming a tungsten bulk layer after forming a crystal transition layer by the gas, and then forming a tungsten bulk layer on the existing crystal grainsFurther growth is promoted, and therefore, the grain size of the upper layer portion becomes large.
Referring to table 1, it was confirmed that there was no significant change in experimental examples 1 to 3, as in the fine structure results of the respective samples. In contrast, in the case of experimental example 4, the resistivity value was increased to 11.0 μ Ω · cm and the surface roughness value was reduced to
Further, in the case of experimental example 5, the resistivity value was reduced to 10.1 μ Ω · cm, but the value of the surface roughness was increased to
It was confirmed that the values of the resistivity and the surface roughness can be controlled according to the kind of gas forming the crystalline conversion layer.
On the other hand, in the experimental example, samples were manufactured in the same manner as the sample of experimental example 4, in which the samples were manufactured while varying the thickness of each of the crystalline conversion layers, and the resistivity and the RMS value of each were comparatively analyzed. The physical properties of each sample are collated in Table 2 below. In the following table, experimental example 6 was conducted using B by a CVD process without a transcrystalline layer2H6Gas and WF6Gas formation
A sample of a tungsten bulk layer of thickness; examples 7 to 10 are for formation
The first tungsten block layer with the thickness is followed by
After the crystalline conversion layer was formed, a second tungsten bulk layer was formed. Here, for the total thickness of the samples of experimental example 7 to experimental example 10, the thickness of the second tungsten bulk layer was adjusted to be the same as that of the sample of experimental example 6.
TABLE 2
Referring to Table 2, in the case of Experimental example 6, the resistivity was at the lowest of 8.9. mu. Ω. cm, and the surface Roughness (RMS) was at the highest
In contrast, in the case of experimental examples 7 to 10 in which the crystalline conversion layer was inserted, the resistivity was improved as compared with experimental example 6, but the value of the surface roughness was reduced to about
In particular, as the thickness of the crystalline conversion layer increases, the resistivity gradually increases, while the value of the surface roughness remains at a similar level. Thus, it was confirmed that: the thickness of the crystalline conversion layer can be formed
To
Is preferably formed in consideration of resistivity
Hereinafter, the effect of improving the resistivity can be obtained without the problem of defects after the CMP process.
In addition, examples 11 to 14 formed
A tungsten bulk layer of thickness. Thereafter, supply B2H6Gas formation on tungsten bulk layer
A crystal transition layer of thickness, followed by a continuous supply of SiH4Gas in utilizing B2H6On the formed crystalline conversion layer respectively form
A crystalline conversion layer of thickness. Then, after utilizing the SiH4A tungsten bulk layer is additionally formed on the formed crystalline transition layer
Samples of the total thickness target.
TABLE 3
Referring to table 3, it was confirmed that: with the utilization of SiH4The thickness of the formed crystal conversion layer is increased, the resistivity is improved from 10.4 mu omega cm to 10.8 mu omega cm, and the value of the surface roughness is changed from
Is reduced to
In addition, it was confirmed that: using a crystal conversion layer forming a two-layer structure (separately supplied B) as compared with a sample using a single-layer crystal conversion layer2H6Gas and SiH4A crystal transition layer formed continuously while being gas) is controlled so as to reduce the surface roughness while reducing the resistivity. Thus, it is determined that: in the case where the crystal conversion layer is controlled to have a two-layer structure, an effect can be obtained in which both the resistivity and the surface roughness characteristics having characteristics opposite to each other can be controlled.
The present invention has been made in view of the above problems, and it is an object of the present invention to provide a substrate processing method which can prevent defects such as seams and voids from being generated in a crystal conversion layer and has a low resistivity. On the other hand, a NAND device having a cop (cell On peri) structure using tungsten metal as a lower wiring can be realized by the above substrate processing method.
The invention has been described with reference to the embodiments shown in the drawings, which are intended to be illustrative only, and that various modifications and equivalent other embodiments will be apparent to those skilled in the art. Accordingly, the true technical scope of the present invention should be defined by the technical idea within the scope of the claims.
Claims (14)
1. A method of processing a substrate, comprising the steps of:
loading the substrate having the groove into the chamber;
forming a nucleation layer containing tungsten on the inner wall of the groove;
forming a first tungsten bulk layer on the nucleation layer to partially fill the interior of the groove;
forming a crystalline conversion layer on the first tungsten bulk layer; and
and forming a second tungsten block body layer with a grain size relatively smaller than that of the first tungsten block body layer on the crystal conversion layer so as to completely fill the inside of the groove.
2. The substrate processing method according to claim 1,
the step of forming the crystalline conversion layer includes:
will WF6Gas and B2H6Supplying a gas into the chamber to form the crystalline conversion layer.
3. The substrate processing method according to claim 2,
the step of forming the crystalline conversion layer includes:
in the connection of WF6Gas and B2H6After the step of supplying gas into the chamber to form the crystal transition layer, WF is supplied6Gas and SiH4A step of continuously supplying gas into the chamber to form the crystal conversion layer.
4. The substrate processing method according to claim 2 or 3,
the step of forming the crystalline conversion layer is,
in addition to the source gas, H2A step of supplying a gas into the chamber to form the crystal conversion layer.
5. The substrate processing method according to claim 1,
the step of forming the nucleation layer, the step of forming the first tungsten bulk layer, the step of forming the crystalline conversion layer, and the step of forming the second tungsten bulk layer are steps formed by an in-situ process within the chamber.
6. The substrate processing method according to claim 1,
the crystal conversion layer has
To
The thickness range of (a).
7. The substrate processing method according to claim 1,
the step of forming the crystalline conversion layer is,
the crystal conversion layer is formed before the opening of the recess region is blocked by the first tungsten bulk layer.
8. The substrate processing method according to claim 1,
the step of forming the crystalline conversion layer is,
the crystalline conversion layer is formed before the opening of the groove region is blocked by the first tungsten bulk layer in the region 1/2 to 2/3.
9. The substrate processing method according to claim 1,
the step of forming the nucleation layer is,
in the connection of WF6Gas and B2H6Gas is supplied into the chamber to form the nucleation layer.
10. The substrate processing method according to claim 1,
the step of forming the first tungsten bulk layer is,
will WF6Gas and H2Gas is supplied into the chamber to form the first tungsten bulk layer.
11. The substrate processing method according to claim 1,
a step of forming the second tungsten bulk layer,
will WF6Gas and H2Gas is supplied into the chamber to form the second tungsten bulk layer.
12. A semiconductor device, comprising:
a substrate having a groove;
a nucleation layer containing tungsten and formed on an inner wall of the groove;
a first tungsten bulk layer formed on the nucleation layer to partially fill the inside of the groove;
a crystalline conversion layer formed on the first tungsten bulk layer; and
a second tungsten bulk layer having a grain size relatively smaller than that of the first tungsten bulk layer and formed on the crystalline transformation layer to fill the inside of the groove entirely.
13. The semiconductor device according to claim 12,
the crystal conversion layer has
To
The thickness range of (a).
14. The semiconductor device according to claim 12,
the crystal conversion layer is formed by a crystalline silicon,
formed in the region 1/2-2/3 of the width inside the groove region.
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| KR1020200026024A KR20210111017A (en) | 2020-03-02 | 2020-03-02 | Method for treating substrate and the semiconductor device manufactured by using the same |
| KR10-2020-0026024 | 2020-03-02 |
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| TW202201749A (en) | 2022-01-01 |
| TWI771917B (en) | 2022-07-21 |
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