CN113342528A - Instruction processing method and processor - Google Patents
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- CN113342528A CN113342528A CN202110663097.4A CN202110663097A CN113342528A CN 113342528 A CN113342528 A CN 113342528A CN 202110663097 A CN202110663097 A CN 202110663097A CN 113342528 A CN113342528 A CN 113342528A
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Abstract
The invention discloses an instruction processing method and a processor, wherein the method comprises the following steps: determining a target working mode of a processor; when the target working mode is the first working mode, processing at least two different instructions to be executed each period; and when the target working mode is the second working mode, processing at least two same instructions to be executed every period, comparing the execution results of the at least two same instructions to be executed, and determining whether the abnormality occurs according to the execution results. The invention not only realizes the multiplexing of hardware resources and saves resources, but also can support two working modes in the same processor, and supports the dynamic switching of the modes, thereby improving the flexibility of the processor when processing instructions.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an instruction processing method and a processor.
Background
At present, when superscalar processing and fault attack resistance of a program instruction are realized, a microprocessor with a superscalar processing function and a microprocessor with a fault attack resistance function are often required to cooperate together to complete processing of the program instruction, so that not only is the economic cost increased, but also resource waste is caused. Therefore, the conventional microprocessor cannot realize superscalar processing of program instructions and fault attack resistance at the same time, so that the economic cost is increased and the resources are wasted.
Disclosure of Invention
The embodiment of the application aims to solve the technical problems that the existing microprocessor cannot realize superscalar processing of program instructions and fault attack resistance at the same time, so that the economic cost is increased and resources are wasted.
The embodiment of the application provides an instruction processing method, which comprises the following steps:
determining a target working mode of a processor;
when the target working mode is a first working mode, processing at least two different instructions to be executed each period;
and when the target working mode is a second working mode, processing at least two identical instructions to be executed every period, comparing the execution results of the at least two identical instructions to be executed, and determining whether an abnormality occurs according to the execution results.
In one embodiment, the step of determining the target operating mode of the processor comprises:
receiving a level signal;
and determining the target working mode according to the level signal.
In one embodiment, the step of determining the target operation mode according to the level signal includes:
when the level signal is a high level signal, determining that the target working mode is a first working mode;
and when the level signal is a low level signal, determining that the target working mode is a second working mode.
In an embodiment, when the target operating mode is the second operating mode, the step of processing at least two identical instructions to be executed each cycle, comparing execution results of the at least two identical instructions to be executed, and determining whether an exception occurs according to the execution results includes:
when the target working mode is a second working mode, decoding at least two identical instructions to be executed in each period, and comparing decoding results of the instructions to be executed;
when the decoding results are the same, executing at least two identical instructions to be executed;
comparing the execution results of at least two identical instructions to be executed, and determining whether an exception occurs according to the execution results.
In an embodiment, after the step of comparing the decoding results of the instructions to be executed, the method further includes:
and when the decoding results are different, determining that the instruction to be executed is abnormal.
In an embodiment, the step of comparing the execution results of at least two identical instructions to be executed and determining whether an exception occurs according to the execution results includes:
and when the execution results are different, determining that the instruction to be executed is abnormal.
In an embodiment, the step of comparing the execution results of at least two identical instructions to be executed and determining whether an exception occurs according to the execution results further includes:
and when the execution results are the same, determining that the to-be-executed instruction has no exception, and submitting the to-be-executed instruction.
In addition, to achieve the above object, the present invention also provides a processor, including:
the mode control module is used for determining a target working mode of the processor;
the processing module is used for processing at least two different instructions to be executed each period when the target working mode is the first working mode;
the processing module is further configured to, when the target operating mode is a second operating mode, process at least two identical instructions to be executed per cycle, compare execution results of the at least two identical instructions to be executed, and determine whether an exception occurs according to the execution results.
The technical scheme of the instruction processing method and the processor provided in the embodiment of the application has at least the following technical effects or advantages:
according to the method and the device, after the target working mode of the processor is determined, when the target working mode is the first working mode, at least two different instructions to be executed are processed every period, when the target working mode is the second working mode, at least two same instructions to be executed are processed every period, the execution results of the at least two same instructions to be executed are compared, and whether an exception occurs is determined according to the execution results.
Drawings
FIG. 1 is a flowchart illustrating a first exemplary embodiment of a method for processing instructions according to the present invention;
FIG. 2 is a flowchart illustrating a second embodiment of an instruction processing method according to the present invention;
FIG. 3 is a flowchart illustrating a third exemplary embodiment of a method for processing instructions according to the present invention;
FIG. 4 is a block diagram of a processor according to the present invention.
Detailed Description
For a better understanding of the above technical solutions, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It should be noted that, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that shown or described, and the instruction processing method is applied to a processor, and the processor processes the instructions by using the instruction processing method.
As shown in fig. 1, in a first embodiment of the present application, an instruction processing method of the present application includes the following steps:
step S210: a target operating mode of the processor is determined.
In this embodiment, the processor may specifically be a microprocessor, the target operating mode refers to different operating modes of the processor, the target operating mode includes two types, which are a first operating mode and a second operating mode, respectively, the first operating mode refers to a superscalar processing mode of the processor, and the second operating mode refers to a redundant processing mode of the processor, that is, the processor described in this embodiment has not only a superscalar processing function of an instruction but also a redundant processing function of the instruction, and the processor can perform dynamic switching between the superscalar processing mode and the redundant processing mode according to the processing requirement of the instruction, thereby implementing processing of the instruction.
Specifically, when the processor is switched to the superscalar processing mode or the processor is in the superscalar processing mode, the processor may extract two or more instructions to be executed, and then simultaneously process the two or more extracted instructions to be executed. In the superscalar processing mode, two or more instructions to be executed extracted by the processor are different instructions. For example, in superscalar processing mode, the processor fetches 3 instructions to be executed, which are a data receiving instruction, a data updating instruction, and a data encrypting instruction, respectively. Correspondingly, when the processor is switched to the redundant processing mode or is in the redundant processing mode, the processor extracts one instruction to be executed, and then processes the extracted instruction to be executed as two or more same instructions to be executed. For example, in the redundant processing mode, the processor fetches 1 instruction to be executed, the instruction to be executed is a data update instruction, and the processor decodes the data update instruction 3 times, that is, performs redundant decoding 2 times.
Step S220: and processing at least two different instructions to be executed each period when the target working mode is the first working mode.
In this embodiment, when the target operating mode after the processor switches the operating mode is the superscalar processing mode, the processor operates in the superscalar processing mode, and the processing of the instruction to be executed is performed according to the processing flow of instruction fetching, instruction decoding, instruction transmitting, instruction executing and instruction submitting every cycle.
Specifically, first, the processor fetches two or more different instructions to be executed per cycle, then parallel decoding is carried out on the extracted different instructions to be executed so as to identify the instruction type of each instruction to be executed, then each different instruction to be executed is written into an instruction transmitting queue, then the arbitration circuit selects two or more different to-be-executed instructions whose operands are ready to be completed from the instruction transmission queue to transmit in each cycle, and executes the transmitted two or more different to-be-executed instructions, because the instructions to be executed that are selected from the issue queue are out-of-order, resulting in out-of-order execution of the instructions to be executed during execution, after two or more different instructions to be executed are executed, the instructions are submitted, wherein the instruction submission is to pull the instructions to be executed which are executed out of order back to the order specified in the application program.
Step S230: and when the target working mode is a second working mode, processing at least two identical instructions to be executed every period, comparing the execution results of the at least two identical instructions to be executed, and determining whether an abnormality occurs according to the execution results.
In this embodiment, when the target operating mode after the processor switches the operating mode is the redundancy processing mode, the processor operates in the redundancy processing mode, and the processing of the instruction to be executed is performed according to the processing flow of instruction extraction, instruction decoding, decoding result judgment, instruction transmission, instruction execution, instruction result judgment and instruction submission every cycle.
Specifically, the processor extracts one instruction to be executed per cycle, decodes the extracted instruction to be executed at least twice to identify the instruction type of the instruction to be executed, or decodes the extracted instruction to be executed as at least two identical instructions to be executed in parallel to identify the instruction type of each instruction to be executed, determines whether each decoding result is abnormal, and if the decoding result is abnormal, triggers the abnormal processing of the decoding result and performs the abnormal processing on the instruction to be executed with the abnormal decoding result; if the decoding result is normal, writing the instruction to be executed into an instruction transmitting queue, then selecting an operand from the instruction transmitting queue by an arbitration circuit every period, transmitting the instruction to be executed to the instruction to be executed, wherein the operand is ready to be completed, or the instruction to be executed is understood to be transmitted as at least two same instructions to be executed together, executing the transmitted instruction to be executed twice, or the transmitted instruction to be executed is understood to be executed in parallel as at least two same instructions to be executed, judging whether each instruction result is abnormal, if the execution result is abnormal, triggering the abnormal processing of the execution result, and performing the abnormal processing on the instruction to be executed with the abnormal execution result; if the execution result is normal, an instruction commit is performed.
As shown in fig. 4, fig. 4 is a schematic structural diagram of a processor according to the present invention, in the diagram, mode control represents a mode control module, instruction extraction represents an instruction extraction module, instruction decoding 1 and instruction decoding 2 both represent instruction decoding modules, decision 1 represents a first judgment module, which is used for judging a decoding result, instruction transmission represents an instruction transmission module, instruction execution 1 and instruction execution 2 both represent instruction execution modules, and instruction submission represents an instruction submission module. From fig. 4 it can be determined that the processor processes two different instructions to be executed in superscalar processing mode and two identical instructions to be executed in redundant processing mode per cycle. The number of the instruction extracting modules and the number of the instruction executing modules provided in fig. 4 are both two, and it should be noted that the number of the instruction decoding modules and the number of the instruction executing modules of the present invention are not limited to two, and may also be three or more, and specifically may be preset according to actual requirements.
Specifically, if the mode control module determines that the target working mode of the processor is the superscalar processing mode, the processor is switched to the superscalar processing mode, and both the first judgment module and the second judgment module are shielded, namely do not participate in the working. The instruction extracting module extracts two different instructions per cycle and transmits the two different instructions to the instruction decoding module, the two instruction decoding modules decode the two different instructions in parallel and transmit the two different instructions to the instruction transmitting module, the instruction transmitting module transmits the two different instructions to the instruction executing module per cycle, the instruction executing module executes the two different instructions in parallel, and the instruction submitting module submits the two different instructions per cycle.
If the mode control module determines that the target working mode of the processor is the redundancy processing mode, the processor is switched to the redundancy processing mode, and the first judgment module and the second judgment module both participate in working. The instruction extracting module extracts one instruction per cycle and simultaneously transmits the instruction to the two instruction decoding modules, the two instruction decoding modules decode the instruction in parallel and transmit the decoded instruction to the instruction transmitting module, wherein the first judging module compares two decoding results, and if the two decoding results are inconsistent, an alarm signal is output; and then, the instruction transmitting module transmits one instruction to the two instruction executing modules in each period, the two instruction executing modules execute the transmitted instruction in parallel, the second judging module compares the two executing results, if the two executing results are inconsistent, an alarm signal is output, and the instruction submitting module submits one or two instructions in each period according to the actual condition.
According to the technical scheme, after the target working mode of the processor is determined, when the target working mode is the first working mode, at least two different instructions to be executed are processed every period, when the target working mode is the second working mode, at least two same instructions to be executed are processed every period, the execution results of the at least two same instructions to be executed are compared, and whether an exception occurs is determined according to the execution results.
As shown in fig. 2, in the second embodiment of the present application, based on the first embodiment, the step S210 includes the following steps:
step S211: a level signal is received.
In this embodiment, the level signal is a mode control signal of the processor, and the level signal is generated by a mode control register. Before processing an instruction to be executed generated by an application program, a processor configures a mode control register through the application program, and the application program is supposed to comprise a general code and a safety code; the security code refers to a code that needs security protection in an application program, such as an encryption algorithm, and the general code refers to a code that does not need security protection, such as an AI inference algorithm. After the application program is run, an instruction to be executed generated by a general code in the application program needs to be processed in a superscalar processing mode through a processor, an instruction to be executed generated by a safety code in the application program needs to be processed in a redundant processing mode through the processor, and after a mode control register is configured according to the instruction to be executed generated by the safety code and the instruction to be executed generated by the general code in the application program, the mode control register can be generated according to which code the instruction to be executed is processed by the processor every period before the processor processes the instruction to be executed, so that a specific level signal is further sent to the processor.
Specifically, if the instruction to be executed to be processed by the processor per cycle is generated by a general-purpose code, the level signal sent to the processor is a high level signal, and then the level signal received by the processor is a high level signal; if the instruction to be executed to be processed by the processor per cycle is generated by the safety code, the level signal sent to the processor is a low level signal, and then the level signal received by the processor is a low level signal.
Step S212: and determining the target working mode according to the level signal.
In this embodiment, after receiving the level signal, the processor further determines whether its own target operation mode is the superscalar processing mode or the redundancy processing mode according to which level signal the level signal is, that is, if the received level signal is a high level signal, the target operation mode is determined to be the superscalar processing mode and the operation mode is set to be the superscalar processing mode, and if the received level signal is a low level signal, the target operation mode is determined to be the redundancy processing mode and the operation mode is set to be the redundancy processing mode.
According to the technical scheme, the dynamic switching control of the working modes of the processor is realized.
As shown in fig. 3, in the third embodiment of the present application, based on the first embodiment, step S230 includes the following steps:
step S231: when the target working mode is a second working mode, decoding at least two same instructions to be executed in each period, and comparing decoding results of the instructions to be executed.
In this embodiment, the processor processes the instruction to be executed according to the redundant processing mode, wherein after the same instruction to be executed is decoded at least twice, each decoding result is compared, and whether to perform subsequent operation on the instruction to be executed is determined according to the comparison result.
Step S232: and when the decoding results are the same, executing at least two identical instructions to be executed.
In this embodiment, if the decoding results of the instructions to be executed are all determined to be the same, the instruction transmission-instruction execution operation is continued.
Step S233: comparing the execution results of at least two identical instructions to be executed, and determining whether an exception occurs according to the execution results.
In this embodiment, after the decoding results are determined to be the same, instruction transmission and instruction execution continue, after the instruction execution is completed, at least two execution results continue to be compared, if the execution results are determined to be different, it is determined that the instruction to be executed is abnormal, an alarm signal about the execution result is generated, it is prompted that the current instruction to be executed is abnormal, the execution results during the instruction execution are inconsistent, and the instruction to be executed continues to be executed. If the execution results are the same, determining that the instruction to be executed is not abnormal, and continuing to perform subsequent operations, namely submitting the instruction to be executed.
Step S234: and when the decoding results are different, determining that the instruction to be executed is abnormal.
In this embodiment, if it is determined that the decoding results of the instructions to be executed are different, it is determined that the current instruction to be executed is abnormal, and an alarm signal related to the decoding result is generated, which indicates that the current instruction to be executed is abnormal, so that the decoding results are inconsistent when the instruction is decoded, and the instruction to be executed is stopped from continuing to execute downwards.
Further, the present application also provides a processor, including:
the mode control module is used for determining a target working mode of the processor;
the processing module is used for processing at least two different instructions to be executed each period when the target working mode is the first working mode;
the processing module is further configured to, when the target operating mode is a second operating mode, process at least two identical instructions to be executed per cycle, compare execution results of the at least two identical instructions to be executed, and determine whether an exception occurs according to the execution results.
The specific implementation of the processor of the present invention is substantially the same as the embodiments of the instruction processing method described above, and will not be described herein again.
Further, as shown in fig. 4, fig. 4 is an architectural schematic diagram of the processor of the present invention, in the diagram, mode control represents a mode control module, instruction extraction represents an instruction extraction module, both instruction decoding 1 and instruction decoding 2 represent instruction decoding modules, decision 1 represents a first judgment module, which is used for judging a decoding result, instruction transmission represents an instruction transmission module, both instruction execution 1 and instruction execution 2 represent instruction execution modules, and instruction submission represents an instruction submission module. Specifically, the processing module comprises an instruction extracting module, at least two instruction decoding modules, a first judging module, an instruction transmitting module, at least two instruction executing modules, a second judging module and an instruction submitting module.
The processor is switched to a superscalar processing mode, and the first judgment module and the second judgment module are both shielded, namely do not participate in work. The instruction extracting module extracts two different instructions per cycle and transmits the two different instructions to the instruction decoding module, the two instruction decoding modules decode the two different instructions in parallel and transmit the two different instructions to the instruction transmitting module, the instruction transmitting module transmits the two different instructions to the instruction executing module per cycle, the instruction executing module executes the two different instructions in parallel, and the instruction submitting module submits the two different instructions per cycle.
The processor is switched to a redundancy processing mode, and the first judging module and the second judging module both participate in working. The instruction extracting module extracts one instruction per cycle and simultaneously transmits the instruction to the two instruction decoding modules, the two instruction decoding modules decode the instruction in parallel and transmit the decoded instruction to the instruction transmitting module, wherein the first judging module compares two decoding results, and if the two decoding results are inconsistent, an alarm signal is output; and then, the instruction transmitting module transmits one instruction to the two instruction executing modules in each period, the two instruction executing modules execute the transmitted instruction in parallel, the second judging module compares the two executing results, if the two executing results are inconsistent, an alarm signal is output, and the instruction submitting module submits one or two instructions in each period according to the actual condition.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. An instruction processing method, comprising:
determining a target working mode of a processor;
when the target working mode is a first working mode, processing at least two different instructions to be executed each period;
and when the target working mode is a second working mode, processing at least two identical instructions to be executed every period, comparing the execution results of the at least two identical instructions to be executed, and determining whether an abnormality occurs according to the execution results.
2. The method of claim 1, wherein the step of determining a target operating mode of the processor comprises:
receiving a level signal;
and determining the target working mode according to the level signal.
3. The method of claim 2, wherein said step of determining said target operating mode based on said level signal comprises:
when the level signal is a high level signal, determining that the target working mode is a first working mode;
and when the level signal is a low level signal, determining that the target working mode is a second working mode.
4. The method according to claim 3, wherein the step of processing at least two identical instructions to be executed each cycle and comparing the execution results of the at least two identical instructions to be executed when the target operation mode is the second operation mode, and determining whether an exception occurs according to the execution results comprises:
when the target working mode is a second working mode, decoding at least two identical instructions to be executed in each period, and comparing decoding results of the instructions to be executed;
when the decoding results are the same, executing at least two identical instructions to be executed;
comparing the execution results of at least two identical instructions to be executed, and determining whether an exception occurs according to the execution results.
5. The method of claim 4, wherein the step of comparing the decoded result of each of the instructions to be executed further comprises:
and when the decoding results are different, determining that the instruction to be executed is abnormal.
6. The method according to claim 4, wherein the step of comparing the execution results of at least two identical instructions to be executed and determining whether an exception occurs according to the execution results comprises:
and when the execution results are different, determining that the instruction to be executed is abnormal.
7. The method according to claim 4, wherein the step of comparing the execution results of at least two identical instructions to be executed and determining whether an exception occurs according to the execution results further comprises:
and when the execution results are the same, determining that the to-be-executed instruction has no exception, and submitting the to-be-executed instruction.
8. A processor, comprising:
the mode control module is used for determining a target working mode of the processor;
the processing module is used for processing at least two different instructions to be executed each period when the target working mode is the first working mode;
the processing module is further configured to, when the target operating mode is a second operating mode, process at least two identical instructions to be executed per cycle, compare execution results of the at least two identical instructions to be executed, and determine whether an exception occurs according to the execution results.
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| CN1871582A (en) * | 2003-10-24 | 2006-11-29 | 罗伯特·博世有限公司 | Method and device for operand processing in a processor unit |
| DE102006004986A1 (en) * | 2005-12-22 | 2007-07-05 | Robert Bosch Gmbh | Method for switching between safety and performance operating mode in processor system with two execution units, involves initialization of set of execution units in same processing cycle to transmit instructions |
| CN106465404A (en) * | 2014-02-06 | 2017-02-22 | 优创半导体科技有限公司 | Method and apparatus for enabling a processor to generate pipeline control signals |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1871582A (en) * | 2003-10-24 | 2006-11-29 | 罗伯特·博世有限公司 | Method and device for operand processing in a processor unit |
| DE102006004986A1 (en) * | 2005-12-22 | 2007-07-05 | Robert Bosch Gmbh | Method for switching between safety and performance operating mode in processor system with two execution units, involves initialization of set of execution units in same processing cycle to transmit instructions |
| CN106465404A (en) * | 2014-02-06 | 2017-02-22 | 优创半导体科技有限公司 | Method and apparatus for enabling a processor to generate pipeline control signals |
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