CN113325919A - Clock compensation method and device - Google Patents

Clock compensation method and device Download PDF

Info

Publication number
CN113325919A
CN113325919A CN202110704345.5A CN202110704345A CN113325919A CN 113325919 A CN113325919 A CN 113325919A CN 202110704345 A CN202110704345 A CN 202110704345A CN 113325919 A CN113325919 A CN 113325919A
Authority
CN
China
Prior art keywords
iteration
clock
frequency offset
current
sampling time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110704345.5A
Other languages
Chinese (zh)
Other versions
CN113325919B (en
Inventor
孔丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou H3C Technologies Co Ltd
Original Assignee
Hangzhou H3C Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou H3C Technologies Co Ltd filed Critical Hangzhou H3C Technologies Co Ltd
Priority to CN202110704345.5A priority Critical patent/CN113325919B/en
Publication of CN113325919A publication Critical patent/CN113325919A/en
Application granted granted Critical
Publication of CN113325919B publication Critical patent/CN113325919B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The application provides a clock compensation method and a device, comprising the following steps: acquiring a clock signal output by the electronic equipment at the current sampling moment; inputting the time mark of the current sampling time into a trained frequency offset prediction model so as to output a frequency offset prediction value corresponding to the current sampling time by the frequency offset prediction model; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock difference actual value corresponding to at least one historical sampling moment before the standard clock is lost; determining a frequency offset predicted value corresponding to the current sampling time based on the frequency offset predicted value corresponding to the current sampling time, the recorded frequency offset predicted value corresponding to each sampling time from the loss of the standard clock to the current sampling time, and a target clock offset accumulated value obtained when the training of the prediction model is completed; and compensating the clock signal output by the electronic equipment at the current sampling moment by adopting the clock difference predicted value corresponding to the current sampling moment, thereby realizing clock compensation.

Description

Clock compensation method and device
Technical Field
The present application relates to the field of communications, and in particular, to a clock compensation method and apparatus.
Background
Clock signals sent by the electronic equipment can change along with time, so that the clock of the electronic equipment is inaccurate. In the prior art, an electronic device usually receives a standard clock, and then uses the standard clock to correct the clock of the electronic device.
However, when the standard clock is lost, the clock signal output by the electronic device needs to be compensated in order to keep the clock difference between the clock signal output by the electronic device and the standard clock signal within a preset interval. Therefore, how to compensate the clock signal output by the electronic device becomes an urgent problem to be solved.
Disclosure of Invention
In view of this, the present application provides a clock compensation method and apparatus for compensating a clock signal output by an electronic device after a standard clock of the electronic device is lost, so that a clock difference between the clock signal output by the electronic device and the standard clock signal is within a preset error range.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, there is provided a clock compensation method, which is applied to an electronic device, where the electronic device is configured to, after a standard clock is lost and before the standard clock is recovered, the method includes:
acquiring a clock signal output by the electronic equipment at the current sampling moment;
inputting a time mark of the current sampling time into a trained frequency offset prediction model so as to output a frequency offset prediction value corresponding to the current sampling time by the frequency offset prediction model; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock error actual value corresponding to at least one historical sampling moment before the loss of the standard clock, and the clock error actual value is the phase difference between the clock signal output by the electronic equipment and the standard clock signal;
determining a frequency deviation predicted value corresponding to the current sampling time based on the frequency deviation predicted value corresponding to the current sampling time, the recorded frequency deviation predicted value corresponding to each sampling time from the loss of the standard clock to the current sampling time, and a target clock difference accumulated value obtained when the training of the frequency deviation prediction model is completed;
and compensating the clock signal output by the electronic equipment at the current sampling time by adopting the clock difference predicted value corresponding to the current sampling time.
Optionally, the frequency offset prediction model and the target clock error cumulative value are trained through a preset recursive algorithm:
circularly executing the following iteration steps until a preset iteration condition is met;
determining a gain vector of the iteration based on the covariance matrix obtained by the last iteration and the moment identifier of the sampling moment corresponding to the iteration;
determining the model parameters of the iteration based on the model parameters of the previous iteration, the clock error actual value corresponding to the iteration and the gain vector obtained by the iteration;
and determining the clock error accumulated value corresponding to the iteration based on the model parameters of the iteration and the clock error accumulated value obtained by the last iteration.
Optionally, after determining the gain vector of the current iteration, the method further includes:
and determining and recording the covariance matrix of the iteration based on the gain vector obtained by the iteration and the covariance matrix obtained by the last iteration, so as to determine the gain vector of the next iteration through the covariance matrix of the iteration during the next iteration.
Optionally, the initial values of the model parameters of the frequency offset prediction model and the initial values of the covariance matrix are calculated from the time identifiers of the two historical sampling times and the frequency offset samples constructed by the clock difference actual values of the two historical sampling times.
Optionally, the determining the clock difference accumulated value corresponding to the current iteration based on the model parameter of the current iteration and the clock difference accumulated value obtained by the previous iteration includes:
determining the accumulated clock error correction amount of the iteration based on the model parameter of the iteration, the model parameter of the last iteration and the time identification of the historical sampling time corresponding to the iteration;
and determining the clock error accumulated value of the current iteration based on the clock error accumulated value obtained by the last iteration, the model parameter obtained by the current iteration and the accumulated clock error correction quantity obtained by the current iteration.
Optionally, the preset recursive algorithm is an RLS algorithm.
According to a second aspect of the present application, there is provided a clock compensation apparatus, which is applied to an electronic device, where the electronic device is configured to, after a standard clock is lost and before the standard clock is recovered, the apparatus includes:
the acquisition unit is used for acquiring a clock signal output by the electronic equipment at the current sampling moment;
the prediction unit is used for inputting the time mark of the current sampling time into the trained frequency offset prediction model so as to output a frequency offset prediction value corresponding to the current sampling time by the frequency offset prediction model; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock error actual value corresponding to at least one historical sampling moment before the loss of the standard clock, and the clock error actual value is the phase difference between the clock signal output by the electronic equipment and the standard clock signal;
a determining unit, configured to determine a frequency offset predicted value corresponding to the current sampling time based on the frequency offset predicted value corresponding to the current sampling time, the recorded frequency offset predicted values corresponding to sampling times from when the standard clock is lost to the current sampling time, and a target clock offset accumulated value obtained when training of the frequency offset prediction model is completed;
and the compensation unit is used for compensating the clock signal output by the electronic equipment at the current sampling moment by adopting the clock difference predicted value corresponding to the current sampling moment.
Optionally, the apparatus further comprises a training unit;
the training unit is used for circularly executing the following iteration steps until a preset iteration condition is met when the frequency offset prediction model and the target clock error accumulated value are trained through a preset recursive algorithm; determining a gain vector of the iteration based on the covariance matrix obtained by the last iteration and the moment identifier of the sampling moment corresponding to the iteration; determining the model parameters of the iteration based on the model parameters of the previous iteration, the clock error actual value corresponding to the iteration and the gain vector obtained by the iteration; and determining the clock error accumulated value corresponding to the iteration based on the model parameters of the iteration and the clock error accumulated value obtained by the last iteration.
Optionally, the training unit is further configured to determine and record a covariance matrix of the current iteration based on the gain vector obtained by the current iteration and a covariance matrix obtained by the previous iteration after the gain vector of the current iteration is determined, so that the gain vector of the next iteration is determined through the covariance matrix of the current iteration during the next iteration.
Optionally, the initial values of the model parameters of the frequency offset prediction model and the initial values of the covariance matrix are calculated from the time identifiers of the two historical sampling times and the frequency offset samples constructed by the clock difference actual values of the two historical sampling times.
Optionally, when determining the clock difference accumulated value corresponding to the current iteration based on the model parameter of the current iteration and the clock difference accumulated value obtained by the previous iteration, the training unit is configured to determine the accumulated clock difference correction amount of the current iteration based on the model parameter of the current iteration, the model parameter of the previous iteration, and the time identifier of the historical sampling time corresponding to the current iteration; and determining the clock error accumulated value of the current iteration based on the clock error accumulated value obtained by the last iteration, the model parameter obtained by the current iteration and the accumulated clock error correction quantity obtained by the current iteration.
Optionally, the preset recursive algorithm is an RLS algorithm.
As can be seen from the above description, in the present application, the clock offset is converted into the frequency offset, and the change rule of the frequency offset with time is found by training the frequency offset prediction model, so that after the standard clock is lost, the frequency offset can be predicted by using the frequency offset prediction model, the predicted frequency offset is converted into the predicted clock offset, and the clock signal output by the electronic device after the standard clock is lost is compensated by using the predicted clock offset, thereby implementing clock compensation.
In addition, compared with other clock compensation methods (such as methods for compensating clocks by using a kalman filter algorithm), the clock compensation method for performing clock difference prediction based on frequency offset is lower in complexity, less in calculation amount during clock compensation, and less in system resource consumption.
Drawings
FIG. 1 is a flow chart of a method of clock compensation shown in an exemplary embodiment of the present application;
FIG. 2 is a diagram illustrating a hardware configuration of an electronic device according to an exemplary embodiment of the present application;
fig. 3 is a block diagram of a clock compensation apparatus according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
In the method, because the frequency deviation constructed by the clock difference between the clock signal output by the electronic equipment and the standard clock signal conforms to the mathematical distribution of a certain rule, a frequency deviation prediction model of the frequency deviation and the sampling moment is constructed firstly. And then training the constructed frequency deviation prediction model.
During training, the clock error actual value corresponding to each historical sampling time (i.e., the clock error actual value corresponding to each historical sampling time acquired before the standard clock is lost) serving as sample data can be converted into frequency offset corresponding to each historical sampling time, and then a frequency offset prediction model is trained by using a recursive algorithm and based on the frequency offset corresponding to each historical sampling time, so as to obtain a trained frequency offset prediction model. Because the clock difference comprises the phase difference between the clock signal of the electronic equipment and the standard clock signal, the clock difference is accumulated along with time, so that the clock difference generated by each iteration is accumulated during each iteration, and a target clock difference accumulated value accumulated during training is obtained after the frequency offset prediction model is trained.
After the standard clock is lost, the electronic device may input the time identifier of the current sampling time to the frequency offset prediction model to obtain the frequency offset prediction value. The electronic device may determine a clock difference corresponding to the current sampling time based on the frequency offset predicted value corresponding to the current sampling time, the frequency offset predicted value corresponding to each sampling time between the loss of the standard clock and the current sampling time, and the target clock difference accumulated value, and compensate the clock signal output by the electronic device at the current sampling time based on the clock difference at the current sampling time, so that the clock difference between the compensated clock signal and the standard clock signal is within a preset threshold, thereby realizing the compensation of the clock signal.
Because the clock offset is converted into the frequency offset and the change rule of the frequency offset along with the time is found, after the standard clock is lost, the frequency offset can be predicted by using the change rule, the predicted frequency offset is converted into the predicted clock offset, and the clock signal output by the electronic equipment after the standard clock is lost is compensated by using the predicted clock offset. Compared with a Kalman filtering algorithm for compensating the clock, the clock compensation method is lower in complexity, less in calculated amount and less in system resource consumption during clock compensation.
The embodiment of the application mainly comprises two parts, namely training of a frequency deviation prediction model and compensation of a clock signal output by electronic equipment by applying the frequency deviation prediction model after a standard clock is lost, and the clock compensation method provided by the application is introduced from the two parts respectively.
For the convenience of distinguishing model training from model application, the sampling time used in model training is referred to as historical sampling time (i.e. sampling time before loss of standard clock), the clock offset used is referred to as actual value of clock offset, and the frequency offset used is referred to as frequency offset sample. The sampling time used when the model is applied is directly used as the sampling time, the used clock difference is called a clock difference predicted value, and the used frequency offset is called a frequency offset predicted value.
1. Training of frequency offset prediction model
Before describing the training of the frequency offset prediction model, several concepts related to the present application will be described.
1) Clock error
The clock difference is a phase difference between a clock signal output by the electronic device and a standard clock signal. Furthermore, the clock difference corresponding to a certain sampling time is the phase difference between the clock signal output by the electronic device at the certain sampling time and the standard clock signal.
2) Frequency offset
In this application, the frequency offset represents an increase in clock difference between two adjacent sampling instants. Therefore, in the present application, the clock difference may be converted into a frequency offset.
For example, assume that the clock difference at the kth sampling instant is τkThe clock difference at the k-1 th sampling time is tauk-1Wherein k is an integer of 1 or more.
Let the time interval between the kth sampling instant and the kth-1 sampling instant be d.
Assume that the frequency offset at time k is assumed to be g k]Then, then
Figure BDA0003131579010000071
Where d is the time interval between the kth sampling instant and the sampling instant of the (k-1) (i.e., d is the sampling step size).
3) Time identification of sampling time
The time-of-day indication of the sampling time-of-day refers to a flag indicating a sampling time-of-day. For example, the time of day identification may be the number of sampling times. For example, the time of the 1 st sampling time is denoted by 1, the time of the 2 nd sampling time is denoted by 2, and the time of the k-th sampling time is denoted by k. The time identification of the sampling time is only exemplified here, and is not particularly limited.
The frequency offset changes along with the sampling time, and the change accords with a certain regular mathematical distribution. Therefore, in the present application, an initial frequency offset prediction model may be constructed first, and then the frequency offset constructed by the clock difference actual values corresponding to the historical sampling times acquired before the loss of the standard clock is utilized to train the frequency offset prediction model.
It should be noted that, since the clock offset includes a phase difference between a clock signal of the electronic device and a standard clock signal, the clock offset is accumulated over time, and therefore, in the present application, the clock offset is accumulated during each iterative training, and a target clock offset accumulated value accumulated during the training is obtained after the frequency offset prediction model is trained.
Therefore, the purpose of training the frequency deviation prediction model is to obtain the model parameters of the frequency deviation prediction model and the target clock error accumulated value.
In the embodiment of the present application, a preset recursive algorithm may be used to train the frequency offset prediction model and obtain the target clock error cumulative value. The preset Recursive algorithm may be an RLS (Recursive Least Square) algorithm, or may be another Recursive algorithm, which is only described by way of example and is not specifically limited.
The following describes in detail "training the frequency offset prediction model by the preset recursive algorithm" through steps a1 to A3.
Before describing steps a 1-A3, how to determine the initial values of the model parameters, the covariance matrix, and the initial clock difference accumulation values for the following iterations are described.
Assume that the training samples are: clock error actual value tau of 0 th historical sampling time01 st clock error actual value tau at historical sampling time1… actual value of clock difference at kth historical sampling timek。
Suppose that the conversion formula of the frequency offset and the clock difference is:
Figure BDA0003131579010000081
wherein g [ k ]]And d is the time interval between the kth historical sampling moment and the (k-1) th historical sampling moment (i.e. d is the sampling step).
Therefore, the electronic device can form frequency offsets from the 1 st historical sampling time to the kth historical sampling time based on the clock difference actual values from the 0 th historical sampling time to the kth historical sampling time.
For example, the frequency offset sample at the 1 st historical sampling time is g [1], the frequency offset sample at the 2 nd historical sampling time is g [2], …, and the frequency offset sample at the kth historical sampling time is g [ k ].
Assuming that the frequency offset and the sampling time follow a linear function, a frequency offset model as shown below can be constructed in advance:
fest[k]＝θ1[k]+kθ2[k](ii) a (formula 1-1)
Wherein k is an independent variable and represents a time mark of the sampling time; f. ofest[k]Is a dependent variable, representing the frequency offset.
Wherein, theta1[k]And theta2[k]Model parameters representing the frequency offset model.
In calculating the initial value, in the conventional RLS recursive algorithm, the conventional way is to substitute a frequency offset sample of a historical sampling time into the formula, which results in the obtained θ1[k]And theta2[k]The initial values of (a) are not unique, resulting in inaccuracy of the trained model.
In the application, the frequency offset samples of two historical sampling moments before the loss of the standard clock are substituted into the formula, so that the only theta can be obtained1[k]And theta2[k]The initial value of (2) makes the trained model more accurate.
For example, the present application may sample g [1] of the 1 st historical sample time]2 nd history miningG 2 of sample time]Substituted into the above frequency offset model, i.e., (1, g 1)]) And (2, g [2]]) Substituting into the frequency deviation model to obtain theta1[k]And theta2[k]Is started.
Specifically, in the RLS recursive algorithm:
Figure BDA0003131579010000091
order to
Figure BDA0003131579010000092
Wherein, YkRepresenting the matrix formed by the frequency offsets from the 1 st to the kth historical sampling instant, i.e.
Figure BDA0003131579010000093
ΦkThe coefficients representing the model parameters in the frequency offset model form a coefficient matrix, i.e.
Figure BDA0003131579010000094
PkIs a covariance matrix.
In calculating theta1[k]And theta2[k]And the initial value of the covariance matrix, k may be 2,
Figure BDA0003131579010000095
substituting into equation 1-2, θ can be obtained1[k]And theta2[k]The initial values of (a) are: theta1[1]＝θ1[2]＝2·g[1]-g[2]；θ2[1]＝θ2[2]＝g[2]-g[1]。
The k is changed to 2, and the reaction is carried out,
Figure BDA0003131579010000096
substituting into the formula 1-3 to obtain the covariance matrix PkI.e. by
Figure BDA0003131579010000097
I.e. p11[2]＝5,p12[2]＝-3,p21[2]＝-3,p22[2]＝2。
Further, assume that the clock difference integrated value at the k-th history time of training is represented by test[k]Indicating the initial value t of the clock difference integrated valueest[2]＝τ2-τ0。
After obtaining the initial value (i.e. theta) of the model parameter1[1]、θ2[1]、θ1[2]、θ2[2]) Initial value of covariance matrix (i.e., P)1And P2) And an initial value t of the clock difference integrated valueest[2]Thereafter, loop iterations such as steps a1 through A3 may be performed based on the initial value until a preset iteration condition is satisfied.
Wherein the iteration stop condition may be: the frequency offset prediction model converges, or the number of iterations reaches a preset number, etc., and here, the iteration stop condition is merely described by way of example, and is not specifically limited.
The following step a1 to step A3 are described in detail below.
Step A1: and determining the gain vector of the iteration based on the covariance matrix obtained by the last iteration and the moment identifier of the sampling moment corresponding to the iteration.
Assuming that the iteration is the mth iteration, the covariance matrix obtained in the previous iteration is:
Figure BDA0003131579010000101
the historical sampling moment mark corresponding to the iteration is m; the gain vector of this iteration is (G)1[m]，G2[m]) Wherein G is1[m]Representing the model parameter theta1[k]Gain of (G)2[m]Representing the model parameter theta2[k]The gain of (c).
The electronic device may obtain the gain vector for this iteration by equations 1-4 and 1-5.
Figure BDA0003131579010000102
Figure BDA0003131579010000103
Where u is the median of the calculated gain vectors.
Further, it is also to be noted that: after the gain vector of the iteration is calculated, although the covariance matrix of the iteration is not needed in the iteration, the covariance matrix of the iteration can be obtained and recorded based on the covariance matrix of the previous iteration and the gain vector obtained in the iteration. The recorded covariance matrix of the iteration is mainly used for calculating a gain vector of the next iteration in the next iteration.
Next, the covariance matrix of the current iteration is obtained based on the covariance matrix of the previous iteration and the gain vector obtained by the current iteration.
Specifically, when the preset recursive algorithm is the RLS algorithm, the electronic device may calculate the covariance matrix of the current iteration based on formulas 1 to 6.
Figure BDA0003131579010000111
Wherein (G)1[m]，G2[m]) Is the gain vector of the iteration;
Figure BDA0003131579010000112
a covariance matrix obtained for the last iteration;
and m is a time mark of the historical sampling time corresponding to the iteration.
And A2, determining the model parameters of the iteration based on the model parameters of the previous iteration, the clock error actual value corresponding to the iteration and the gain vector obtained by the iteration.
Specifically, when the preset recursive algorithm is the RLS algorithm, the electronic device may calculate the model parameter of the current iteration based on formulas 1 to 7 and 1 to 8.
v＝g[m]-(θ1[m-1]+m·θ2[m-1]) (ii) a (formulae 1 to 7)
Figure BDA0003131579010000113
Wherein, theta1[m-1]、θ2[m-1]Model parameters obtained for the last iteration;
g [ m ] is a frequency offset sample of the corresponding mth historical sampling moment of the iteration;
(G1[m]，G2[m]) Is the gain vector of the iteration;
v is the median value of the model parameters for calculating this iteration.
Step A3: and determining the clock error accumulated value corresponding to the iteration based on the model parameters of the iteration and the clock error accumulated value obtained by the last iteration.
Because the clock error is accumulated in each iteration, after the model parameters of the current iteration are calculated, the electronic equipment can also determine the clock error accumulated value corresponding to the current iteration based on the model parameters of the current iteration and the clock error accumulated value obtained in the last iteration.
In an optional method for calculating the clock difference accumulated value, the electronic device determines the clock difference accumulated value corresponding to the current iteration directly based on the model parameter of the current iteration and the clock difference accumulated value obtained from the last iteration, which can be specifically realized by formulas 1 to 9.
test[m]＝test[m-1]-d·(θ1[m]+(m-1)·θ2[m]) (ii) a (formulae 1 to 9)
Wherein, test[m]The accumulated value of the clock error of the iteration is obtained;
test[m-1]the accumulated value of the clock error obtained from the last iteration;
d is the time interval (or sampling step length) between the mth historical sampling moment and the (m-1) th sampling moment;
θ1[m]、θ2[m]the model parameters obtained for this iteration.
Of course, in another alternative implementation, the accumulated value of the clock difference is obtained more accurately. The electronic device may determine the cumulative clock error correction amount of the current iteration based on the model parameter of the current iteration, the model parameter of the last iteration, and the time identifier of the historical sampling time corresponding to the current iteration. Then, the electronic device determines the clock error accumulated value of the current iteration based on the clock error accumulated value obtained by the last iteration, the model parameter obtained by the current iteration and the accumulated clock error correction quantity obtained by the current iteration.
Specifically, when calculating the cumulative clock error correction amount, the electronic device may be implemented by equations 1-10 and equations 1-11.
Figure BDA0003131579010000121
Figure BDA0003131579010000122
Wherein, theta1[m]、θ2[m]Obtaining model parameters for the iteration;
θ1[m-1]、θ2[m-1]model parameters obtained for the last iteration;
m is a time mark of a historical sampling time corresponding to the iteration;
Ca、Cban intermediate value calculated for the cumulative clock error correction;
Figure BDA0003131579010000123
and obtaining the accumulated clock error correction quantity for the iteration.
In the present application, when determining the clock difference accumulated value of the current iteration based on the clock difference accumulated value obtained by the last iteration, the model parameter obtained by the current iteration, and the accumulated clock difference correction amount obtained by the current iteration, the electronic device may implement the calculation of the clock difference accumulated value of the current iteration by using formulas 1 to 12.
Figure BDA0003131579010000124
Wherein, test[m]The accumulated value of the clock error of the iteration is obtained;
test[m-1]the accumulated value of the clock error obtained from the last iteration;
d is the time interval (or sampling step length) between the mth historical sampling moment and the (m-1) th historical sampling moment;
θ1[m]、θ2[m]obtaining model parameters for the iteration;
Figure BDA0003131579010000131
and obtaining the accumulated clock error correction quantity for the iteration.
Further, upon each iteration performing step a3, the electronic device may detect whether an iteration stop condition is satisfied. If the iteration stop condition is met, taking the model parameter of the current iteration as the final model parameter of the frequency offset prediction model, and determining the clock error accumulated value corresponding to the current iteration as the target clock error accumulated value; if the iteration stop condition is not satisfied, the next iteration from step A1 to step A3 is performed.
The above is the training process of the frequency offset prediction model.
2. Compensating clock signal output by electronic equipment by using frequency offset prediction model
Referring to fig. 1, fig. 1 is a flowchart illustrating a clock compensation method according to an exemplary embodiment of the present application, which can be applied to an electronic device.
The electronic device is a device having a clock and requiring clock adjustment. For example, the electronic device may be a base station, or may be a hardware device on the base station, and the electronic device is only described as an example and is not specifically limited.
In addition, the clock compensation method may be applied in a 5G (5th Generation Mobile Communication Technology, fifth Generation Mobile Communication Technology) Communication scenario, and may also be applied in a 4G (4th Generation Mobile Communication Technology, fourth Generation Mobile Communication Technology) Communication scenario, and a 3G (3th Generation Mobile Communication Technology, third Generation Mobile Communication Technology) Communication scenario, which is not specifically limited herein.
The method may include the steps shown below.
Step 101: the electronic equipment acquires a clock signal output by the electronic equipment at the current sampling moment;
step 102: the electronic equipment inputs the time identification of the current time into a trained frequency offset prediction model so as to output a frequency offset prediction value corresponding to the current time by the frequency offset prediction model; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock difference corresponding to at least one historical sampling moment before the loss of the standard clock, wherein the clock difference is the phase difference between a clock signal output by the electronic equipment and the standard clock signal;
the prediction method of the frequency offset prediction model may be as described above, and is not described here again.
The way of constructing the frequency offset samples is also as shown above and will not be described again here.
As can be seen from the above description, the frequency offset prediction model is a model describing the sampling time and the frequency offset change rule, so that the electronic device can obtain the frequency offset prediction value corresponding to the current sampling time after inputting the time identifier of the current time into the trained frequency offset prediction model.
For example, still taking the above example as an example, if the historical sampling time corresponding to the last iteration is the nth historical sampling time when the training of the frequency offset prediction model is completed, the model parameter of the frequency offset prediction model is θ1[N]、θ2[N]。
The trained frequency offset prediction model is: f. ofest[k]＝θ1[N]+kθ2[N]；
The target clock error accumulated value obtained when training is completed is as follows: t is test[N]。
Assuming that the current sampling time is the Tth sampling time from when the standard clock is lost, the electronic device may send the current sampling time to the receiverT input to fest[k]＝θ1[N]+kθ2[N]In the method, a frequency deviation predicted value f at the T-th sampling moment is obtainedest[T]。
Step 103: and the electronic equipment determines the clock error corresponding to the current sampling time based on the frequency offset predicted value corresponding to the current sampling time, the recorded frequency offset predicted value corresponding to each sampling time from the loss of the standard clock to the current sampling time, and the target clock error accumulated value obtained when the training of the frequency offset prediction model is completed.
Assuming that the current sampling time is T time, in implementation, the electronic device may implement a clock difference corresponding to the current sampling time by using the following formulas 1 to 13:
Figure BDA0003131579010000141
wherein,
Figure BDA0003131579010000142
the clock error of the current Tth sampling moment;
test[N]obtaining a target clock error accumulated value when the frequency deviation prediction model is trained;
d is a sampling step length;
Figure BDA0003131579010000151
the sum of the predicted values of the frequency offset at each sampling time from the 1 st sampling time to the T-th sampling time (i.e. the current sampling time) when the standard clock is lost.
Step 104: the electronic equipment compensates the clock signal output by the electronic equipment at the current sampling time by adopting the clock difference corresponding to the current sampling time.
The electronic device can adjust the clock signal output by the electronic device at the current sampling time according to the clock difference determined at the current sampling time, so that the adjusted clock signal is closer to the standard clock signal, namely, the difference value between the adjusted clock signal and the standard clock signal is within the preset range.
As can be seen from the above description, in the present application, since the clock offset is converted into the frequency offset, and the change rule of the frequency offset with time is found, after the standard clock is lost, the frequency offset can be predicted by using the change rule, the predicted frequency offset is converted into the predicted clock offset, and the predicted clock offset is used to compensate the clock signal output by the electronic device after the standard clock is lost. Compared with a Kalman filtering algorithm for compensating the clock, the clock compensation method is lower in complexity, less in calculated amount and less in system resource consumption during clock compensation.
In addition, the RLS algorithm is applied to the training process of the frequency offset prediction model, and the clock difference accumulated value in the training process is accumulated, so that the accuracy of predicting the clock difference of the current sampling time when the subsequent standard clock is lost is higher, and the clock calibration with higher precision can be realized (for example, the clock calibration in a 5G scene can be realized).
Referring to fig. 2, fig. 2 is a hardware structure diagram of an electronic device according to an exemplary embodiment of the present application.
The electronic device includes: a communication interface 201, a processor 202, a machine-readable storage medium 203, and a bus 204; wherein the communication interface 201, the processor 202 and the machine-readable storage medium 203 communicate with each other via a bus 204. The processor 202 may perform the clock compensation method described above by reading and executing machine-executable instructions in the machine-readable storage medium 203 corresponding to the clock compensation control logic.
The machine-readable storage medium 203 referred to herein may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and the like. For example, the machine-readable storage medium may be: volatile memory, non-volatile memory, or similar storage media. In particular, the machine-readable storage medium 203 may be a RAM (random Access Memory), a flash Memory, a storage drive (e.g., a hard drive), a solid state drive, any type of storage disk (e.g., a compact disk, a DVD, etc.), or similar storage medium, or a combination thereof.
Referring to fig. 3, fig. 3 is a block diagram of a clock compensation apparatus according to an exemplary embodiment of the present application. The device can be applied to electronic equipment and comprises the following steps:
an obtaining unit 301, configured to obtain a clock signal output by the electronic device at a current sampling time;
a predicting unit 302, configured to input a time identifier of a current sampling time into a trained frequency offset prediction model, so that the frequency offset prediction model outputs a frequency offset prediction value corresponding to the current sampling time; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock error actual value corresponding to at least one historical sampling moment before the loss of the standard clock, and the clock error actual value is the phase difference between the clock signal output by the electronic equipment and the standard clock signal;
a determining unit 303, configured to determine a clock difference predicted value corresponding to the current sampling time based on the frequency offset predicted value corresponding to the current sampling time, the recorded frequency offset predicted values corresponding to sampling times from when the standard clock is lost to the current sampling time, and a target clock difference accumulated value obtained when training of the frequency offset prediction model is completed;
and the compensating unit 304 is configured to compensate the clock signal output by the electronic device at the current sampling time by using the clock difference predicted value corresponding to the current sampling time.
Optionally, the apparatus further comprises a training unit;
the training unit 305, when training the frequency offset prediction model and the target clock error cumulative value through a preset recursive algorithm, is configured to cyclically execute the following iteration steps until a preset iteration condition is met; determining a gain vector of the iteration based on the covariance matrix obtained by the last iteration and the moment identifier of the sampling moment corresponding to the iteration; determining the model parameters of the iteration based on the model parameters of the previous iteration, the clock error actual value corresponding to the iteration and the gain vector obtained by the iteration; and determining the clock error accumulated value corresponding to the iteration based on the model parameters of the iteration and the clock error accumulated value obtained by the last iteration.
Optionally, the training unit 305 is further configured to, after the gain vector of the current iteration is determined, determine and record a covariance matrix of the current iteration based on the gain vector obtained by the current iteration and a covariance matrix obtained by the last iteration, so that the gain vector of the next iteration is determined through the covariance matrix of the current iteration during the next iteration.
Optionally, the initial values of the model parameters of the frequency offset prediction model and the initial values of the covariance matrix are calculated from the time identifiers of the two historical sampling times and the frequency offset samples constructed by the clock difference actual values of the two historical sampling times.
Optionally, when determining the clock difference integrated value corresponding to the current iteration based on the model parameter of the current iteration and the clock difference integrated value obtained by the previous iteration, the training unit 305 is configured to determine the accumulated clock difference correction amount of the current iteration based on the model parameter of the current iteration, the model parameter of the previous iteration, and the time identifier of the historical sampling time corresponding to the current iteration; and determining the clock error accumulated value of the current iteration based on the clock error accumulated value obtained by the last iteration, the model parameter obtained by the current iteration and the accumulated clock error correction quantity obtained by the current iteration.
Optionally, the preset recursive algorithm is an RLS algorithm.
The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (12)

1. A clock compensation method is applied to an electronic device, the electronic device is used after a standard clock is lost and before the standard clock is recovered, and the method comprises the following steps:
acquiring a clock signal output by the electronic equipment at the current sampling moment;
inputting a time mark of the current sampling time into a trained frequency offset prediction model so as to output a frequency offset prediction value corresponding to the current sampling time by the frequency offset prediction model; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock error actual value corresponding to at least one historical sampling moment before the loss of the standard clock, and the clock error actual value is the phase difference between the clock signal output by the electronic equipment and the standard clock signal;
determining a frequency deviation predicted value corresponding to the current sampling time based on the frequency deviation predicted value corresponding to the current sampling time, the recorded frequency deviation predicted value corresponding to each sampling time from the loss of the standard clock to the current sampling time, and a target clock difference accumulated value obtained when the training of the frequency deviation prediction model is completed;
and compensating the clock signal output by the electronic equipment at the current sampling time by adopting the clock difference predicted value corresponding to the current sampling time.
2. The method of claim 1, wherein the frequency deviation prediction model and the target clock error accumulation value are trained by a predetermined recursive algorithm:
circularly executing the following iteration steps until a preset iteration condition is met;
determining a gain vector of the iteration based on the covariance matrix obtained by the last iteration and the moment identifier of the sampling moment corresponding to the iteration;
determining the model parameters of the iteration based on the model parameters of the previous iteration, the clock error actual value corresponding to the iteration and the gain vector obtained by the iteration;
and determining the clock error accumulated value corresponding to the iteration based on the model parameters of the iteration and the clock error accumulated value obtained by the last iteration.
3. The method of claim 2, wherein after determining the gain vector for the current iteration, the method further comprises:
and determining and recording the covariance matrix of the iteration based on the gain vector obtained by the iteration and the covariance matrix obtained by the last iteration, so as to determine the gain vector of the next iteration through the covariance matrix of the iteration during the next iteration.
4. The method of claim 2, wherein the initial values of the model parameters of the frequency offset prediction model and the initial values of the covariance matrix are calculated from frequency offset samples constructed by time identifications of two historical sampling times and actual values of clock differences of the two historical sampling times.
5. The method of claim 2, wherein determining the clock error cumulative value corresponding to the current iteration based on the model parameters of the current iteration and the clock error cumulative value obtained from the last iteration comprises:
determining the accumulated clock error correction amount of the iteration based on the model parameter of the iteration, the model parameter of the last iteration and the time identification of the historical sampling time corresponding to the iteration;
and determining the clock error accumulated value of the current iteration based on the clock error accumulated value obtained by the last iteration, the model parameter obtained by the current iteration and the accumulated clock error correction quantity obtained by the current iteration.
6. The method of claim 2, wherein the predetermined recursive algorithm is an RLS algorithm.
7. A clock compensation apparatus, applied to an electronic device, wherein the electronic device is configured to recover a standard clock after the standard clock is lost and before the standard clock is recovered, the apparatus comprising:
the acquisition unit is used for acquiring a clock signal output by the electronic equipment at the current sampling moment;
the prediction unit is used for inputting the time mark of the current sampling time into the trained frequency offset prediction model so as to output a frequency offset prediction value corresponding to the current sampling time by the frequency offset prediction model; the frequency offset prediction model is obtained by training a frequency offset sample; the frequency offset sample is constructed by a clock error actual value corresponding to at least one historical sampling moment before the loss of the standard clock, and the clock error actual value is the phase difference between the clock signal output by the electronic equipment and the standard clock signal;
a determining unit, configured to determine a frequency offset predicted value corresponding to the current sampling time based on the frequency offset predicted value corresponding to the current sampling time, the recorded frequency offset predicted values corresponding to sampling times from when the standard clock is lost to the current sampling time, and a target clock offset accumulated value obtained when training of the frequency offset prediction model is completed;
and the compensation unit is used for compensating the clock signal output by the electronic equipment at the current sampling moment by adopting the clock difference predicted value corresponding to the current sampling moment.
8. The apparatus of claim 7, further comprising a training unit;
the training unit is used for circularly executing the following iteration steps until a preset iteration condition is met when the frequency offset prediction model and the target clock error accumulated value are trained through a preset recursive algorithm; determining a gain vector of the iteration based on the covariance matrix obtained by the last iteration and the moment identifier of the sampling moment corresponding to the iteration; determining the model parameters of the iteration based on the model parameters of the previous iteration, the clock error actual value corresponding to the iteration and the gain vector obtained by the iteration; and determining the clock error accumulated value corresponding to the iteration based on the model parameters of the iteration and the clock error accumulated value obtained by the last iteration.
9. The apparatus according to claim 8, wherein the training unit is further configured to, after determining the gain vector of the current iteration, determine and record a covariance matrix of the current iteration based on the gain vector of the current iteration and a covariance matrix of the last iteration, so as to determine a gain vector of a next iteration through the covariance matrix of the current iteration at a next iteration.
10. The apparatus of claim 8, wherein the initial values of the model parameters of the frequency offset prediction model and the initial values of the covariance matrix are calculated from frequency offset samples constructed by time identifications of two historical sampling times and actual values of clock differences of the two historical sampling times.
11. The apparatus according to claim 8, wherein the training unit, when determining the clock error integrated value corresponding to the current iteration based on the model parameter of the current iteration and the clock error integrated value obtained from the previous iteration, is configured to determine the accumulated clock error correction amount of the current iteration based on the model parameter of the current iteration, the model parameter of the previous iteration, and the time stamp of the historical sampling time corresponding to the current iteration; and determining the clock error accumulated value of the current iteration based on the clock error accumulated value obtained by the last iteration, the model parameter obtained by the current iteration and the accumulated clock error correction quantity obtained by the current iteration.
12. The apparatus of claim 8, wherein the pre-determined recursive algorithm is an RLS algorithm.
CN202110704345.5A 2021-06-24 2021-06-24 Clock compensation method and device Active CN113325919B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110704345.5A CN113325919B (en) 2021-06-24 2021-06-24 Clock compensation method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110704345.5A CN113325919B (en) 2021-06-24 2021-06-24 Clock compensation method and device

Publications (2)

Publication Number Publication Date
CN113325919A true CN113325919A (en) 2021-08-31
CN113325919B CN113325919B (en) 2024-01-23

Family

ID=77424623

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110704345.5A Active CN113325919B (en) 2021-06-24 2021-06-24 Clock compensation method and device

Country Status (1)

Country Link
CN (1) CN113325919B (en)

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645718A (en) * 2008-08-07 2010-02-10 中兴通讯股份有限公司 Method and device for holding clock
US20100266003A1 (en) * 2009-03-19 2010-10-21 Lucila Patino-Studencka Method and Apparatus for Estimating Clock Deviations, for Virtual Synchronization of Free-Running Clocks and for Determining the Position of a Movable Object
CN102394855A (en) * 2011-11-17 2012-03-28 北京新岸线无线技术有限公司 Sampling clock frequency compensation method and device
CN102983881A (en) * 2012-12-17 2013-03-20 广州海格通信集团股份有限公司 Frequency hopping synchronization realization method based on Big Dipper timing chip
CN104378109A (en) * 2013-08-13 2015-02-25 中兴通讯股份有限公司 Synchronous clock signal compensation method and device
CN104579527A (en) * 2013-10-12 2015-04-29 联发科技（新加坡）私人有限公司 Timing deviation compensation device and method
CN106877963A (en) * 2016-12-29 2017-06-20 河北远东通信系统工程有限公司 A kind of synchronised clock with learning functionality keeps system and method
CN107566105A (en) * 2017-08-07 2018-01-09 南方电网科学研究院有限责任公司 Time synchronization equipment compensation method, device, storage medium and computer equipment thereof
CN110557826A (en) * 2019-09-20 2019-12-10 北京邮电大学 Clock synchronization method and device
CN110649913A (en) * 2018-06-27 2020-01-03 北京松果电子有限公司 Frequency adjustment method and device for crystal oscillator, storage medium and electronic equipment
CN112969229A (en) * 2021-01-28 2021-06-15 新华三技术有限公司合肥分公司 Clock correction method and device and network equipment

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645718A (en) * 2008-08-07 2010-02-10 中兴通讯股份有限公司 Method and device for holding clock
US20100266003A1 (en) * 2009-03-19 2010-10-21 Lucila Patino-Studencka Method and Apparatus for Estimating Clock Deviations, for Virtual Synchronization of Free-Running Clocks and for Determining the Position of a Movable Object
CN102394855A (en) * 2011-11-17 2012-03-28 北京新岸线无线技术有限公司 Sampling clock frequency compensation method and device
CN102983881A (en) * 2012-12-17 2013-03-20 广州海格通信集团股份有限公司 Frequency hopping synchronization realization method based on Big Dipper timing chip
CN104378109A (en) * 2013-08-13 2015-02-25 中兴通讯股份有限公司 Synchronous clock signal compensation method and device
CN104579527A (en) * 2013-10-12 2015-04-29 联发科技（新加坡）私人有限公司 Timing deviation compensation device and method
CN106877963A (en) * 2016-12-29 2017-06-20 河北远东通信系统工程有限公司 A kind of synchronised clock with learning functionality keeps system and method
CN107566105A (en) * 2017-08-07 2018-01-09 南方电网科学研究院有限责任公司 Time synchronization equipment compensation method, device, storage medium and computer equipment thereof
CN110649913A (en) * 2018-06-27 2020-01-03 北京松果电子有限公司 Frequency adjustment method and device for crystal oscillator, storage medium and electronic equipment
CN110557826A (en) * 2019-09-20 2019-12-10 北京邮电大学 Clock synchronization method and device
CN112969229A (en) * 2021-01-28 2021-06-15 新华三技术有限公司合肥分公司 Clock correction method and device and network equipment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
寸天睿;: "TDM网络时钟同步改进方法研究", 电子技术与软件工程, no. 14, pages 19 - 20 *

Also Published As

Publication number Publication date
CN113325919B (en) 2024-01-23

Similar Documents

Publication Publication Date Title
CN108573270B (en) Method and apparatus for synchronizing multi-sensor target information fusion and multi-sensor sensing, computer device, and recording medium
CN109472418B (en) Maneuvering target state prediction optimization method based on Kalman filtering
CN110865398B (en) Processing method and processing device for positioning data, terminal equipment and storage medium
WO2018059532A1 (en) Integrated navigational data calculation method of time-delay observation system, apparatus and navigational device
CN108319570B (en) Asynchronous multi-sensor space-time deviation joint estimation and compensation method and device
KR20160035637A (en) method, apparatus, and recording medium for estimating location
JP2009300380A (en) Target tracking device
CN107086901A (en) A kind of BDT method for building up and UTC (NTSC) method for building up
CN113393519B (en) Laser point cloud data processing method, device and equipment
CN110375772A (en) The ring laser stochastic error modeling of adaptive Kalman filter and compensation method
KR20200077713A (en) Method for estimating brix degree of citrus using climate information, device and computer readable medium for performing the method
CN113325919A (en) Clock compensation method and device
KR101675759B1 (en) method, apparatus, and recording medium for estimating location
US10820152B2 (en) Device diversity correction method for RSS-based precise location tracking
Ma et al. Output‐only modal parameter recursive estimation of time‐varying structures via a kernel ridge regression FS‐TARMA approach
CN112414431A (en) Robust vehicle-mounted multi-sensor external parameter calibration method
CN104614704B (en) A kind of method and apparatus of determining mobile terminal locations
JP5300333B2 (en) POSITIONING DEVICE, POSITIONING METHOD, AND POSITIONING PROGRAM
CN110113660A (en) Method, device, terminal and storage medium for transcoding time length estimation
CN114818247A (en) Atomic time calculation method and device based on hydrogen atomic clock drift prediction
CN114254063A (en) Method for acquiring track recovery model, and method and device for track recovery
JP5058594B2 (en) POSITIONING POINT ESTIMATION DEVICE, POSITIONING POINT ESTIMATION METHOD, PROGRAM THEREOF, AND RECORDING MEDIUM
CN102788988B (en) Positioning device and positioning method thereof
CN112698368B (en) Navigation signal analysis method of navigation receiver and computer readable medium
CN109581284A (en) Non-line-of-sight error elimination method based on interactive multiple models

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant