CN113324661B - Built-in test circuit and test method for infrared focal plane detector reading circuit - Google Patents
Built-in test circuit and test method for infrared focal plane detector reading circuit Download PDFInfo
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Abstract
The invention discloses a built-in test circuit and a test method of a read-out circuit of an infrared focal plane detector, which comprises a row test pixel circuit array, a column test pixel circuit array, a reference group test pixel circuit array and a test current generating circuit, wherein the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array are independent from an effective pixel circuit array of the read-out circuit, and signal reading is carried out by multiplexing a control logic unit, a signal transmission unit and the like of the read-out circuit. The test current generating circuit generates current to replace photocurrent to drive each test pixel circuit in a certain sequence. The test and evaluation of crosstalk, signal integrity, dynamic range of a reading circuit, linearity and the like can be completed only by carrying out single acquisition and calculation analysis on the output of the test pixel circuit.
Description
Technical Field
The invention relates to the technical field of infrared focal plane detectors, in particular to a built-in test circuit and a test method of a reading circuit of an infrared focal plane detector.
Background
The reading circuit is used as an important component of an infrared detector assembly, and has the main functions of integrating, amplifying, performing analog-digital conversion and the like on photocurrent of the detector and outputting a result to the outside of a chip, wherein the performance of the reading circuit has important influence on the performance of the infrared detector and even the whole infrared imaging system.
The main components of the readout circuit include: an effective pixel circuit array (hereinafter abbreviated as PX) composed of H × V (H and V are integers) identical effective pixel circuits, a column-level circuit, a multiplexer, a row control logic circuit, and the like. The input of the readout circuit is the photocurrent of the detector, in order to examine the performance of the readout circuit simply, the current testing technology generally adds a testing unit in each effective pixel circuit, the current input is generated by replacing an infrared detector under the drive of a bias voltage, the effective pixel circuit integrates and amplifies the current, the same column of effective pixel circuits PX <1, i >, PX <2, i > … … PX < H, i > transmit output signals to a column-level circuit row by row through a signal bus W < i > under the control of a row control logic circuit (i is an integer and i is not less than 1 and not more than V), and finally the output signals are output to the outside of the chip through a multiplexer, and a testing system collects the output data to a PC end for analysis and processing and calculates various performance indexes of the readout circuit. The timing diagram of the operation of the readout circuit is shown in fig. 1.
In the current test technology of the readout circuit, in order to reduce the number of pins and the size of a chip of the readout circuit, the test units of all the effective pixel circuits are driven by the same bias voltage, that is, the inputs of all the effective pixel circuits are the same. However, in an actual application environment, because the focal plane infrared detector faces a complex scene, the input of each effective pixel circuit of the readout circuit is different, and the current on-chip test circuit and test method cannot simulate the situation, the performances in the aspects of crosstalk between the effective pixel circuits and between signal buses cannot be reflected; because the inputs of all the effective pixels are the same, the establishment condition of a time-varying signal on a signal bus cannot be reflected, and the working condition of a column-level circuit facing the time-varying input cannot be reflected; in addition, in the current readout circuit testing technology, in order to obtain technical indexes such as the dynamic range of the readout circuit, the adjustment of the magnitude of the bias voltage needs to be performed outside the readout circuit chip for many times in combination with the working timing sequence of the readout circuit so as to adjust the input current of the effective pixel circuit, data needs to be collected and calculated after each adjustment, and the whole process is complicated.
Disclosure of Invention
The invention aims to provide a built-in test circuit and a test method of a reading circuit of an infrared focal plane detector, which solve the problem that the existing on-chip test circuit and test method can not reflect the performance of each effective pixel circuit of the reading circuit facing different inputs, and provide a method which is simpler and easier than the traditional test technology to test the dynamic performance of the reading circuit.
The invention discloses a built-in test circuit for a reading circuit of an infrared focal plane detector, which comprises the following components: the device comprises a row test pixel circuit array, a column test pixel circuit array, a reference group test pixel circuit array and a test current generation circuit.
The array specification of the row test pixel circuit array is M multiplied by N (M, N is an integer and is an even number, the same below), the row test pixel circuit array is positioned in the row direction of the reading circuit, and each test pixel circuit is completely the same as the effective pixel circuit;
the array specification of the column test pixel circuit array is NxM, the column test pixel circuit array is positioned in the column direction of the reading circuit, and each test pixel circuit is completely the same as the effective pixel circuit;
the array specification of the reference group test pixel circuit array is Mx 1, the reference group test pixel circuit array is positioned around the reading circuit, and each test pixel circuit is completely the same as the effective pixel circuit;
the input of the test current generating circuit is provided by the outside of the reading circuit and generates M currents I <1> to I < M >, wherein I <1> I <2> … …: I < M > is 1:2: … …: M; the M currents replace the photocurrent of the infrared detector to drive the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array in a certain sequence; the input of the test current generating circuit is such that the generated test current satisfies the following condition:
a) i <1> should be small enough that the output value of the test pixel circuit with I <1> as an input reaches the minimum output value of the readout circuit after integrating and amplifying the current;
b) i < M > should be large enough, so that the I < M > is used as the input of the test pixel circuit, and after the current is integrated and amplified, the output value of the test pixel circuit reaches the maximum output value of the reading circuit;
c) the design of the test current generating circuit and the selection of the input current are such that I <1> to I < M > cover the dynamic range of the sensing circuit.
The connection relation between the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array and the test current generating circuit is as follows:
a) the input of the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array is provided by a test current generating circuit;
b) i <1> to I < M > sequentially drive the M < M, 1> to R <1, 1> of the 1 st column in the row test pixel circuit array, simultaneously sequentially drive the 1 st to M <1, 2> to R < M, 2> of the 2 nd column, and simultaneously sequentially drive the M < M, 3> to R <1, 3> … … of the 3 rd column;
c) meanwhile, I <1> -I < M > also sequentially drive the 1 st to M th test pixel circuits C <1, 1> -C <1, M > in the 1 st row in the column test pixel circuit array, simultaneously sequentially drive the M to 1 st test pixel circuits C <2, M > -C <2, 1> in the 2 nd column, and simultaneously sequentially drive the 1 st to M test pixel circuits C <3, 1> -C <3, M > … … in the 3 rd column;
d) meanwhile, I <1> to I < M > also sequentially drive the 1 st to M th test pixel circuits F <1, 1> to F < M, 1> of the reference group test pixel circuit array.
I <1> simultaneously drives R < M, 1>, R <1, 2> and R < M, 3> … … in the row test pixel circuit array and C <1, 1>, C <2, M > and C <3, 1> … … in the column test pixel circuit array and also drives the 1 st test pixel circuit F <1, 1> of the reference group test pixel circuit array; i <2> simultaneously drives R < M-1, 1>, R <2, 2>, R < M-1, 3> … … in the row test pixel circuit array and C <1, 2>, C <2, M-1>, C <3, 2> … … in the column test pixel circuit array and drives the 2 nd test pixel circuit F <2, 1> of the reference group test pixel circuit array. And so on.
The row test pixel circuit array is transmitted to the existing column-level circuit of the readout circuit row by row through M signal buses W _ R <1> -W _ R < M > (the same column of test pixel circuits of the row test pixel circuit array multiplexes one signal bus) under the control of the row control logic circuit; the column test pixel circuit array is transmitted to the existing column-level circuit of the readout circuit row by row through M signal buses W _ C <1> -W _ C < M > (the same column test pixel circuit of the column test pixel circuit array multiplexes one signal bus) under the control of the row control logic circuit; the reference group test pixel circuit array is transmitted to the existing column circuit of the reading circuit row by row through a signal bus W _ F under the control of the row control logic circuit; the outputs of the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array complete the transmission of signals to the outside of the chip through the existing column level circuit and the multiplexer of the multiplexing reading circuit.
As described above, the core idea of the built-in test circuit for the focal plane infrared detector readout circuit of the present invention is to investigate crosstalk of each effective pixel circuit of the readout circuit under different input signals through the row test pixel circuit array and the reference group test pixel circuit array; inspecting the integrity of signals facing different input ends of the reading circuit in the signal bus transmission process through the column test pixel circuit array and the reference group test pixel circuit array; the dynamic range and linearity of the readout circuit are examined by referring to the group test pixel circuit array. The other purpose of the invention, namely, the performance test method for the readout circuit of the infrared focal plane detector, is realized by adopting a test method for crosstalk of the readout circuit facing different inputs, a test method for integrity of signals of the readout circuit facing different inputs in a signal bus transmission process, a test method for dynamic range and linearity of the readout circuit, and the like, which are respectively described below.
(1) Method for testing crosstalk of reading circuit facing different inputs
In the row test pixel circuit array, the inputs of the adjacent test pixel circuits (R <1, 1>, R <1, 2> … … R <1, M) in the 1 st row are I <1> and I < M >, namely, the inputs of R <1, 1>, R <1, 2> … … R <1, M) have the largest input difference, and under the control of the existing row control logic circuit of the readout circuit, R <1, 1>, R <1, 2> … … R <1, M > are integrated at the same time and signal readout is carried out at the same time, so that the adjacent test pixel circuits in the 1 st row in the row test pixel circuit array have the largest crosstalk.
In the row test pixel circuit array, the inputs of the adjacent test pixel circuits (R <2, 1>, R <2, 2> … … R <2, M >) in the 2 nd row are I <2> and I < M-1>, namely, the inputs of R <2, 1>, R <2, 2> … … R <2, M > have the second largest input difference, and under the control of the existing row control logic circuit of the readout circuit, R <2, 1>, R <2, 2> … … R <2, M > are integrated at the same time and read out signals at the same time, so that the adjacent test pixel circuits in the 2 nd row in the row test pixel circuit array have the second largest crosstalk.
By analogy with the above, in the row test pixel circuit array, the inputs of each test pixel circuit (R < M/2, 1>, R < M/2, 2> … … R < M/2, M >) in the M/2 th row (for example, M is 512, here, 256 th row) are the same and are all I < M/2>, so that there is no crosstalk between adjacent test pixel circuits in the M/2 th row in the row test pixel circuit array.
The area array specification of the reference group test pixel circuit array is M multiplied by 1, the input of each test pixel circuit F <1, 1>, F <2, 1> … … F < M, 1> is I <1>, and no other test pixel circuits and signals around I <2> … … I < M > cause crosstalk.
Because the input of the adjacent test pixel circuits R <1, 1>, R <1, 2> … … R <1, M > of the 1 st row in the row test pixel circuit array is I <1> and I < M >, and the input of the 1 st and M test pixel circuits F <1, 1>, F < M, 1> of the reference group test pixel circuit array is I <1> and I < M > (the input of each test pixel circuit in the reference group test pixel circuit array is the same as the test pixel circuit in the row test pixel circuit array), the output OUT _ R <1, 1>, R <1, 3> … … R <1, M-1> of the R <1, R-1 > is output OUT _ R <1, 1>, OUT _ R <1, 3> … … _ R <1, M-1> is output OUT _ F M, 1> of the pixel circuits and the output OUT _ F M, 1> of the pixel circuits are respectively <1, averaged, so that the input of the left and right test pixel circuits is I <1> and the input of the test pixel circuits is subtraction of the output OUT _ M <1> of the test pixel circuits Crosstalk, wherein the crosstalk to the test pixel circuit with input I <1> when the input of the test pixel circuit on the left side and the right side is I < M > can be obtained by respectively subtracting and averaging the outputs OUT _ R <1, 2>, OUT _ R <1, 4> … … OUT _ R <1, M > of R <1, 4> … … R <1, M > and the outputs OUT _ F <1, 1> of F <1, 1 >; this is the maximum crosstalk. Since the inputs of the adjacent test pixel circuits R <2, 1>, R <2, 2> … … R <2, M > in row 2 in the row-test pixel circuit array are I <2> and I < M-1>, respectively, and the inputs of the 2 nd and M-1 st test pixel circuits F <2, 1>, F < M-1, 1> in the reference group test pixel circuit array are I <2> and I < M-1> (each of the test pixel circuits in the reference group test pixel circuit array is the same as the test pixel circuit in the row-test pixel circuit array), by making the outputs OUT _ R <2, 1>, R <2, 3> … … R <2, M-1> OUT _ R <2, 3> … … OUT _ R <2, M-1> and OUT _ F < M-1, 1>, 1, respectively carrying OUT subtraction and averaging to obtain crosstalk to the test pixel circuit with input of I < M-1> when the input of the left and right test pixel circuits is I <2>, and respectively carrying OUT subtraction and averaging on the output OUT _ R <2, 2>, OUT _ R <2, 4> … … R <2, M > and the output OUT _ F <2, 1> of the R <2, 2>, R <2, 4> … … OUT _ R <2, M > and the output OUT _ F <2, 1> of the F <2, 1>, so as to obtain crosstalk to the test pixel circuit with input of I <2> when the input of the left and right test pixel circuits is I < M-1 >; this is the next largest crosstalk.
The above processes are repeated until the output results of all the test pixel circuits in the row test pixel circuit array and the output results of the corresponding test pixel circuits in the reference group test pixel circuits are analyzed and compared, and finally the test evaluation of the crosstalk of the reading circuit facing different input signals can be completed.
(2) Method for testing integrity of signal in signal bus transmission process under different input faces of reading circuit
For the 1 st column test pixel circuit C <1, 1>, C <2, 1> … … C < N, 1> of the column test pixel circuit array, there is the largest input difference between the inputs thereof, I <1> and I < M >, i.e., C <1, 1>, C <2, 1> … … C < N, 1>, respectively. In the readout circuit, the input and the output of the effective pixel circuit have a linear relationship, and the same test pixel circuit as the effective pixel circuit also has the characteristic, so the output OUT _ C <1, 1> of C <1, 1>, C <2, 1> … … C < N, 1> is OUT _ C <2, 1>: … …: OUT _ C < N, 1>: 1: M: … …:1, and has the largest difference. Under the control of the row control logic unit of the readout circuit, the signals of the signal bus W <1> and the input of the corresponding column stage circuit are square wave signals and have the maximum swing amplitude.
For the 2 nd column test pixel circuit C <1, 2>, C <2, 2> … … C < N, 2> of the column test pixel circuit array, there is the next largest difference in input between I <2> and I < M-1>, i.e., C <1, 2>, C <2, 2> … … C < N, 2>, respectively. In a system such as a readout circuit, where the input and output of an active pixel circuit are linear, this feature is also present in the same test pixel circuit as the active pixel circuit, and thus C <1, 2>, C <2, 2> … … C < N, 2> is 2: M-1: … …:2, with the next largest difference. Under the control of the row control logic unit of the readout circuit, the signals of the signal bus W <1>, and the corresponding input of the column stage circuit are square wave signals and have the next largest swing amplitude.
By analogy, for the M/2 th column test pixel circuit C <1, M/2>, C <2, M/2> … … C < N, M/2> of the column test pixel circuit array, the inputs are I < M/2>, so that the signal of the signal bus W < M/2> and the input of the corresponding column stage circuit are direct current signals.
For the reference group test pixel circuit array, the array specification is M × 1, and the inputs of each test pixel circuit F <1, 1>, F <2, 1> … … F < M, 1> are I <1>, I <2> … … I < M >, so the signal of the signal bus W _ F and the input of the corresponding column-level circuit are approximate to a ramp signal, and the signal can be considered to be fully established in the signal bus.
Since the inputs of the 1 st and Mth test pixel circuits F <1, 1>, F < M, 1> of the reference group test pixel circuit array are I <1> and I < M > (each test pixel circuit in the reference group test pixel circuit array is the same as the test pixel circuit in the row test pixel circuit array), the integrity of the signal when the signal bus faces the square wave signal with the maximum swing can be obtained by comparing OUT _ C <1, 1>, OUT _ C <2, 1> … … OUT _ C < N, 1> with OUT _ F <1, 1> and OUT _ F < M, 1> respectively. Since the inputs of the 2 nd and M-1 th test pixel circuits F <2, 1>, F < M-1, 1> of the reference group test pixel circuit array are I <2> and I < M-1> (each test pixel circuit in the reference group test pixel circuit array is the same as the test pixel circuit in the row test pixel circuit array), the integrity of the signal bus facing the square wave signal of the next largest swing can be obtained by comparing OUT _ C <1, 2>, OUT _ C <2, 2> … … OUT _ C < N, 2> with OUT _ F <2, 1> and OUT _ F < M-1, 1> respectively.
The above processes are repeated until the output results of all the test pixel circuits in the column test pixel circuit array and the output results of the corresponding test pixel circuits in the reference group test pixel circuits are analyzed and compared, and finally the evaluation of the signal integrity of the reading circuit facing different input signals can be completed.
(3) Method for testing dynamic range and linearity of reading circuit
For the reference group test pixel circuit array, the array specification is M multiplied by 1, no other test pixel circuits and signals cause crosstalk to the reference group test pixel circuit array, the input of each test pixel circuit F <1, 1>, F <2, 1> … … F < M, 1> is I <1>, I <2> … … I < M >, the signal of the signal bus W _ F and the input of the corresponding column stage circuit are approximate to a ramp signal, and the signal can be considered to be fully established in the signal bus. Therefore, the influence of crosstalk and signal integrity is eliminated by analyzing the output of each test pixel circuit in the reference group test pixel circuit array. Because the input of the test current generation circuit is selected and the test current generation circuit is designed to make I <1> small enough, so that the output value of the test pixel circuit with I <1> as input reaches the minimum output value of the readout circuit after the current is integrated and amplified, and I < M > is large enough, so that the output value of the test pixel circuit with I < M > as input reaches the maximum output value of the readout circuit after the current is integrated and amplified, the dynamic range DR of the readout circuit can be obtained by taking the ratio of the outputs OUT _ F < M, 1> and OUT _ F <1, 1> of F < M, 1> and F <1, 1>, as shown in formula (1), in dB.
As the input of F <1, 1>, F <2, 1> … … F < M, 1> changes linearly, the output OUT _ F <1, 1>, OUT _ F <2, 1> … … OUT _ F < M, 1> is collected, a straight line is fitted through a least square method, and the degree of deviation of OUT _ F <1, 1>, OUT _ F <2, 1> … … OUT _ F < M, 1> from the straight line is obtained, so that the linearity of the reading circuit can be obtained.
The above test on crosstalk, signal integrity, dynamic range and linearity of the readout circuit can be completed only by performing data acquisition once on the outputs of the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array.
Compared with the existing built-in test circuit for the reading circuit of the infrared focal plane detector, the invention has the beneficial effects that:
(1) according to the invention, by introducing the row test pixel circuit array, the column test pixel circuit array, the reference group test pixel circuit array and the test current generation circuit, the performances of the read-out circuit in the aspects of crosstalk, signal integrity and the like can be conveniently tested and evaluated, and the traditional built-in test circuit and test method for the read-out circuit of the infrared focal plane detector cannot embody the performances of the read-out circuit in the aspects;
(2) the existing built-in test circuit for the reading circuit of the infrared focal plane detector needs to adjust the bias voltage outside a chip for many times by combining the working time sequence of the reading circuit for the performance test of the reading circuit in the aspects of dynamic range, linearity and the like, and collects output data for many times, so that the operation is complicated. The invention can complete the performance test of the dynamic range, the linearity and the like of the reading circuit only by one operation, thereby greatly improving the test efficiency.
The invention will be better understood from the following drawings in conjunction with the description of embodiments.
Drawings
FIG. 1: the working timing diagram of the reading circuit.
FIG. 2: the invention discloses a composition schematic diagram of a built-in test circuit for a focal plane infrared detector reading circuit.
FIG. 3: a schematic block diagram of one embodiment of the built-in test circuit of the present invention is shown, in which W _ R<1>～W _ R<M>Representing an array of row-test pixel circuitsM signal buses, W _ C<1>～W _ C<M>M signal buses, W, representing an array of column-test pixel circuits _ And F represents M signal buses of the reference group test pixel circuit array. RD<1>～RD<M>The M readout signals are generated by the row control logic circuit and are used for driving the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array;
FIG. 4: in fig. 3, the test current generating circuit diagram shows that Iref is the input current.
In the figure: the circuit comprises a 1-row test pixel circuit array, a 2-row test pixel circuit array, a 3-reference group test pixel circuit array, a 4-test current generating circuit, a 5-column circuit, a 6-multiplexer, a 7-row control logic circuit, an 8-effective pixel circuit array, a 401-input MOS (metal oxide semiconductor) transistor and a 402-output MOS transistor.
Detailed Description
The present invention will be described in further detail below by way of examples with reference to the accompanying drawings.
The invention relates to a built-in test circuit for an infrared detector reading circuit, which comprises a row test pixel circuit array, a column test pixel circuit array, a reference group test pixel circuit array and a test current generating circuit, wherein the block diagram of the test circuit is shown in figure 2.
Each of the test pixel circuits in the row test pixel circuit array 1, the column test pixel circuit array 2, and the reference group pixel circuit array 3 is completely the same as an effective pixel circuit of the readout circuit, and the test current generation circuit 4 provides an input signal for testing for each test pixel circuit (including the test pixel circuits of the row test pixel circuit array 1, the column test pixel circuit array 2, and the reference group pixel circuit array 3). The whole built-in test circuit finishes the reading of signals through circuit modules such as a row control logic circuit 7, a column level circuit 5, a multiplexer 6 and the like of a multiplexing reading circuit.
Fig. 3 shows an embodiment of the invention in combination with the existing column stage circuitry 5, multiplexer 6 and row control logic circuitry 7 of the read-out circuitry.
Wherein the row test pixel circuit array 1 is placed on the top of the effective pixel circuit array 8 of the readout circuit, the column test pixel circuit array 2 is placed on the left side of the effective pixel circuit array 8 of the readout circuit, and the reference group test pixel circuit array 3 is placed on the right side of the effective pixel circuit array 8 of the readout circuit. Each test pixel circuit in the row test pixel circuit array 1, the column test pixel circuit array 2, and the reference group row test pixel circuit array 3 is identical to an effective pixel circuit of the effective pixel circuit array 8, and according to different readout circuit designs, it can adopt DI, BDI, SFD, CTIA, and other injection-level circuits, and can adopt Global exposure (Global Shutter) or Rolling Shutter exposure (Rolling Shutter) and other structural designs. The test current generation circuit is implemented by a current mirror circuit, as shown in fig. 4, and includes an input MOS transistor 401 and M output MOS transistors 402, all of which operate in a saturation region and have the same channel length; the ratio of the channel width of the output MOS tube to the channel width of the input MOS tube is 1:1 and 1:2 … … 1: 1. The following formula (2) shows a current calculation formula of the MOS transistor in the saturation region, where μ is electron mobility, Cox is gate oxide thickness, Vth is threshold voltage of the MOS transistor, VGS is gate-source voltage of the MOS transistor, and W and L are channel width and length of the MOS transistor.
Mu and Cox are fixed values in a specific CMOS process, VGS and Vth of all transistors in the current mirror circuit are the same, so that the generated current I <1>: I <2>: I <3>: … … I < M > -1: 2:3: … … M, namely, linear current is generated. The current is used as the input of the test pixel circuit array to replace the photocurrent input of the detector.
The row test pixel circuit array is controlled by the existing row control logic circuit 7 of the reading circuit to be transmitted to a column-level circuit 5 which is composed of a column-level amplifier, a column-level ADC and the like through M signal buses W _ R <1> -W _ R < M > (the same column of test pixel circuits of the row test pixel circuit array multiplexes one signal bus) row by row; the column test pixel circuit array is controlled by the existing row control logic circuit 7 of the reading circuit to be transmitted to a column-level circuit 5 which is composed of a column-level amplifier, a column-level ADC and the like through M signal buses W _ C <1> -W _ C < M > (the same column test pixel circuit of the column test pixel circuit array multiplexes one signal bus) row by row; the reference group test pixel circuit array is transmitted to a column stage circuit 5 composed of a column stage amplifier, a column stage ADC and the like row by row through a signal bus W _ F under the control of an existing row control logic circuit 7 of a reading circuit; the outputs of the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array complete the transmission of signals to the outside of the chip through the existing column level circuit and the multiplexer of the multiplexing reading circuit. The column stage circuit 5 amplifies and converts the outputs of the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array, transmits the amplified and converted outputs to the multiplexer 6, and finally transmits the amplified and converted outputs to the outside of the chip. The external test system collects the output OUT _ R <1, 1-OUT _ R < M, N > of the row test pixel circuit array 1, the output OUT _ C <1, 1-OUT _ C < N, M > of the column test pixel circuit array 2 and the output OUT _ F <1, 1-OUT _ R < M, 1> of the reference group test pixel circuit array 3, and analyzes and compares the collected data to obtain the performance indexes of the read-OUT circuit, such as crosstalk facing different inputs, signal integrity, dynamic range, linearity and the like in the signal channel transmission process. The above analysis can be carried out by collecting the output of the whole built-in test circuit at one time.
Specifically, the method for testing crosstalk of the read-out circuit facing different inputs includes:
since the inputs of the adjacent test pixel circuits (R <1, 1>, R <1, 2> … … R <1, M > in the row test pixel circuit array in the 1 st row are I <1> and I < M >, respectively, that is, R <1, 1>, R <1, 2> … … R <1, M > have the largest input difference, R <1, 1>, R <1, 2> … … R <1, M > are integrated at the same time and read out signals at the same time under the control of the existing row control logic circuit of the readout circuit, the adjacent test pixel circuits in the 1 st row in the row test pixel circuit array have the largest crosstalk; in the row test pixel circuit array, the input of the adjacent test pixel circuits (R <2, 1>, R <2, 2> … … R <2, M >) in the 2 nd row are I <2> and I < M-1>, namely, the R <2, 1>, R <2, 2> … … R <2, M > have the second largest input difference, and under the control of the existing row control logic circuit of the readout circuit, the R <2, 1>, R <2, 2> … … R <2, M > are integrated at the same time and read out signals at the same time, so that the adjacent test pixel circuits in the 2 nd row in the row test pixel circuit array have the second largest crosstalk; by analogy, in the row test pixel circuit array, the inputs of all the test pixel circuits (R < M/2, 1>, R < M/2, 2> … … R < M/2, M >) in the M/2 th row are the same and are I < M/2>, so that no crosstalk exists between the adjacent test pixel circuits in the M/2 th row in the row test pixel circuit array.
By subtracting and averaging the outputs OUT _ R <1, 1>, OUT _ R <1, 3> … … OUT _ R <1, M-1> of R <1, 1>, R <1, 3> … … R <1, M-1> respectively with the output OUT _ F < M, 1> of the Mth test pixel circuit F < M, 1> of the reference group test pixel circuit array, the crosstalk to the test pixel circuit with input I < M > can be obtained when the input of the test pixel circuit on the left side and the right side is I <1>, by subtracting and averaging the outputs OUT _ R <1, 2>, OUT _ R <1, 4> … … OUT _ R <1, M > of R <1, 2>, R <1, 4> … … R <1, M > and the outputs OUT _ F <1, 1> of F <1, 1>, respectively, the crosstalk to the test pixel circuit with input I <1> when the input of the test pixel circuit on the left side and the right side is I < M > can be obtained; this is the maximum crosstalk. By subtracting and averaging the outputs OUT _ R <2, 1>, OUT _ R <2, 3> … … OUT _ R <2, M-1> of R <2, 1>, R <2, 3> … … R <2, M-1> and OUT _ F < M-1, 1> of F < M-1, 1>, respectively, the crosstalk to the test pixel circuit with input I < M-1> can be obtained when the input of the test pixel circuit on the left side and the right side is I <2>, by subtracting and averaging the outputs OUT _ R <2, 2>, OUT _ R <2, 4> … … OUT _ R <2, M > of R <2, 2>, R <2, 4> … … R <2, M > and the outputs OUT _ F <2, 1> of F <2, 1>, respectively, the crosstalk to the test pixel circuit with input I <2> can be obtained when the input of the test pixel circuit on the left side and the right side is I < M-1 >; this is the next largest crosstalk.
The above processes are repeated until the analysis and comparison of the output results of all the test pixel circuits in the row test pixel circuit array and the output results of the corresponding test pixel circuits in the reference group test pixel circuits are completed, and finally the crosstalk evaluation of the read-out circuit facing different input signals can be completed.
The integrity of the signal during the transmission of the signal bus is tested for different inputs to the sensing circuit as follows:
since the 1 st column test pixel circuit C <1, 1>, C <2, 1> … … C < N, 1> of the column test pixel circuit array has the largest input difference between the inputs thereof, I <1> and I < M >, i.e., C <1, 1>, C <2, 1> … … C < N, 1>, respectively. In the system of the readout circuit, the input and the output of the effective pixel circuit have a linear relationship, and the same test pixel circuit as the effective pixel circuit also has the characteristic, so that the output OUT _ C <1, 1> of C <1, 1>, C <2, 1> … … C < N, 1> OUT _ C <2, 1>: … …: OUT _ C < N, 1>: 1: M: … …:1 has the largest difference. Under the control of the row control logic unit of the readout circuit, the signals of the signal bus W _ C <1> and the input of the corresponding column stage circuit are square wave signals and have the maximum swing amplitude. For the 2 nd column test pixel circuit C <1, 2>, C <2, 2> … … C < N, 2> of the column test pixel circuit array, there is the next largest difference in input between I <2> and I < M-1>, i.e., C <1, 2>, C <2, 2> … … C < N, 2>, respectively. In a system such as a readout circuit, where the input and output of an active pixel circuit are linear, this feature is also present in the same test pixel circuit as the active pixel circuit, and thus C <1, 2>, C <2, 2> … … C < N, 2> is 2: M-1: … …:2, with the next largest difference. Under the control of the row control logic unit of the readout circuit, the signals of the signal bus W _ C <2> and the input of the corresponding column stage circuit are square wave signals and have the next largest swing amplitude. By analogy, for the M/2 th column test pixel circuit C <1, M/2>, C <2, M/2> … … C < N, M/2> of the column test pixel circuit array, the inputs are I < M/2>, so that the signal of the signal bus W _ C < M/2> and the input of the corresponding column stage circuit are direct current signals.
By comparing the outputs OUT _ C <1, 1>, OUT _ C <2, 1> … … OUT _ C < N, 1> of C <1, 1>, C <2, 1> … … C < N, 1> with the outputs OUT _ F <1, 1> and OUT _ F < M, 1> of the 1 st and Mth test pixel circuits F <1, 1> and F < M, 1> of the reference group test pixel circuit array, respectively, the integrity of the signal bus facing the square wave signal of the maximum swing can be obtained. By comparing OUT _ C <1, 2>, OUT _ C <2, 2> … … OUT _ C < N, 2> with the outputs OUT _ F <2, 1> and OUT _ F < M-1, 1> of the 2 nd and M-1 th test pixel circuits F <2, 1> and F < M-1, 1> of the reference group test pixel circuit array, respectively, the integrity of the signal bus facing the square wave signal of the second maximum swing can be obtained.
The above processes are repeated until the output results of all the test pixel circuits in the column test pixel circuit array and the output results of the corresponding test pixel circuits in the reference group test pixel circuits are analyzed and compared, and finally the evaluation of the signal integrity of the reading circuit facing different input signals can be completed.
The method for testing the dynamic range and the linearity of the reading circuit specifically comprises the following steps:
the input of each test pixel circuit F <1, 1>, F <2, 1> … … F < M, 1> of the reference group test pixel circuit array is I <1>, I <2> … … I < M >, I <1>, I <2>, I <3> and … … I < M > is 1:2:3: … … M. Because the input of the test current generating circuit is selected and the test current generating circuit is designed to make I <1> small enough, so that the output value of the test pixel circuit with I <1> as the input reaches the minimum output value of the reading circuit after the current is integrated and amplified, and I < M > is large enough, so that the output value of the test pixel circuit with I < M > as the input reaches the maximum output value of the reading circuit after the current is integrated and amplified, the dynamic range of the reading circuit can be obtained by substituting the outputs OUT _ F < M, 1> and OUT _ F <1, 1> of F < M, 1> and F <1, 1> into the formula (1). As the input of F <1, 1>, F <2, 1> … … F < M, 1> changes linearly, the output OUT _ F <1, 1>, OUT _ F <2, 1> … … OUT _ F < M, 1> is collected, a straight line is fitted through a least square method, and the degree of deviation of OUT _ F <1, 1>, OUT _ F <2, 1> … … OUT _ F < M, 1> from the straight line is obtained, so that the linearity of the reading circuit can be obtained.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (12)
1. The utility model provides an infrared focal plane detector reading circuit's built-in test circuit, infrared focal plane detector reading circuit includes effective pixel circuit array, its characterized in that:
the built-in test circuit comprises a row test pixel circuit array, a column test pixel circuit array, a reference group test pixel circuit array and a test current generation circuit;
the row test pixel circuit array is positioned in the row direction of the reading circuit, the array specification is M multiplied by N, and each test pixel circuit in the row test pixel circuit array is completely the same as an effective pixel circuit in the effective pixel circuit array;
the column test pixel circuit array is positioned in the column direction of the reading circuit, the array specification is NxM, and each test pixel circuit in the column test pixel circuit array is completely the same as an effective pixel circuit in the effective pixel circuit array;
the reference group test pixel circuit array is positioned around the reading circuit, the array specification is Mx 1, and each test pixel circuit in the reference group test pixel circuit array is completely the same as an effective pixel circuit in the effective pixel circuit array;
the input of the test current generating circuit is provided by the outside of the reading circuit, and M currents I <1> to I < M > are generated, and the M currents replace the photocurrent of the infrared detector to drive the row test pixel circuit array, the column test pixel circuit array and the reference group test pixel circuit array in a certain sequence;
the above-mentionedMAndNis an even number.
2. The built-in test circuit of claim 1, wherein:
the currents I <1> to I < M > sequentially drive the line test pixel circuit array from the Mth to 1 st test pixel circuits R < M, 1> to R <1, 1> of the 1 st column to the 1 st to Mth test pixel circuits R <1, N > to R < M, N > of the Nth column.
3. The built-in test circuit of claim 1, wherein:
the currents I <1> to I < M > sequentially drive the 1 st to Mth test pixel circuits C <1, 1> to C <1, M > to the Mth to 1 st test pixel circuits C < N, M > to C < N, 1> of the 1 st row in the column test pixel circuit array.
4. The built-in test circuit of claim 1, wherein:
the currents I <1> to I < M > sequentially drive the 1 st to Mth test pixel circuits F <1, 1> to F < M, 1> of the reference group test pixel circuit array.
5. The built-in test circuit according to any one of claims 1 to 4, wherein:
the I <1>: i <2>: … …: i < M > = 1:2: … …: and M.
6. The built-in test circuit of claim 5, wherein:
the test pixel circuit takes I <1> as input, and after the current is integrated and amplified, the output value reaches the minimum output value of the reading circuit;
the test pixel circuit takes I < M > as input, and after the current is integrated and amplified, the output value reaches the maximum output value of the reading circuit;
the I <1>: i < M > can cover the dynamic range of the sensing circuit.
7. The built-in test circuit according to any one of claims 1 to 4, wherein:
the polarity of the test pixel circuit array is any one of N-on-P, P-on-N and double colors;
the structure of the test pixel circuit array is any one of a 4T, CTIA structure and a current mirror structure;
the structure of the test pixel circuit array adopts global exposure or roller shutter door exposure design;
the test current generation circuit array comprisesM+1 MOS tubes in saturation state;
the test current generating circuit array is an NMOS tube or a PMOS tube according to different polarities of the detectors.
8. The test method of the built-in test circuit according to any one of claims 1 to 7, characterized in that:
including testing for crosstalk in the sense circuitry for different inputs, testing for integrity of signals during signal bus transmission in the sense circuitry for different inputs, and testing for dynamic range and linearity of the sense circuitry.
9. The method of testing of claim 8, wherein said testing of the sensing circuit for crosstalk at different inputs comprises:
in the row test pixel circuit array, the inputs of the adjacent test pixel circuits (R <1, 1>, R <1, 2> … … R <1, M) in the 1 st row are I <1> and I < M >, namely, the maximum input difference exists between R <1, 1>, R <1, 2> … … R <1, M >, and under the control of the existing row control logic circuit of the reading circuit, R <1, 1>, R <1, 2> … … R <1, M > are integrated at the same time and signal reading is carried out at the same time, so that the maximum crosstalk exists between the adjacent test pixel circuits in the 1 st row in the row test pixel circuit array;
in the row test pixel circuit array, the inputs of the adjacent test pixel circuits (R <2, 1>, R <2, 2> … … R <2, M >) in the 2 nd row are I <2> and I < M-1>, namely, the inputs of R <2, 1>, R <2, 2> … … R <2, M > have the second largest input difference, and under the control of the existing row control logic circuit of the readout circuit, R <2, 1>, R <2, 2> … … R <2, M > are integrated at the same time and read out signals at the same time, so that the adjacent test pixel circuits in the 2 nd row in the row test pixel circuit array have the second largest crosstalk;
by analogy, in the row test pixel circuit array, the inputs of all the test pixel circuits (R < M/2, 1>, R < M/2, 2> … … R < M/2, M >) in the M/2 th row are the same and are I < M/2>, so that no crosstalk exists between the adjacent test pixel circuits in the M/2 th row in the row test pixel circuit array;
the area array specification of the reference group test pixel circuit array is Mx 1, and the input of each test pixel circuit F <1, 1-F < M, 1> is I <1> -I < M > without other test pixel circuits and signals causing crosstalk;
the above processes are repeated until the output results of all the test pixel circuits in the row test pixel circuit array and the output results of the corresponding test pixel circuits in the reference group test pixel circuits are analyzed and compared, and finally the test evaluation of the crosstalk of the reading circuit facing different input signals can be completed.
10. The method of claim 8, wherein said testing the integrity of the sensing circuit during signal bus transmission in the face of different inputs comprises:
for the 1 st column test pixel circuit C <1, 1>, C <2, 1> … … C < N, 1> of the column test pixel circuit array, the inputs thereof are I <1> and I < M >, i.e., C <1, 1>, C <2, 1> … … C < N, 1>, respectively, with the largest input difference, and the outputs OUT _ C <1, 1> of the C <1, 1>, C <2, 1> … … C < N, 1> OUT _ C <1, 1: OUT _ C <2, 1: … …: OUT _ C < N, 1> = M: … …:1 with the largest difference; under the control of the existing row control logic unit of the readout circuit, the signals of the OUT _ C <1>, OUT _ C <2, 1> … … OUT _ C < N, 1> are sequentially transmitted to the column-level circuit through the signal bus W _ C <1> for further processing, and the signal of the signal bus W <1> and the input of the corresponding column-level circuit are square wave signals and have the maximum swing amplitude;
for the 2 nd column test pixel circuit C <1, 2>, C <2, 2> … … C < N, 2> of the column test pixel circuit array, the inputs thereof are I <2> and I < M-1>, i.e., C <1, 2>, C <2, 2> … … C < N, 2> have the next largest input difference therebetween; the C <1, 2>, C <2, 2> … … C < N, 2> = 2: M-1: … …:2, with the next largest difference; under the control of the existing row control logic unit of the readout circuit, the signals of the OUT _ C <1, 2>, OUT _ C <2, 2> … … OUT _ C < N, 2> are sequentially transmitted to the column-level circuit through the signal bus W <2> for further processing, and the signal of the signal bus W <1> and the input of the corresponding column-level circuit are square wave signals and have the next large swing amplitude;
by analogy, for the M/2 th column test pixel circuit C <1, M/2>, C <2, M/2> … … C < N, M/2> of the column test pixel circuit array, the input of the M/2 th column test pixel circuit is I < M/2>, and the signal of the signal bus W < M/2> and the input of the corresponding column level circuit are direct current signals;
for a reference group test pixel circuit array, the array specification is M multiplied by 1, the input of each test pixel circuit F <1, 1>, F <2, 1> … … F < M, 1> is I <1>, I <2> … … I < M >, the signal of the signal bus W _ F and the input of the corresponding column level circuit are approximate to a ramp signal, and the signal is fully established in the signal bus;
for the 2 nd column test pixel circuits C <1, 2>, C <2, 2> … … C < N, 2> of the column test pixel circuit array, the inputs are I <2> and I < M-1>, namely C <1, 2>, C <2, 2> … … C < N, 2> have the next largest input difference, and the C <1, 2> -C < N, 2> = 2: M-1-: 2 have the next largest difference; under the control of the existing row control logic unit of the readout circuit, OUT _ C <1, 2> -OUT _ C < N, 2> are sequentially transmitted to the column-level circuit through a signal bus W <2> for further processing, and the signal of the signal bus W <1> and the input of the corresponding column-level circuit are square wave signals and have secondary large swing amplitude;
by analogy, for the M/2 th column test pixel circuit C <1, M/2> to C < N, M/2> of the column test pixel circuit array, the input is I < M/2>, and the signal of the signal bus W < M/2> and the input of the corresponding column level circuit are direct current signals;
for the reference group test pixel circuit array, the array specification is M multiplied by 1, the input of each test pixel circuit F <1, 1-F < M, 1> is I <1> -I < M >, the signal of the signal bus W _ F and the input of the corresponding column level circuit are approximate to a ramp signal, and the signal is fully established in the signal bus.
11. The method of claim 8, wherein the method of testing the dynamic range of the readout circuitry comprises:
for a reference group test pixel circuit array, the array specification is M multiplied by 1, no other test pixel circuits and signals cause crosstalk to the reference group test pixel circuit array, the input of each test pixel circuit F <1, 1>, F <2, 1> … … F < M, 1> is I <1>, I <2> … … I < M >, the signal of the signal bus W _ F and the input of the corresponding column-level circuit are approximate to ramp signals, which shows that the signals are fully established in the signal bus, and the influence of crosstalk and signal integrity is eliminated in the analysis of the output of each test pixel circuit in the reference group test pixel circuit array;
the dynamic range DR (in dB) of the readout circuit is obtained by ratioing the outputs OUT _ F < M, 1> and OUT _ F <1, 1> of F < M, 1> and F <1, 1>:
12. the method of claim 11, wherein the method of testing linearity of the readout circuit comprises:
the linearity of the reading circuit can be obtained by fitting a straight line by a least square method and solving the degree of deviation of OUT _ F <1, 1>, OUT _ F <2, 1> … … OUT _ F < M, 1> from the straight line.
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