CN113321178B

CN113321178B - MEMS filter

Info

Publication number: CN113321178B
Application number: CN202110603290.9A
Authority: CN
Inventors: 周华芳
Original assignee: Chengdu Hiwafer Technology Co Ltd
Current assignee: Chengdu Hiwafer Technology Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2023-05-16
Anticipated expiration: 2041-05-31
Also published as: CN113321178A

Abstract

The invention discloses an MEMS filter, which belongs to the technical field of filters and comprises a substrate; the front and back surfaces of the substrate are sequentially grown with an isolation layer, a first DBR dielectric film, a sacrificial layer and a second DBR dielectric film; the front surface of the substrate is provided with an upper electrode and a lower electrode, the bottom of the upper electrode is contacted with the bottom layer film of the second DBR dielectric film on the front surface of the substrate, and the bottom of the lower electrode is contacted with the top layer film of the first DBR dielectric film on the back surface of the substrate; the sacrificial layer on the front side of the substrate is provided with a cavity, and the position of the second DBR dielectric film on the front side of the substrate corresponding to the cavity is a floating bridge area. The filter provided by the invention has a double-sided structure, so that the flatness of the device can be ensured, the warping of the device caused by a single-sided long film in the prior art is solved, meanwhile, the floating bridge area is a sealed closed-loop floating bridge, and compared with the existing hollow floating bridge, the structural strength is improved, and the rupture risk of a second DBR dielectric film on the front side of the substrate is reduced.

Description

MEMS filter

Technical Field

The invention relates to the technical field of filters, in particular to an MEMS filter.

Background

The MEMS filter has the characteristics of large tunable range, high fineness and wide free spectrum area, and has wider application in the fields of radio communication and optical fiber communication. The filter generally comprises a substrate with a bragg mirror attached to it, and two electrodes attached to the bragg mirror. The cavity length tuning of the filter is generally realized by driving an upper layer reflecting mirror (Bragg reflecting mirror) of the filter to move downwards through static electricity or micro-electromagnetic so as to change the cavity length of the filter, thereby achieving the purpose of tuning resonance wavelength and frequency selection.

In order to further increase the tuning range of the filter, the prior art introduces a cantilever beam structure with large deformation in the filter, after two electrodes of the filter are electrified, one or more cantilever beams are elastically deformed and drive one Bragg reflector to move in the direction perpendicular to the other Bragg reflector, so that the cavity length of a resonant cavity is changed, and the tunable function of the filter is realized. Although the filter structure well changes the cavity length of the resonant cavity, the bottom of the cantilever beam is hollowed out with a larger area, so that the filter structure is extremely easy to crack in the deformation process and has poor structural strength; further, to ensure the device performance of the filter, it is necessary to ensure the flatness of the device, and how to prevent the device from warping is a technical problem to be solved.

Disclosure of Invention

The invention aims to solve the problems of poor structural strength and easiness in warping of the existing MEMS filter and provides the MEMS filter.

The aim of the invention is realized by the following technical scheme: a MEMS filter comprising a substrate;

the front and back surfaces of the substrate are sequentially grown with an isolation layer, a first DBR dielectric film, a sacrificial layer and a second DBR dielectric film;

the front surface of the substrate is provided with an upper electrode and a lower electrode, the bottom of the upper electrode is contacted with the bottom layer film of the second DBR dielectric film on the front surface of the substrate, and the bottom of the lower electrode is contacted with the top layer film of the first DBR dielectric film on the back surface of the substrate;

The sacrificial layer on the front side of the substrate is provided with a cavity, and the position of the second DBR dielectric film on the front side of the substrate corresponding to the cavity is a floating bridge area.

In one example, the first DBR dielectric film includes polysilicon layers and silicon nitride layers alternately arranged; the second DBR dielectric film comprises polycrystalline silicon layers and silicon nitride layers which are alternately arranged; the sacrificial layer is a silicon dioxide layer.

In an example, a top layer film of the first DBR dielectric film on the front surface of the substrate is a heavily doped first electrode conductive layer; and/or the number of the groups of groups,

and the bottom layer film of the second DBR dielectric film on the front surface of the substrate is a second electrode conducting layer subjected to heavy doping treatment.

In an example, a first alignment mark and a second alignment mark are arranged on the sacrificial layer on the front surface of the substrate, the first alignment mark is used for alignment when the back hole is formed on the back surface of the substrate, and the second alignment mark is used for alignment when the middle sacrificial layer is removed.

In an example, the sacrificial layer on the front surface of the substrate is fabricated with an annular first concave portion or an annular first convex portion, so that the second DBR dielectric film grown on the sacrificial layer forms an annular concave-convex portion that is convex downward and concave upward corresponding to the position of the annular first concave portion, or the second DBR dielectric film grown on the sacrificial layer forms an annular concave-convex portion that is concave downward and convex upward corresponding to the position of the annular first convex portion, and the annular concave-convex portion is used as an annular rupture preventing beam.

In an example, the annular rupture prevention beam is a plurality of hollow concentric cylinders or a plurality of hollow concentric polygonal prisms, and adjacent cylinders or adjacent prisms are closely stacked to form annular concave-convex portions or convex-concave portions.

In one example, the substrate back surface has a back hole made from the second DBR dielectric film of the substrate back surface to the first DBR dielectric film of the substrate back surface, and the second DBR dielectric film surface non-back hole region of the substrate back surface has a metal reflective layer.

In an example, the floating bridge region of the second DBR dielectric film has a release aperture, the bottom of the release aperture residing in the sacrificial layer on the front side of the substrate.

In an example, the second DBR dielectric film floating bridge region has a plurality of release holes, and the adjacent release holes are distributed with an equidistant offset.

In an example, an upper and lower electrode barrier strip is provided at the periphery of the lower electrode, and the upper and lower electrode barrier strip stays on the surface of the first DBR dielectric film on the front surface of the substrate.

It should be further noted that the technical features corresponding to the above options may be combined with each other or replaced to form a new technical scheme.

Compared with the prior art, the invention has the beneficial effects that:

(1) In an exemplary embodiment of the invention, the filter has a double-sided structure, so that the flatness of the device can be ensured, the warping of the device caused by a single-sided long film in the prior art is solved, and meanwhile, the floating bridge area is a sealed closed-loop floating bridge, so that the structural strength is improved, and the rupture risk of a second DBR dielectric film on the front side of the substrate is reduced compared with the existing hollowed floating bridge.

(2) In an exemplary embodiment of the present invention, the annular anti-cracking beam structure can provide a rebound traction force for the floating bridge of the second DBR dielectric film during the downward deformation of the second DBR dielectric film, so as to enhance the toughness of the whole floating bridge, and the floating bridge is less prone to cracking.

Drawings

The following detailed description of the present invention is further detailed in conjunction with the accompanying drawings, which are provided to provide a further understanding of the present application, and in which like reference numerals are used to designate like or similar parts throughout the several views, and in which the illustrative examples and descriptions thereof are used to explain the present application and are not meant to be unduly limiting.

FIG. 1 is a schematic diagram of a filter device in an example of the invention;

FIG. 2 is a schematic diagram of a substrate and alignment marks according to an example of the present invention;

FIG. 3 (a) is a schematic diagram of a front alignment mark in an example of the invention;

FIG. 3 (b) is a schematic diagram of a backside alignment mark in an example of the invention;

FIG. 4 is a schematic view of an annular burst beam formed in accordance with an example of the present invention;

FIG. 5 is a schematic diagram of a floating bridge region in an example of the invention;

FIG. 6 is a top view of a floating bridge region in an example of the invention;

FIG. 7 is a schematic view of a release hole in an example of the invention;

FIG. 8 is a schematic diagram of a floating bridge region in an example of the invention;

FIG. 9 is a flow chart of a method in an example of the invention;

FIG. 10 is a schematic illustration of a front-side and back-side growth of a first DBR dielectric film on a substrate in an example of the invention;

FIG. 11 is a schematic illustration of a front and back side growth sacrificial layer of a substrate in an example of the invention;

FIG. 12 (a) is a schematic view of an annular first recess formed in an example of the present invention;

FIG. 12 (b) is a schematic view of an annular first protrusion according to an example of the present invention;

FIG. 13 is a schematic view of an example of an annular rupture prevention beam made in accordance with the present invention;

FIG. 14 is a schematic diagram of a back hole fabricating process step S11 according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a back hole manufacturing process step S12 according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a back hole fabricating process step S13 according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of a back hole fabricating process step S13 according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a back hole manufacturing process step S15 according to an embodiment of the present invention;

FIG. 19 is a schematic diagram of a back hole manufacturing process step S16 according to an embodiment of the present invention;

FIG. 20 is a schematic diagram of a metal reflective layer fabricated according to an example of the present invention;

FIG. 21 is a schematic diagram of an upper electrode hole made in accordance with an example of the present invention;

FIG. 22 is a schematic diagram of a bottom electrode hole made in accordance with an example of the present invention;

FIG. 23 is a diagram of upper and lower electrode holes in an example of the invention;

FIG. 24 is a schematic view of a floating bridge formation region in accordance with an example of the present invention;

FIG. 25 is a schematic illustration of forming a metal protection layer in an example of the present invention;

FIG. 26 is a schematic illustration of forming a second photoresist layer in accordance with an embodiment of the present invention.

In the figure: 1-substrate, 2-isolation layer, 3-first DBR dielectric film, 4-sacrificial layer, 5-second DBR dielectric film, 6-polysilicon layer, 7-silicon nitride layer, 8-contact layer, 9-first photoresist layer, 10-first sharp corner, 11-cavity, 12-annular first concave portion, 13-annular first convex portion, 14-floating bridge region, 141-release hole, 142-annular fracture prevention beam, 15-upper electrode hole, 16-lower electrode hole, 17-upper electrode, 18-lower electrode, 20-metal protection layer, 21-second photoresist layer, 25-metal reflective layer, 26-upper and lower electrode blocking ring, 27-alignment mark pair, 27 a-first alignment mark, 27 b-second alignment mark.

Detailed Description

The following description of the embodiments of the present invention will be made apparent and fully understood from the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be noted that directions or positional relationships indicated as being "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are directions or positional relationships described based on the drawings are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

Example 1

As shown in fig. 1, in embodiment 1, a MEMS filter, the structure of which specifically includes a substrate 1; the front and back surfaces of the substrate 1 are sequentially grown with an isolation layer 2, a first DBR dielectric film 3, a sacrificial layer 4 and a second DBR dielectric film 5; the front surface of the substrate 1 is provided with an upper electrode 17 and a lower electrode 18, the bottom of the upper electrode 17 is contacted with the bottom layer film of the second DBR dielectric film 5 on the front surface of the substrate 1, and the bottom of the lower electrode 18 is contacted with the top layer film of the first DBR dielectric film 3 on the back surface of the substrate 1; the sacrificial layer 4 on the front side of the substrate 1 is provided with a cavity 11, and the position of the second DBR dielectric film 5 on the front side of the substrate 1 corresponding to the cavity 11 is a floating bridge region 14.

In an example, the substrate 1 is a double polished circular wafer silicon wafer, the wafer thickness is 400 μm, and in other exemplary embodiments, the substrate 1 may be a substrate 1 of other materials, and other shapes of the substrate 1 may be selected, as long as the MEMS filter can be implemented.

In one example, the isolation layer 2 is made of SiO ₂ The thickness is 200-400nm, and the refractive index is 1.46+/-0.03. The sacrificial layer 4 is a silicon dioxide layer with a thickness of about 1-3 μm and a refractive index in the range of 1.46 + -0.03.

In an example, the first DBR dielectric film 3 includes polysilicon layers 6 (Poly Si) (shown as a diagonal line from lower left to upper right in the drawing) and silicon nitride layers 7 (shown as a diagonal line from upper left to lower right in the drawing) alternately arranged, and the second DBR dielectric film 5 includes polysilicon layers 6 and silicon nitride layers 7 alternately arranged. More specifically, the thickness of the polysilicon layer 6 is 80-200nm, and the refractive index range is 3.48+ -0.03; the thickness of the silicon nitride layer 7 is 150-400nm, and the refractive index range is 2.0+/-0.03.

In an example, the first DBR dielectric film 3 includes seven layers, namely, a polysilicon layer 6 (i.e., a contact layer 8), a silicon nitride layer 7, a polysilicon layer 6, a silicon nitride layer 7, and a polysilicon layer 6 in order from the direction approaching the substrate 1 to the direction separating from the substrate 1, wherein the top layer film (polysilicon layer 6) of the first DBR dielectric film 3 is heavily doped with B ⁺ Or P ⁺ A treated first electrode conductive layer with ion doping concentration range of 10 ¹⁴ -10 ¹⁶ 。

In an example, the second DBR dielectric film 5 includes six layers, namely, a polysilicon layer 6, a silicon nitride layer 7, a polysilicon layer 6, and a silicon nitride layer 7 in order from the direction approaching the substrate 1 to the direction separating from the substrate 1, wherein the bottom layer film (polysilicon layer 6) of the first DBR dielectric film 3 is heavily doped with B ⁺ Or P ⁺ A treated first electrode conductive layer with ion doping concentration range of 10 ¹⁴ -10 ¹⁶ 。

Compared with the single Poly layer in the prior art, the first DBR dielectric film 3 and the second DBR dielectric film 5 of the present application are realized by multiple layers, the antireflection effect of the multilayer film structure on the light wavelength is better, and the anti-cracking effect of the annular anti-cracking beam 142 can be further improved, because each layer comprises a concave surface and a convex surface.

In an example, the front sacrificial layer 4 of the substrate 1 is provided with a first alignment mark 27a and a second alignment mark 27ab, wherein the first alignment mark 27a is used for aligning the manufacturing process of the front surface of the substrate, and the second alignment mark is used for aligning the manufacturing process of the back surface of the substrate, and is mainly used for a back hole process of the back surface of the substrate 1 and manufacturing the metal reflecting layer 35. The first alignment mark 27a and the second alignment mark 27b form an alignment mark pair 27, the first alignment mark 27a and the second alignment mark 27b in the alignment mark pair 27 are not overlapped, as shown in fig. 2, two alignment mark pairs 27 are arranged on the sacrificial layer 4 on the front surface of the wafer, and the two alignment mark pairs 27 are symmetrically arranged on two sides of the wafer. More specifically, as shown in fig. 3 (a), the first alignment marks 27a include a lateral array wire frame alignment mark provided at the upper left corner and the lower right corner, respectively, and a longitudinal array wire frame alignment mark provided at the lower left corner and the upper right corner, respectively; as shown in FIG. 3 (b), the second alignment mark 27ab comprises a cross alignment mark and a rectangular alignment mark, and the alignment mark occupies a small wafer area of about 2mm ² . It should be further noted that, in the filter device of the present application, each film layer is a transparent dielectric film, and each film layer is thinner, so after the first alignment mark 27a and the second alignment mark 27ab are manufactured, the corresponding alignment marks can still be observed in the subsequent front side process and back side process.

In an example, the sacrificial layer 4 on the front surface of the substrate 1 is fabricated with a first annular concave portion 12 or a first annular convex portion 13, so that the second DBR dielectric film 5 grown on the sacrificial layer 4 forms a concave-down annular concave-convex portion corresponding to the first annular concave portion 12, or the second DBR dielectric film 5 grown on the sacrificial layer 4 forms a concave-down convex annular concave-convex portion corresponding to the first annular convex portion 13, and the annular concave-convex portion serves as an annular rupture preventing beam 142. As an option, the annular first recess 12 comprises a plurality of circles of horizontal grooves and the annular first protrusion 13 comprises a plurality of circles of horizontal protrusions. One of the upper and lower surfaces of the annular rupture prevention beam 142 is concave (having a plurality of grooves), and the other surface is convex (having a plurality of protrusions). In one example, the annular rupture prevention beam 142 is concave on the upper side (away from the substrate 1) and convex on the lower side (toward the substrate 1); in another example, the annular rupture prevention beam 142 is convex on the upper side (away from the substrate 1) and concave on the lower side (toward the substrate 1).

In addition, when the embodiment in which the upper surface (away from the substrate 1) of the annular rupture prevention beam 142 is concave and the lower surface (toward the substrate 1) is convex as shown in fig. 4 is adopted, the contact between the first DBR dielectric film 3 and the second DBR dielectric film 5 can be changed from the surface contact to the point contact, and the floating bridge region 14 of the second DBR dielectric film 5 is less likely to adhere to the first DBR dielectric film 3 due to electrostatic adsorption by the point contact, so that the risk of rupture of the floating bridge region 14 can be further reduced.

More preferably, in an exemplary embodiment, the annular rupture prevention beam 142 divides the pontoon area 14 into at least two sub-areas. In particular, this way it is possible to have the effect that the entire pontoon area 14 has a reduced risk of rupture of the pontoon area 14. As shown in fig. 5, the top view of the floating bridge region 14 formed by the release holes 141 is circular, and the annular rupture preventing beams 142 are hollow concentric cylinders, adjacent cylinders are closely stacked to form annular concave-convex portions, the concentric cylinders divide the floating bridge region 14 into an inner ring and an outer ring, so that the entire floating bridge region 14 can be subjected to the annular rupture preventing beams 142. More specifically, FIG. 6 is a top plan view block diagram of a MEMS filter, the device being of a square configuration with dimensions L ranging from 2000-3000 μm; the outer diameter R1 of the pontoon region 14 ranges from 1500-1700 μm; the annular anti-cracking beams 142 are composed of 3-6 concentric cylinders, the outer diameter R2 of the outermost ring ranges from 1000 μm to 1200 μm, as shown in FIG. 7, the width d3 of each annular anti-cracking beam 142 ranges from 3 μm to 6 μm, the distance d4 between the annular anti-cracking beams 142 ranges from 10 μm to 15 μm, and the depth of the entire annular anti-cracking beam 142 penetrating through the second DBR dielectric film 5 ranges from 50 nm to 200nm. When the structure of this exemplary embodiment is adopted, in the actual working process of the filter, the inside of the annular anti-cracking beam 142 is a working plane, the parallelism is good, the area of the annular anti-cracking beam 142 is similar to a series of micro springs (similar to trampoline), the toughness of the whole floating bridge area 14 can be enhanced, the floating bridges on the two sides of the annular anti-cracking beam 142 are connected, so that the connection is firmer, the floating bridge area 14 is not easy to crack, that is, the floating bridge area 14 cannot float up and down due to the driving of electrostatic force, so that the floating bridge area 14 is not cracked. In another example, as shown in fig. 8, the floating bridge region 14 formed by the release holes 141 has a circular shape in plan view, and the annular rupture prevention beam 142 is a plurality of hollow concentric regular hexagonal prisms, and adjacent prisms are stacked and arranged to form an annular concave-convex portion.

In one example, the floating bridge region 14 has release holes 141, the bottoms of which 141 reside in the sacrificial layer 4 on the front side of the substrate 1. The electrode area of the device is spaced from the etched aperture at the edge of the floating bridge area 14 by a distance of 200-400 um, preferably 400 um, which is too close to cause the metal electrode to be etched during etching. As shown in fig. 8, the radius r1 of the release holes 141 is 1.5-2.5 μm, and the adjacent release holes 141 are distributed at equal intervals in a staggered manner, so that the etching solution entering the sacrificial layer 4 through the release holes 141 can be ensured to uniformly and fully release the sacrificial layer 4, the manufacturing accuracy of the device is ensured, the performance of the device is further ensured, and the distance d3 between the release holes 141 in the embodiment is 15-25 μm.

In an example, the back surface of the substrate 1 has a back hole made from the second DBR dielectric film 5 on the back surface of the substrate 1 to the first DBR dielectric film 3 on the back surface of the substrate 1, and a non-back hole region of the second DBR dielectric film 5 on the back surface of the substrate 1 has a metal reflective layer 25. Specifically, the back hole size is 650-850 μm, and the metal reflecting layer 25 is any one of aluminum, titanium, silver, platinum, and other materials. It should be further noted that, in the present invention, the back hole area on the back surface of the wafer is opposite to the cavity of the sacrificial layer on the front surface of the wafer, and is a transmission channel for light wavelength, and the transmission channel and the metal reflection layer on the back surface of the wafer are both configured to enable the light wavelength to pass through the light wavelength transmission channel to the maximum extent, so as to ensure the filtering performance of the filter.

In an example, the upper electrode 17 and the lower electrode 18 are preferably metal aluminum or gold, the upper electrode 17 is connected to the bottom polysilicon layer 6 (second electrode conductive layer) of the second DBR dielectric film 5 on the front surface of the substrate 1, and the lower electrode 18 is connected to the top polysilicon layer 6 (first electrode conductive layer) of the first DBR dielectric film 3 on the front surface of the substrate 1. As an option, the electrode portion (in a cylindrical shape) of the second DBR dielectric film 5 protruding from the front surface of the substrate 1 can cover the electrode connection hole digging region in a plan view, and in an example, as shown in fig. 4, the upper electrode 17 and the lower electrode 18 are uniform in size, and the electrode size r is in the range of 320-400 μm; the distance between the electrode part of the second DBR dielectric film 5 protruding from the front surface of the substrate 1 and the outer circle of the electrode hole is 40-80 mu m, and the electrode part of the second DBR dielectric film 5 protruding from the front surface of the substrate is 3.5-5 mu m.

In an example, the periphery of the lower electrode 18 is provided with an upper electrode 18 blocking hole and a lower electrode 18 blocking hole, the upper electrode 18 blocking hole and the lower electrode 18 blocking hole stay on the surface of the first DBR dielectric film 3 on the front surface of the substrate 1, and in this embodiment, the upper electrode 18 blocking hole and the lower electrode 18 blocking hole are upper electrode 18 blocking rings around the periphery of the lower electrode 18. The invention adopts the electrode blocking ring to cut the upper reflecting layer film around the lower electrode 18 around the metal of the lower electrode 18 to isolate the upper electrode 17 and the lower electrode 18, the blocking depth of the electrode blocking ring is required to be in the sacrificial layer 4, as shown in figure 4, the distance d2 between the inner diameter of the blocking ring of the upper electrode 18 and the outer diameter of the electrode is about 30-60 mu m, and the width of the blocking ring of the upper electrode 18 and the lower electrode 18 is about 5-10 mu m.

Based on the MEMS filter device structure, the invention further comprises a manufacturing method of the MEMS filter device, and the method specifically comprises the following steps:

as shown in fig. 9, in embodiment 1, a method for manufacturing a MEMS filter specifically uses a double-sided structure process to manufacture a filter specifically includes:

s1: an isolation layer 2, a first DBR dielectric film 3, a sacrificial layer 4 and a second DBR dielectric film 5 are sequentially grown on the front side and the back side of a substrate 1;

s2: manufacturing an upper electrode 17 and a lower electrode 18 on the front surface of the substrate 1, wherein the bottom of the upper electrode 17 is contacted with the bottom layer film of the second DBR dielectric film 5 on the front surface of the substrate 1, and the bottom of the lower electrode 18 is contacted with the top layer film of the first DBR dielectric film 3 on the front surface of the substrate 1;

s3: releasing the intermediate sacrificial layer 4 on the front side of the substrate 1 results in a sacrificial layer 4 with a cavity 11, the second DBR dielectric film 5 corresponding to the position of the cavity 11 being a floating bridge region 14.

In one exemplary embodiment, the substrate 1 is a 6 inch double polished circular wafer silicon wafer with a diameter of 150mm, while in other exemplary embodiments, the substrate 1 may be a substrate 1 of other materials, and other shapes of the substrate 1 may be selected, as long as a MEMS filter can be implemented.

In an example, the first DBR dielectric film 3 includes polysilicon layers 6 (Poly Si) (shown as a diagonal line from lower left to upper right in the drawing) and silicon nitride layers 7 (shown as a diagonal line from upper left to lower right in the drawing) alternately arranged, and the second DBR dielectric film 5 includes polysilicon layers 6 and silicon nitride layers 7 alternately arranged; the sacrificial layer 4 is a silicon dioxide layer.

In one example, as shown in FIG. 10, after wafer cleaning, a LPCVD tool is used to grow SiO2/Poly Si/SiN/Poly Si/SiN/Poly Si/SiN/Poly Si dielectric films on the front and back sides of the wafer simultaneously. According to the invention, the isolation layer 2 and the first DBR dielectric layer 3 are grown on the front side and the back side of the wafer at the same time, so that the flatness of the device can be ensured, and the warping of the device caused by single-sided film growth in the prior art is solved. It should be further noted that, in the process of manufacturing a device with a single-sided film, a substrate for preventing wafer warpage cannot be provided on the back of the wafer, because the flatness of the wafer before the film is not grown is relatively high, the wafer needs to be kept in a flat state all the time in the whole film growth process, if the substrate for preventing wafer warpage is provided on only one side of the wafer, that is, on the back of the wafer, the wafer is already warped after the film growth is completed, even if the wafer is subjected to a subsequent flattening process, the wafer cannot be restored to a flat state, and the film layer is easily broken due to stress influence caused by the subsequent flattening process, and the process of performing the flatness process on the wafer is quite limited and has an unsatisfactory effect due to extremely high temperature (800-1000 ℃) of the film growth process. It should be emphasized that in the process of growing the wafer multilayer film, the stress matching between the film layers is an important influence, the matching is improper, the film layers are broken because of the stress mismatch when the film growth process is not finished, and the film growth process cannot be completed.

In an example, after growing the first DBR dielectric film 3 on the front surface of the substrate 1, further comprises: and carrying out heavy doping treatment on the top layer film of the first DBR dielectric film 3 on the front surface of the substrate 1 to obtain a first electrode conducting layer, namely adopting an ion implantation machine to carry out heavy doping treatment on the top layer Poly Si of the DBR dielectric film, doping B+ or P+, and then annealing by using a rapid annealing process to improve the conductivity of the doped layer.

In one example, as shown in FIG. 11, a sacrificial layer SiO is formed on the front and back surfaces of a wafer by PECVD ₂ Compared with the second DBR dielectric film manufactured by high-temperature LPCVD, the PECVD manufacturing sacrificial layer has a faster etching rate, can well improve the etching selectivity between the sacrificial layer and the second DBR dielectric film 5 on the front surface of the wafer in the subsequent cantilever beam etching process of the sacrificial layer 4, and is convenient for manufacturing the subsequent floating bridge region process.

In an example, the preparation of the sacrificial layer 4 on the first DBR dielectric film 3 on the front and back sides of the substrate 1 further comprises: first alignment marks 27a and second alignment marks 27ab are prepared on the sacrificial layer 4 on the front surface of the substrate 1, wherein the first alignment marks 27a are used for aligning the manufacturing process of the front surface of the substrate, and the second alignment marks are used for aligning the manufacturing process of the back surface of the substrate, and are mainly used for a back hole process of the back surface of the substrate 1 and manufacturing the metal reflecting layer 35. The first alignment mark 27a and the second alignment mark 27b form an alignment mark pair 27, the first alignment mark 27a and the second alignment mark 27b in the alignment mark pair 27 are not overlapped, as shown in fig. 2, two alignment mark pairs 27 are arranged on the sacrificial layer 4 on the front surface of the wafer, and the two alignment mark pairs 27 are symmetrically arranged on two sides of the wafer. More specifically, as shown in fig. 3 (a), the first alignment marks 27a include a lateral array wire frame alignment mark provided at the upper left corner and the lower right corner, respectively, and a longitudinal array wire frame alignment mark provided at the lower left corner and the upper right corner, respectively; as shown in FIG. 3 (b), the second alignment mark 27ab comprises a cross alignment mark and a rectangular alignment mark, and the alignment mark occupies a small wafer area of about 2mm ² . It should be further noted that, in the filter device of the present application, each film layer is a transparent dielectric film, and each film layer is thinner, so after the first alignment mark 27a and the second alignment mark 27ab are manufactured, the front side process and the back side process are still performed subsequentlyThe corresponding alignment marks can be observed.

In an example, growing the second DBR dielectric film 5 on the front and back surfaces of the substrate 1 includes heavily doping the bottom film of the grown second DBR dielectric film 5 on the front surface of the substrate 1 to obtain the second electrode conductive layer. Specifically, poly Si is grown on the front side and the back side of the wafer at the same time by adopting a LAPECVD machine, ion implantation heavy doping B+ or P+ is carried out on the Poly Si film on the front side, and RTA rapid annealing is carried out on the wafer, so that the conductivity of the second electrode conductive layer is improved.

In one example, after the second electrode conductive layer is formed, an LPCVD method is used to sequentially form SiN/Poly Si/SiN/Poly Si/SiN dielectric films on the front and back surfaces of the wafer.

In an example, before the second DBR dielectric film 5 is prepared on the front side of the substrate 1, it further comprises:

an annular first concave portion 12 or an annular first convex portion 13 is formed on the sacrificial layer 4 on the front surface of the substrate 1, as shown in fig. 12 (a-b), so that an annular concave-convex portion is formed at a position corresponding to the annular first concave portion 12 of the second DBR dielectric film 5 grown on the sacrificial layer 4 (based on the film level of each layer in the second DBR dielectric film 5), or an annular concave-convex portion is formed at a position corresponding to the annular first convex portion 13 of the second DBR dielectric film 5 grown on the sacrificial layer 4, so that the annular concave-convex portion serves as an annular rupture preventing beam 142 as shown in fig. 1. As an option, the annular first recess 12 comprises a plurality of circles of horizontal grooves and the annular first protrusion 13 comprises a plurality of circles of horizontal protrusions. The annular rupture prevention beam 142 is located at each layer of the second DBR dielectric film 5 and includes a concave surface and a convex surface as shown in fig. 4 (only a case where an annular concave-convex portion, which is convex downward and concave upward, is formed at a position of the second DBR dielectric film 5 corresponding to the annular first concave portion 1232 is shown). More specifically, the second DBR dielectric film 5 grown on the sacrificial layer 4 may be grown using an LPCVD tool.

In an example, when the annular first recess 12 is formed, etching may be performed on the sacrificial layer 4 by dry etching; when the annular first protruding portion 13 is formed, a part of the sacrificial layer 4 may be grown more in a partially grown manner (any other realizable manner may be used, and the method is not limited herein).

More preferably, in an exemplary embodiment, the annular rupture prevention beam 142 divides the pontoon area 14 into at least two sub-areas. In particular, this way it is possible to have the effect that the entire pontoon area 14 has a reduced risk of rupture of the pontoon area 14. Wherein fig. 5 and 8 respectively show two exemplary embodiments thereof: as shown in fig. 5, the top view of the floating bridge region 14 formed by the release holes 141 is circular, the annular rupture preventing beams 142 are concentric cylinders, and adjacent cylinders are closely stacked to form annular concave-convex parts, and the concentric rings divide the floating bridge region 14 into an inner ring and an outer ring, so that the whole floating bridge region 14 can be acted by the annular rupture preventing beams 142; as shown in fig. 8, the floating bridge region 14 formed by the release holes 141 is circular in plan view, and the annular rupture prevention beam 142 is a plurality of hollow concentric regular hexagonal prisms, and adjacent prisms are stacked and arranged to form annular concave-convex portions.

When the structure of this exemplary embodiment is adopted, in the actual working process of the filter, the inside of the annular anti-cracking beam 142 is a working plane, the parallelism is good, the area of the annular anti-cracking beam 142 is similar to a series of annular micro springs distributed in a ring shape, the toughness of the whole floating bridge area 14 can be enhanced, the floating bridges on two sides of the annular anti-cracking beam 142 are connected, so that the connection is firmer, the floating bridge area 14 is not easy to crack, that is, the floating bridge area 14 cannot float up and down due to the driving of electrostatic force, so that the floating bridge area 14 is not cracked.

In an example, the second DBR dielectric film 5 is grown on the front and back sides of the wafer, and then the back hole of the filter device is formed, that is, the back hole is formed from the second DBR dielectric film 5 on the back side of the substrate to the first DBR dielectric film 3 on the back side of the substrate until the isolation layer 2 on the back side of the substrate is exposed. When etching is performed on multiple layers of different dielectric films, sharp angle influence caused by etching of the different dielectric films can be eliminated, the isolation layer 2 on the upper portion of the substrate is accurately etched, and the surface of the isolation layer 2 is kept smooth. Specifically, the back hole manufacturing process comprises the steps S11-S16:

s11: the first photoresist layer 9 of the back hole region is formed on the second DBR dielectric film 5 as shown in fig. 13 (only the front surface pattern of the wafer is illustrated in the back hole forming process, and the following description will be given). When the first photoresist layer 9 of the back hole area is manufactured, the first photoresist layer 9 is prepared in alignment with the first alignment mark, so that the manufacturing accuracy of the device is ensured.

In one exemplary embodiment, the thickness of the first photoresist layer 9 must be thick and resistant to dry and wet etching, and the thickness of the first photoresist layer is 5-20 μm, considering a subsequent multi-step etching process.

S12: the first dry etching is etched to the sacrificial layer 4 as shown in fig. 14.

More preferably, in an exemplary embodiment, the specific content of this step includes: the second DBR dielectric film 5 and the sacrificial layer 4 are dry etched using an ICP etching machine, and some sacrificial layer 4 remains when etching to the sacrificial layer 4, so that the first sharp angle 10 of the cumulative etching is included in the thickness of the remaining sacrificial layer 4.

When a thicker multilayer film is etched by dry method, particularly, the sacrificial layer 4 is thicker, sharp corners (first sharp corners 10 in this step) are easily formed due to the accumulated effect of etching during etching due to different etching rates of different film layers, and uneven etched surfaces are caused. In the process, each single-layer film layer of the multi-layer dielectric film (the step is the second DBR dielectric film 5) is thinner, the thickness is about 80-150nm, if the multi-layer dielectric film is etched directly by a dry method, sharp corners formed by etching easily penetrate through a single-layer dielectric film and cannot accurately stay on the surface of the isolation layer 2, so that some sacrificial layers 4 are purposely remained when the sacrificial layers 4 are etched, the first sharp corners 10 formed by accumulated etching are contained in the thickness of the remained sacrificial layers 4, and a flattening process (namely the next step) is performed in the middle of etching so as to reduce the sharp corner influence formed by accumulated etching effect.

More preferably, in an exemplary embodiment, in this step, the etching gas is CF ₄ &O ₂ The gas flow is 0-500sccm, the RF power of the upper electrode is 300-600W, the RF power of the lower electrode is 100-200W, and the process pressure is 10mtorr-1.5Par. The etching time can be appropriately adjusted according to the thickness of the etched sacrificial layer 4, and the residual thickness of the sacrificial layer 4 after etching is 500-1000 angstroms.

S13: the remaining sacrificial layer 4 is removed as shown in fig. 15.

The purpose of this step is to remove the remaining sacrificial layer 4 and to remove the sharp corner phenomenon (i.e. the first sharp corner 10) in the sacrificial layer 4 together, providing a planarized etching plane for the next dry etching.

More preferably, in an exemplary embodiment, said removing the remaining sacrificial layer 4 comprises: the remaining sacrificial layer 4, including sharp corners, is removed using a BOE solution to form a planarization plane.

If the thickness of the remaining sacrificial layer 4 is 500-1000 angstroms, the sacrificial layer 4 at the bottom of the back hole is etched clean to form a smooth plane by soaking in dilute BOE solution for about 5-10min, and the lateral etching to the sidewall is also small due to the short planarization process time (as shown in fig. 15).

S14: and a second dry etching, etching is stopped at the contact layer 8 of the first DBR dielectric film 3 in contact with the spacer layer 2, as shown in fig. 16. Wherein the contact layer 8 is a polysilicon layer 6;

Specifically, in this step, an ICP etching machine is used to etch the first DBR dielectric film 3 under the sacrificial layer 4 so that the etching stays in the polysilicon layer 6 (i.e., the contact layer 8) over the spacer layer 2. The dry etching in this step also forms sharp corners, but the sharp corners formed have a shallower depth due to the small overall thickness of the first DBR dielectric film 3 and the slow etching rate, and may be included in a single polysilicon layer 3.

More preferably, in an exemplary embodiment, in this step, the etching gas is CF ₄ &O ₂ The gas flow is 0-200sccm, the RF power of the upper electrode is 50-200W, the RF power of the lower electrode is 0-100W, and the process pressure is 10mtorr-1.5Par.

Specifically, according to the above exemplary embodiment, the first dry etching is a fast dry etching, and the second dry etching is a slow dry etching. The fast dry etching and the slow dry etching are determined by the flow of etching gas, the RF power of the upper electrode, the RF power of the lower electrode and the process pressure.

The first dry etching etches the upper multilayer film and etches into the sacrificial layer 4, the sacrificial layer 4 is thicker, the rapid dry etching is adopted, the etching rate is fast, the process time can be saved, the etching sharp angle brought by the rapid dry etching is deeper, but the etching sharp angle can be contained in the thicker sacrificial layer 4, so that the subsequent wet planarization process is not influenced. When the lower multilayer film is etched for the second time, because the thickness of each layer is thinner, the thickness of the whole film is thinner, rapid dry etching cannot be adopted, and only slow dry etching can be adopted, so that the formed etching sharp angle is shallower, and the etching sharp angle can be contained in the single-layer polycrystalline silicon film at the lowest layer, thereby facilitating the subsequent removal of polycrystalline silicon by TMAH and enabling the surface of the isolation layer 2 to be relatively flat.

S15: the remaining contact layer 8 is etched as shown in fig. 17.

More preferably, in an exemplary embodiment, the etching the remaining contact layer includes: the device is placed in a 15% -25% TMAH solution and soaked at 80 ℃ for 60-80s, so that polysilicon 6 (i.e. contact layer 8) on isolation layer 2 can be removed, leaving smooth isolation layer 2.

S16: the first photoresist layer 9 is removed as shown in fig. 18.

More preferably, in an exemplary embodiment, said removing the first photoresist layer 9 comprises:

s161: adopting an NMP solution flushing process to flush, wherein the flushing pressure is 300-1500Psi, and the flushing time is about 3-10min; s162: washing off excess NMP solution with IPA solution; s163: drying the device (a spin dryer, an oven or a nitrogen gun and the like); s164: and removing the first photoresist residues on the surface of the device by using an O2 ashing process.

In addition, the first dry etching cannot directly etch any layer in the first DBR dielectric film 3 layer below the sacrificial layer 4, so that the planarization meaning is lost, and the subsequent slow etching cannot planarize. Specifically: the sacrificial layer 4 is thickest and can be planarized by a wet process, which makes sense here and is also technically easy to implement. If placed below the sacrificial layer 4, the sharp corners penetrate several layers and wet planarization is not possible. The problem caused by the subsequent slow dry etch of sharp corners is even more serious.

In an example, as shown in fig. 19, after the back hole manufacturing process of the back surface of the wafer is completed, the method further includes manufacturing a metal reflective layer 25 on a non-hole digging area on the surface of the second DBR dielectric film 5 on the back surface of the wafer, where the metal reflective layer 25 is any one of materials such as aluminum, titanium, silver, and platinum.

In one example, the wafer front side upper electrode 17 and the wafer front side lower electrode 18 are fabricated after the back side metal reflective layer 25 is fabricated, specifically comprising steps S21-S23:

s21: hole digging treatment is carried out on the second DBR dielectric film 5 on the front surface of the wafer until the bottom layer film (the second electrode conductive layer) of the second DBR dielectric film 5 on the front surface of the substrate 1 is exposed, and a cylindrical upper electrode hole 15 is obtained as shown in FIG. 20;

s22: hole digging is carried out from the second DBR dielectric film 5 on the front surface of the wafer to the first DBR dielectric film 3 on the front surface of the wafer until the top layer film (the first electrode conducting layer) of the first DBR dielectric film 3 on the front surface of the substrate 1 is exposed, and a cylindrical lower electrode hole 16 is obtained as shown in fig. 21;

s23: the upper electrode hole 15 and the lower electrode hole 16 are respectively filled with a metal material and extended to protrude from the second DBR dielectric film 5 layer on the front surface of the substrate 1, as shown in fig. 22, to obtain an upper electrode 17 and a lower electrode 18. As an option, the electrode portion (in a cylindrical shape) of the second DBR dielectric film 5 layer protruding from the front surface of the substrate 1 can cover the electrode connection hole-digging region in a plan view.

In an example, releasing the intermediate sacrificial layer 4 on the front side of the substrate 1 in step S3 to obtain the sacrificial layer 4 with the cavity 11 specifically includes steps S31-S32:

s31: a release hole 141 is formed around the annular rupture prevention beam 142 of the second DBR dielectric film 5 on the front surface of the substrate 1, as shown in fig. 22; wherein the relief holes 141 are between about 1.5-3 μm in size and the hole-to-hole spacing is between about 10-30 μm; the etching solution is not easy to enter after the holes are too small, and the second DBR dielectric film 5 is not firm enough and is easy to damage after the holes are too large and are manufactured later; the hole spacing is too large, the sacrificial layer 4 is not easy to dig, the hole spacing is too small, the small holes are too dense, and the second DBR dielectric film 5 is easy to damage after manufacturing. The release holes 141 are formed in the form of dry etching. It should be noted that, the dry etching needs to reach a part of the sacrificial layer 4, the etching time can be properly adjusted according to the thickness of the sacrificial layer 4, the depth of the sacrificial layer 4 is deep, then the subsequent cavity 11 is made by wet etching, the side wall of the cavity 11 has a slope, the depth of the sacrificial layer 4 is shallow, and the side wall angle of the cavity 11 is straight during the subsequent etching, but at least the sacrificial layer 4500-1000 angstroms is needed.

S32: a cavity 11 is formed in the sacrificial layer 4 through the release hole 141, and a floating bridge region 14 is formed in the second DBR dielectric film 5 corresponding to the cavity 11, as shown in fig. 23.

When the structure of this exemplary embodiment is adopted, in the actual working process of the filter, the inside of the annular anti-cracking beam 142 is a working plane, the parallelism is good, the area of the annular anti-cracking beam 142 is similar to a series of micro springs (similar to trampoline), the toughness of the whole floating bridge area 14 can be enhanced, the floating bridges on the two sides of the annular anti-cracking beam 142 are connected, so that the connection is firmer, the floating bridge area 14 is not easy to crack, that is, the floating bridge area 14 cannot float up and down due to the driving of electrostatic force, so that the floating bridge area 14 is not cracked.

In an example, forming the release hole 141 around the annular anti-fracture beam 142 of the second DBR dielectric film 5 on the front side of the substrate 1 specifically includes:

s311: as shown in fig. 24 (only a wafer front side view is illustrated here), a metal protection layer 20 is formed on the second DBR dielectric film 5 on the wafer front side;

s312: as shown in fig. 25 (only a wafer front view is illustrated here), a second photoresist layer 219 is formed on the metal protection layer 20;

s313: as shown in fig. 26 (only a wafer front view is illustrated here), holes are opened in the photoresist layer 9, the metal protection layer 20, and the second DBR dielectric film 5 in order to form release holes 141;

s314: removing the second photoresist layer 219;

Specifically, since the scheme of step S32, i.e. "forming the cavity 11 in the sacrificial layer 4 through the release hole 141", is preferably implemented by wet etching (BOE solution), the metal electrodes (the upper electrode 17 and the lower electrode 18) are easily etched by the BOE solution due to their strong chemical activity (for example, when Al is used); the second DBR dielectric film 5 also has a risk of being etched by the BOE solution (especially in the case of the example embodiment described later, the uppermost layer is a silicon nitride film), so in this example embodiment, protection needs to be provided for the electrode and the second DBR dielectric film 5, otherwise damage to the electrode and the second DBR dielectric film 5 is easily caused during the process of manufacturing the cavity 11, and the performance of the product is affected.

The metal protection layer 20 in step S311 is preferably a gold layer, after the wafer is cleaned, a layer of pure gold is sputtered on the front surface of the wafer by using a magnetron sputtering machine, the thickness is 500-5000 angstrom, the gold layer is manufactured by using a sputtering mode, and metal can be sputtered on the side edge of the wafer to play a role in protecting the side edge of the wafer.

For step S312, when the etching hole photoresist layer is manufactured, the thickness of the photoresist and the etching selection ratio of the subsequent dry etching multilayer film need to be considered, the residual photoresist is ensured after the subsequent dry etching enters the sacrificial layer 4, and if the residual photoresist is not available, the electrode and the second DBR dielectric film 5 below the photoresist are etched after the photoresist is etched; if the photoresist layer 9 is too thick, the development of the etching holes is easily problematic, and the photoresist at the bottom of the etching holes cannot be completely developed, which affects the subsequent etching of the release holes 141.

For step S313, the gold layer at the release hole 141 is not removed before etching by several methods, and the gold layer needs to be etched by dry method in the dry etching process, the etching rate of the gold layer by dry method is low, the etching time is long, the photoresist is easy to be insufficient in step S312, and the gold particles on the wafer surface are easy to remain by dry etching, if the etching hole is blocked, the subsequent cavity 11 of the sacrificial layer 4 is affected, so the gold layer at the etching hole position needs to be removed first. In an exemplary embodiment, a diluted potassium iodide solution (1% -10% strength) is used to remove the gold layer at the location of the etch holes, the time being dependent on the gold layer thickness. Examples: a gold layer of 2000 a thickness is immersed in a dilute potassium iodide solution for about 7-8 seconds, the gold layer at the etched holes is etched clean, and the gold layer at the photoresist covered locations is not etched.

And (3) carrying out dry etching on the opening of the second DBR dielectric film 5 in the step S313, wherein an ICP etching machine is adopted, 2 radio frequency sources are arranged on the ICP etching machine, etching gas is CF4& O2, the gas flow is 0-2000sccm, the RF power of the ICP radio frequency source is 100-600W, the RF power of the bias radio frequency source is 0-200W, and the process pressure is 10mtorr-1.5Par. The etching time can be properly adjusted according to the thickness of the entering sacrificial layer 4, the depth of the entering sacrificial layer 4 is deep, the side wall of the cavity 11 has a gradient during subsequent wet etching, the depth of the entering sacrificial layer 4 is shallow, the side wall angle of the cavity 11 during subsequent etching is straight, but at least the entering sacrificial layer 4500-1000 angstroms is needed.

For the removal of the second photoresist layer 219 in step S314, an NMP solution rinse process at 80 ℃ is used, the rinse pressure is 300-1500Psi, the time is about 3-10min, the excess NMP solution is rinsed with IPA solution, and finally wafer is dried by a dryer, oven or nitrogen gun. And finally, removing photoresist residues on the surface of the wafer by adopting an O2 ashing process so as to prevent photoresist residues in the etching holes.

In one example, forming the cavity 11 in the sacrificial layer 4 through the release hole 141 specifically includes:

s321: immersing the device in BOE solution, and removing part of the sacrificial layer 4 by wet etching to form a cavity 11;

s322: and (5) after taking out, washing the excessive BOE solution by using deionized water. BOE solution concentration is 1% -10% for about 3-4 hours. In this process, the second DBR dielectric film 5 of the device is easily broken, and wet etching is performed in a still mild manner during etching, so that cleaning actions such as bubbling and shaking are strictly prohibited.

In an example, the via hole 141 further includes, after the sacrificial layer 4 forms the cavity 11:

s33: the metal cap layer 20 is removed. Specifically, the metal protection layer 20 (i.e., gold layer) at the position of the release hole 141 is removed, the excess BOE solution is rinsed with deionized water, and then diluted potassium iodide solution (1% -10% concentration) is added to remove the gold protection layer of the wafer, wherein the time depends on the thickness of the gold layer. After the gold layer is removed, the gold layer is put into deionized water solution for cleaning, and redundant potassium iodide solution is cleaned. And finally, adopting hot nitrogen to dry. The hot nitrogen drying temperature is not too high, the blow-drying air pressure is not too high, and the hot nitrogen drying temperature is 50-80 ℃ for about 5-10min.

In an example, step S31 forms a release hole 141 around the annular anti-fracture beam 142 of the second DBR dielectric film 5 on the front side of the substrate 1 while further comprising:

and forming isolation etching small holes on the periphery of the lower electrode 18 to remove the sacrificial layer 4 corresponding to the isolation etching small holes, so as to form upper and lower electrode 18 blocking holes, wherein the upper and lower electrode 18 blocking holes are upper and lower electrode 18 blocking rings in the embodiment.

It should be noted that, as an option, the order of fabricating the upper electrode 17 and the lower electrode 18 on the front surface of the wafer in step S2 and fabricating the intermediate sacrificial layer 4 on the front surface of the release liner 1 in step S3 may be changed, in which case, steps S31-S33 are repeated after the above two steps are completed to prepare the barrier ring for the upper electrode 18 and the lower electrode 18.

The MEMS filter device of the example is formed by matching the annular anti-cracking beam 142, the sealed closed-loop floating bridge and the like, so that the structural strength of the device is effectively improved, and the floating bridge region 14 is not cracked under 40V pressurization. Furthermore, the invention adopts LPCVD and PECVD to prepare the first DBR dielectric film 3, the second DBR dielectric film 5 and the middle sacrificial layer, combines the ion implantation process, the etching hole digging process, the metal evaporation process, the cavity structure manufacturing process and other process methods to realize the manufacture of the filter device, can be compatible with the existing semiconductor chip process, and reduces the cost of manufacturing the device.

The foregoing detailed description of the invention is provided for illustration, and it is not to be construed that the detailed description of the invention is limited to only those illustration, but that several simple deductions and substitutions can be made by those skilled in the art without departing from the spirit of the invention, and are to be considered as falling within the scope of the invention.

Claims

1. A MEMS filter, characterized by: comprises a substrate;

the sacrificial layer on the front side of the substrate is provided with a cavity, and the position of the second DBR dielectric film on the front side of the substrate corresponding to the cavity is a floating bridge area;

the first DBR dielectric film comprises polysilicon layers and silicon nitride layers which are alternately arranged; the second DBR dielectric film comprises polycrystalline silicon layers and silicon nitride layers which are alternately arranged; the sacrificial layer is a silicon dioxide layer;

the top layer film of the first DBR dielectric film on the front surface of the substrate is a first electrode conducting layer subjected to heavy doping treatment; and/or the number of the groups of groups,

The bottom layer film of the second DBR dielectric film on the front surface of the substrate is a second electrode conducting layer subjected to heavy doping treatment;

the sacrificial layer on the front surface of the substrate is provided with an annular first concave part or an annular first convex part, so that the second DBR dielectric film grown on the sacrificial layer forms an annular concave-convex part which is downwards convex and upwards concave corresponding to the annular first concave part, or the second DBR dielectric film grown on the sacrificial layer forms an annular concave-convex part which is downwards concave and upwards convex corresponding to the annular first convex part, and the annular concave-convex part is used as an annular anti-cracking beam.

2. A MEMS filter as claimed in claim 1, wherein: the sacrificial layer on the front side of the substrate is provided with a first alignment mark and a second alignment mark, wherein the first alignment mark is used for alignment when the back hole is formed in the back side of the substrate, and the second alignment mark is used for alignment when the middle sacrificial layer is removed.

3. A MEMS filter as claimed in claim 1, wherein: the annular anti-cracking beam is a plurality of hollow concentric cylinders or a plurality of hollow concentric polygonal prisms, and adjacent cylinders or adjacent prisms are closely laminated and arranged to form annular concave-convex parts.

4. A MEMS filter as claimed in claim 1, wherein: the back surface of the substrate is provided with a back hole which is formed from a second DBR dielectric film on the back surface of the substrate to a first DBR dielectric film on the back surface of the substrate, and a non-back hole area on the surface of the second DBR dielectric film on the back surface of the substrate is provided with a metal reflection layer.

5. A MEMS filter as claimed in claim 1, wherein: and the floating bridge region of the second DBR dielectric film is provided with a release hole, and the bottom of the release hole stays in the sacrificial layer on the front surface of the substrate.

6. A MEMS filter as defined by claim 5, wherein: the second DBR dielectric film floating bridge area is provided with a plurality of release holes, and the adjacent release holes are distributed in an equidistant staggered mode.

7. A MEMS filter as claimed in claim 1, wherein: and an upper electrode blocking belt and a lower electrode blocking belt are arranged on the periphery of the lower electrode, and the upper electrode blocking belt and the lower electrode blocking belt stay on the surface of the first DBR dielectric film on the front surface of the substrate.