CN113315519A - Successive comparison type analog-to-digital converter - Google Patents
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- CN113315519A CN113315519A CN202110649907.0A CN202110649907A CN113315519A CN 113315519 A CN113315519 A CN 113315519A CN 202110649907 A CN202110649907 A CN 202110649907A CN 113315519 A CN113315519 A CN 113315519A
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Abstract
The invention discloses a successive comparison analog-digital converter, belonging to the field of integrated circuit design, comprising: the first logic device of each stage comprises a first preceding-stage capacitor and a first redundant capacitor, one end of the first preceding-stage capacitor and one end of the first redundant capacitor are switched among a positive input signal, a reference voltage and a grounding end, and the other end of the first preceding-stage capacitor and one end of the first redundant capacitor are connected to a first node; each stage of the second logic device comprises a second pre-stage capacitor and a second redundant capacitor, one end of the second pre-stage capacitor and one end of the second redundant capacitor are switched among the negative input signal, the reference voltage and the grounding terminal, and the other end of the second pre-stage capacitor and the second redundant capacitor are connected to a second node; the comparator is used for comparing the voltage of the first node with the voltage of the second node. The invention has the beneficial effects that: a redundant capacitor is added to each stage of preceding stage capacitor, and successive approximation comparison is performed based on a binary search algorithm, so that the electric charge carried in each successive comparison period is equal to an ideal value, and the precision of the converter is improved.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a successive comparison analog-to-digital converter.
Background
Analog-to-Digital converters (ADCs) are indispensable conversion circuits in modern electronic systems, are front-ends of various Digital systems, and have a critical performance. With successive approximation register analog-to-digital converters (SAR ADCs) occupying a large portion of the medium to high resolution ADC market. The SAR ADC is widely used in low-power-consumption electronic devices due to its simple structure, few analog modules, small area, low power consumption, and benefit from a small-sized advanced integrated circuit process.
A successive approximation type analog-to-digital converter (SAR ADC) successively approximates the input analog signal based on a binary search algorithm,the internal part of the DAC is mostly a capacitor array which is used as a DAC of switchable voltage of a capacitor in a sampling stage and a successive comparison stage, and the DAC can be mainly divided into the sampling stage, a zero clearing stage and the successive comparison stage; due to the reference voltage V in the actual circuitrAnd GND are not ideal values, and the voltage is relatively stable all the time in the sampling and zero clearing stages; however, in the successive comparison stage, since the capacitor channels are all powered on to generate strong impulse response, which results in voltage reduction, directly reduces the decision accuracy of the comparator and the whole significant digit of the analog-to-digital converter, destroys the binary relation, reduces the accuracy of the converter, and seriously deteriorates the performance of the SAR ADC, there is a strong need to design a successive comparison analog-to-digital converter to meet the requirement of practical use.
Disclosure of Invention
The invention aims to provide a successive comparison analog-digital converter, which adds a redundant capacitor beside a preceding stage capacitor of a logic device, so that the electric charge quantity conveyed in each successive comparison period is equal to an ideal value, and the precision of the converter is improved.
The technical problem solved by the invention can be realized by adopting the following technical scheme:
the invention provides a successive approximation analog-to-digital converter, comprising:
a plurality of stages of first logic, each stage of the first logic including a first pre-capacitor and a first redundant capacitor, the first logic generating a first control signal under the action of a first comparison signal for controlling one end of the first pre-capacitor and the first redundant capacitor to switch among a positive input signal, a reference voltage and a ground terminal, the other end of the first pre-capacitor and the first redundant capacitor being connected to a first node;
a plurality of stages of second logic, each stage of the second logic including a second pre-capacitor and a second redundant capacitor, the second logic generating a second control signal under the action of a second comparison signal for controlling one end of the second pre-capacitor and the second redundant capacitor to switch among a negative input signal, the reference voltage and the ground terminal, the other end of the second pre-capacitor and the second redundant capacitor being connected to a second node;
and the comparator compares the voltage of the first node with the voltage of the second node and outputs the first comparison signal or the second comparison signal.
Preferably, each stage of the first logic and the second logic further includes:
and the control end is used for receiving the first comparison signal or the second comparison signal and generating the first control signal or the second control signal under the action of the first comparison signal or the second comparison signal.
Preferably, each stage of the first logic and the second logic further includes:
an enable terminal, configured to receive an enable signal of the first logic or the second logic of a previous stage;
and the output end is used for generating the enable signal while the control end outputs the first control signal or the second comparison signal, and outputting the enable signal to the enable end of the first logic device or the second logic device at the subsequent stage.
Preferably, the first logic or the second logic of a previous stage outputs a feedback signal to the first logic or the second logic of a previous stage at the same time when the first logic or the second logic of a subsequent stage outputs the enable signal;
and the first logic device or the second logic device of the previous stage receives the feedback signal and generates the first control signal or the second control signal under the action of the feedback signal.
Preferably, after receiving the feedback signal, the first logic or the second logic switches the first redundant capacitor from the reference voltage to the ground terminal under the action of the first control signal or the second control signal.
Preferably, the method further comprises the following steps:
and the switching device group is connected between a common-mode voltage and the comparator and used for controlling the successive comparison type analog-to-digital converter to be alternately switched between a sampling function mode and a successive comparison mode.
Preferably, the switching device group includes:
a first main switch connected between the common mode voltage and the first node;
a second main switch connected between the common mode voltage and the second node.
Preferably, a non-inverting input terminal of the comparator is connected to the first node, and an inverting input terminal of the comparator is connected to the second node.
Preferably, the first logic and the second logic are each a SAR logic circuit.
Preferably, when the voltage of the first node is greater than the voltage of the second node, the comparator outputs the first comparison signal;
when the voltage of the first node is smaller than the voltage of the second node, the comparator outputs the second comparison signal.
The technical scheme of the invention has the beneficial effects that:
the invention adds a redundant capacitor in the preceding stage capacitor of each stage of first logic device and each stage of second logic device, based on binary search algorithm successive approximation comparison, determines to control the first logic device or the second logic device according to the comparison signal output by the comparator, controls the preceding stage capacitor and the redundant capacitor corresponding to the first logic device or the second logic device to switch from the reference voltage to the grounding terminal, enables the next stage logic device, and controls the redundant capacitor of the previous stage logic device to switch from the grounding terminal to the reference voltage at the same time when the previous stage logic device enables the next stage logic device, so that the electric charge quantity carried in each successive comparison period is equal to an ideal value, thereby improving the precision of the converter.
Drawings
Fig. 1 is a circuit diagram of a successive approximation analog-to-digital converter according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The invention provides a successive approximation type analog-to-digital converter, belonging to the field of integrated circuit design, as shown in figure 1, comprising:
a plurality of stages of first logic devices (11#, 12#, 13# …), each stage of the first logic device including a first pre-stage capacitor and a first redundant capacitor, the first logic device generating a first control signal under the action of a first comparison signal for controlling one end of the first pre-stage capacitor and the first redundant capacitor to a positive input signal VinpA reference voltage VrThe other ends of the first pre-stage capacitor and the first redundant capacitor are connected to a first node;
multiple stages of second logic (21#, 22#, 23# …), each stage of the second logic including a second pre-capacitor and a second redundant capacitor, the second logic generating a second control signal under the action of a second comparison signal for controlling one end of the second pre-capacitor and the second redundant capacitor to a negative input signal VinnReference voltage VrThe other ends of the first pre-stage capacitor and the first redundant capacitor are connected to a first node;
a comparator 1 for comparing the voltage of the first node with the voltage of the second node and outputting a first comparison signal or a second comparison signal.
Specifically, in the present embodiment, the successive approximation analog-to-digital converter includes:
a plurality of first pre-stage capacitors (C11, C12, C13 …), one end of each first pre-stage capacitor is connected to the first node, and the other end of each first pre-stage capacitor is connected to the positive input signal V of the corresponding first logic deviceinpOr a reference voltage VrOr the ground terminal GND for controlling the first pre-stage capacitor to the positive input signal V under the first control signalinpReference voltage VrAnd the ground end GND;
a plurality of second pre-stage capacitors (C21, C22, C23 …), one end of each second pre-stage capacitor being connected to the second node, and the other end of each second pre-stage capacitor being connected to the negative input signal V of the corresponding second logic deviceinnOr a reference voltage VrOr ground terminal GND for controlling the second pre-stage capacitor to the negative input signal V under the second control signalinnReference voltage VrAnd the ground end GND;
further comprising: first redundancy capacitors (Δ C11, Δ C12, Δ C13 …) corresponding to the first pre-stage capacitors (C11, C12, C13 …), respectively, one end of each first redundancy capacitor being connected to the first node, and the other end of each first redundancy capacitor being controlled by a first control signal according to a positive input signal VinpOr a reference voltage VrOr the ground ends GND are switched;
second redundancy capacitors (Δ C21, Δ C22, Δ C23 …) corresponding to the second pre-stage capacitors (C21, C22, C23 …) one to one, one end of each of the second redundancy capacitors being connected to the second node, respectively, and the other end of each of the second redundancy capacitors being controlled by the second control signal in response to the negative input signal VinnOr a reference voltage VrOr the ground ends GND are switched;
a redundant capacitor is added beside each first preceding-stage capacitor and each second preceding-stage capacitor, the comparator 1 compares the voltage of the first node and the voltage of the second node in a successive approximation manner based on a binary search algorithm, and controls the switching of the capacitors according to an output comparison signal, so that the charge amount carried in each successive comparison period is equal to an ideal value, for example: the first stage carries a charge Q ═ C11 ═ V ═ (C11+ Δ C11) V ×. 0.9.
In order to overcome ADC reference voltage VrNon-ideal characteristics due to current surges during successive comparisons (e.g. V in first and second comparison stagesrFrom the ideal 1V down to 0.9V, 0.95V and back to 1V after the third and fourth stage comparisons), a redundant capacitor is added in each stage to make the total charge transferred equal to the ideal value (i.e. an extra ac to make up V is added to make up V)rAnd the ideal value 1V such that the total amount of Q ═ C × V remains constant).
As a preferred embodiment, each of the first logic and the second logic of each stage further includes:
and a control terminal J1, configured to receive the first comparison signal or the second comparison signal and generate the first control signal or the second control signal under the action of the first comparison signal or the second comparison signal.
Specifically, each stage of the first logic device further includes a control terminal J1 for receiving the first comparison signal and generating a first control signal under the action of the first comparison signal;
the second logic units also respectively include a control terminal J1 for receiving the second comparison signal and generating a second control signal under the action of the second comparison signal.
Further, the method also comprises the following steps:
one end of each upper level plate capacitor switch is correspondingly connected with the first preceding-stage capacitor or the first redundant capacitor, and the other end of each upper level plate capacitor switch is controlled by a first control signal to be in positive input signal VinpOr a reference voltage VrOr the ground ends GND are switched;
a plurality of lower plate capacitance switches, one end of each lower plate capacitance switch is correspondingly connected with the second front-stage capacitance or the second redundant capacitance, and the other end is controlled by the second control signal to be in the negative input signal VinnOr a reference voltage VrOr ground GND.
As a preferred embodiment, each of the first logic and the second logic of each stage further includes:
an enable terminal J3 for receiving an enable signal of the first logic or the second logic of the previous stage;
an output terminal J4 for generating an enable signal at the same time when the control terminal J1 outputs the first control signal or the second comparison signal, and outputting the enable signal to the enable terminal J3 of the first logic or the second logic of the next stage.
In a preferred embodiment, the previous stage first logic or second logic outputs a feedback signal to the previous stage first logic or second logic while outputting the enable signal to the next stage first logic or second logic;
the first logic device or the second logic device of the previous stage receives the feedback signal and generates a first control signal or a second control signal under the action of the feedback signal.
Specifically, the logic device outputs a control signal for controlling the capacitor switch and enables the next-stage logic device after receiving the comparison signal, and simultaneously outputs a feedback signal to the feedback terminal J2 from the previous-stage logic device, for example, when the comparator output is 1, i.e. the first comparison signal, and the logic device 12# receives the first comparison signal, outputs the first control signal to control the upper-stage plate capacitor switch corresponding to the capacitor C12 and the capacitor Δ C12 to be switched by the reference voltage VrSwitching to the ground terminal GND, enabling the next stage logic device 13#, and outputting the feedback signal to the previous stage logic device 11#, wherein the logic device 11# switches the upper stage plate capacitance switch corresponding to the corresponding capacitance Δ C11 from the ground terminal GND to the reference voltage V after receiving the feedback signal at the feedback terminal J2r。
In a preferred embodiment, the first logic device or the second logic device receives the feedback signal and then transfers the first redundant capacitor from the reference voltage V under the action of the first control signal or the second control signalrSwitched to ground GND.
As a preferred embodiment, the method further comprises:
and the switching device group is connected between a common-mode voltage and the comparator 1 and used for controlling the successive comparison analog-digital converter to be alternately switched between a sampling function mode and a successive comparison mode.
As a preferred embodiment, the switching device group includes:
a first main switch L1, the first main switch L1 connected between the common mode voltage Vcm and the first node;
a second main switch connected between the common mode voltage Vcm and the second node.
Further, when the successive approximation analog-to-digital converter is in the sampling function mode, the first main switch L1 and the second main switch L2 are both closed, and all the first pre-stage capacitors and all the first redundant capacitors are switched to the positive input signal VinpAll second pre-stage capacitors and all second redundant capacitors are switched to the negative input signal Vinn；
When the successive comparison type analog-to-digital converter is in the successive comparison mode, the first main switch L1 and the second main switch L2 are both turned off, all the pre-stage capacitors and the redundant capacitors are switched to be connected with the reference signal, and the first pre-stage capacitors and the first redundant capacitors are controlled by the first control signal to be connected with the reference voltage VrAnd the ground end GND; or controlling the second pre-stage capacitor and the second redundant capacitor to the reference voltage V under the second control signalrAnd ground GND.
In a preferred embodiment, the non-inverting input terminal of the comparator 1 is connected to the first node, and the inverting input terminal of the comparator 1 is connected to the second node.
As a preferred embodiment, when the voltage of the first node is greater than the voltage of the second node, the comparator 1 outputs a first comparison signal;
when the voltage of the first node is less than the voltage of the second node, the comparator 1 outputs a second comparison signal.
As a preferred embodiment, the first logic (11#, 12#, 13# …) and the second logic (21#, 22#, 23# …) are SAR logic circuits, respectively.
The technical scheme of the invention has the beneficial effects that:
the invention adds a redundant capacitor in the preceding stage capacitor of each stage of first logic device and each stage of second logic device, based on binary search algorithm successive approximation comparison, determines to control the first logic device or the second logic device according to the comparison signal output by the comparator, controls the preceding stage capacitor and the redundant capacitor corresponding to the first logic device or the second logic device to switch from the reference voltage to the grounding terminal, enables the next stage logic device, and controls the redundant capacitor of the previous stage logic device to switch from the grounding terminal to the reference voltage at the same time when the previous stage logic device enables the next stage logic device, so that the electric charge quantity carried in each successive comparison period is equal to an ideal value, thereby improving the precision of the converter.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A successive approximation analog-to-digital converter, comprising:
a plurality of stages of first logic, each stage of the first logic including a first pre-capacitor and a first redundant capacitor, the first logic generating a first control signal under the action of a first comparison signal for controlling one end of the first pre-capacitor and the first redundant capacitor to switch among a positive input signal, a reference voltage and a ground terminal, the other end of the first pre-capacitor and the first redundant capacitor being connected to a first node;
a plurality of stages of second logic, each stage of the second logic including a second pre-capacitor and a second redundant capacitor, the second logic generating a second control signal under the action of a second comparison signal for controlling one end of the second pre-capacitor and the second redundant capacitor to switch among a negative input signal, the reference voltage and the ground terminal, the other end of the second pre-capacitor and the second redundant capacitor being connected to a second node;
and the comparator compares the voltage of the first node with the voltage of the second node and outputs the first comparison signal or the second comparison signal.
2. A successive comparison analog-to-digital converter as claimed in claim 1, wherein each of said first logic and said second logic further comprises:
and the control end is used for receiving the first comparison signal or the second comparison signal and generating the first control signal or the second control signal under the action of the first comparison signal or the second comparison signal.
3. A successive comparison analog-to-digital converter as claimed in claim 2, wherein each of said first logic and said second logic further comprises:
an enable terminal, configured to receive an enable signal of the first logic or the second logic of a previous stage;
and the output end is used for generating the enable signal while the control end outputs the first control signal or the second comparison signal, and outputting the enable signal to the enable end of the first logic device or the second logic device at the subsequent stage.
4. A successive approximation analog-to-digital converter according to claim 3, wherein said first logic or said second logic of a preceding stage outputs a feedback signal to said first logic or said second logic of a preceding stage while said first logic or said second logic of a succeeding stage outputs said enable signal;
and the first logic device or the second logic device of the previous stage receives the feedback signal and generates the first control signal or the second control signal under the action of the feedback signal.
5. The successive approximation analog-to-digital converter of claim 4, wherein the first logic or the second logic switches the first redundant capacitor from the reference voltage to the ground terminal under the action of the first control signal or the second control signal after receiving the feedback signal.
6. A successive comparison analog-to-digital converter according to claim 1, further comprising:
and the switching device group is connected between a common-mode voltage and the comparator and used for controlling the successive comparison type analog-to-digital converter to be alternately switched between a sampling function mode and a successive comparison mode.
7. A successive comparison analog-to-digital converter according to claim 6, wherein said switching device group comprises:
a first main switch connected between the common mode voltage and the first node;
a second main switch connected between the common mode voltage and the second node.
8. A successive comparison analog-to-digital converter as claimed in claim 1, wherein a non-inverting input of said comparator is connected to said first node and an inverting input of said comparator is connected to said second node.
9. A successive approximation analog-to-digital converter as claimed in claim 1, wherein said first logic and said second logic are each SAR logic circuits.
10. A successive comparison analog-to-digital converter according to claim 1, wherein said comparator outputs said first comparison signal when the voltage of said first node is greater than the voltage of said second node;
when the voltage of the first node is smaller than the voltage of the second node, the comparator outputs the second comparison signal.
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